1 // SPDX-License-Identifier: GPL-2.0-only 1
2 /*
3 * First-level interrupt controller model for
4 *
5 * Copyright (c) 2010-2011, The Linux Foundati
6 */
7
8 #include <linux/interrupt.h>
9 #include <asm/irq.h>
10 #include <asm/hexagon_vm.h>
11
12 static void mask_irq(struct irq_data *data)
13 {
14 __vmintop_locdis((long) data->irq);
15 }
16
17 static void mask_irq_num(unsigned int irq)
18 {
19 __vmintop_locdis((long) irq);
20 }
21
22 static void unmask_irq(struct irq_data *data)
23 {
24 __vmintop_locen((long) data->irq);
25 }
26
27 /* This is actually all we need for handle_fa
28 static void eoi_irq(struct irq_data *data)
29 {
30 __vmintop_globen((long) data->irq);
31 }
32
33 /* Power mamangement wake call. We don't need
34 * if this is absent, then an -ENXIO error is
35 * msm_serial driver, and it fails to correctl
36 * This is a bug in the msm_serial driver, but
37 * work around it here, by providing this bogu
38 * XXX FIXME!!! remove this when msm_serial is
39 */
40 static int set_wake(struct irq_data *data, uns
41 {
42 return 0;
43 }
44
45 static struct irq_chip hexagon_irq_chip = {
46 .name = "HEXAGON",
47 .irq_mask = mask_irq,
48 .irq_unmask = unmask_irq,
49 .irq_set_wake = set_wake,
50 .irq_eoi = eoi_irq
51 };
52
53 /**
54 * The hexagon core comes with a first-level i
55 * with 32 total possible interrupts. When th
56 * into different systems/platforms, it is typ
57 * macro cells that provide one or more second
58 * controllers that are cascaded into one or m
59 * interrupts handled here. The precise wiring
60 * irqs varies from platform to platform, and
61 * in the platform-specific files.
62 *
63 * The first-level interrupt controller is wra
64 * virtualizes the interrupt controller for us
65 * simple, fast & efficient API, and so the fa
66 * appropriate for this case.
67 */
68 void __init init_IRQ(void)
69 {
70 int irq;
71
72 for (irq = 0; irq < HEXAGON_CPUINTS; i
73 mask_irq_num(irq);
74 irq_set_chip_and_handler(irq,
75
76 }
77 }
78
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