1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 /*
3 * Author: Huacai Chen <chenhuacai@loongson.cn
4 * Copyright (C) 2020-2022 Loongson Technology
5 */
6
7 #ifndef __ASM_LOONGSON_H
8 #define __ASM_LOONGSON_H
9
10 #include <linux/init.h>
11 #include <linux/io.h>
12 #include <linux/irq.h>
13 #include <linux/pci.h>
14 #include <asm/addrspace.h>
15 #include <asm/bootinfo.h>
16
17 #define LOONGSON_REG(x) \
18 (*(volatile u32 *)((char *)TO_UNCACHE(
19
20 #define LOONGSON_LIO_BASE 0x18000000
21 #define LOONGSON_LIO_SIZE 0x00100000
22 #define LOONGSON_LIO_TOP (LOONGSON_LIO_
23
24 #define LOONGSON_BOOT_BASE 0x1c000000
25 #define LOONGSON_BOOT_SIZE 0x02000000
26 #define LOONGSON_BOOT_TOP (LOONGSON_BOOT
27
28 #define LOONGSON_REG_BASE 0x1fe00000
29 #define LOONGSON_REG_SIZE 0x00100000
30 #define LOONGSON_REG_TOP (LOONGSON_REG_
31
32 /* GPIO Regs - r/w */
33
34 #define LOONGSON_GPIODATA LOONGS
35 #define LOONGSON_GPIOIE LOONGS
36 #define LOONGSON_REG_GPIO_BASE (LOONG
37
38 #define MAX_PACKAGES 16
39
40 #define xconf_readl(addr) readl(addr)
41 #define xconf_readq(addr) readq(addr)
42
43 static inline void xconf_writel(u32 val, volat
44 {
45 asm volatile (
46 " st.w %[v], %[hw], 0 \n"
47 " ld.b $zero, %[hw], 0 \n"
48 :
49 : [hw] "r" (addr), [v] "r" (val)
50 );
51 }
52
53 static inline void xconf_writeq(u64 val64, vol
54 {
55 asm volatile (
56 " st.d %[v], %[hw], 0 \n"
57 " ld.b $zero, %[hw], 0 \n"
58 :
59 : [hw] "r" (addr), [v] "r" (val64)
60 );
61 }
62
63 /* ============== LS7A registers =============
64 #define LS7A_PCH_REG_BASE 0x1000
65 /* LPC regs */
66 #define LS7A_LPC_REG_BASE (LS7A_
67 /* CHIPCFG regs */
68 #define LS7A_CHIPCFG_REG_BASE (LS7A_
69 /* MISC reg base */
70 #define LS7A_MISC_REG_BASE (LS7A_
71 /* ACPI regs */
72 #define LS7A_ACPI_REG_BASE (LS7A_
73 /* RTC regs */
74 #define LS7A_RTC_REG_BASE (LS7A_
75
76 #define LS7A_DMA_CFG (volat
77 #define LS7A_DMA_NODE_SHF 8
78 #define LS7A_DMA_NODE_MASK 0x1F00
79
80 #define LS7A_INT_MASK_REG (volat
81 #define LS7A_INT_EDGE_REG (volat
82 #define LS7A_INT_CLEAR_REG (volat
83 #define LS7A_INT_HTMSI_EN_REG (volat
84 #define LS7A_INT_ROUTE_ENTRY_REG (volat
85 #define LS7A_INT_HTMSI_VEC_REG (volat
86 #define LS7A_INT_STATUS_REG (volat
87 #define LS7A_INT_POL_REG (volat
88 #define LS7A_LPC_INT_CTL (volat
89 #define LS7A_LPC_INT_ENA (volat
90 #define LS7A_LPC_INT_STS (volat
91 #define LS7A_LPC_INT_CLR (volat
92 #define LS7A_LPC_INT_POL (volat
93
94 #define LS7A_PMCON_SOC_REG (volat
95 #define LS7A_PMCON_RESUME_REG (volat
96 #define LS7A_PMCON_RTC_REG (volat
97 #define LS7A_PM1_EVT_REG (volat
98 #define LS7A_PM1_ENA_REG (volat
99 #define LS7A_PM1_CNT_REG (volat
100 #define LS7A_PM1_TMR_REG (volat
101 #define LS7A_P_CNT_REG (volat
102 #define LS7A_GPE0_STS_REG (volat
103 #define LS7A_GPE0_ENA_REG (volat
104 #define LS7A_RST_CNT_REG (volat
105 #define LS7A_WD_SET_REG (volat
106 #define LS7A_WD_TIMER_REG (volat
107 #define LS7A_THSENS_CNT_REG (volat
108 #define LS7A_GEN_RTC_1_REG (volat
109 #define LS7A_GEN_RTC_2_REG (volat
110 #define LS7A_DPM_CFG_REG (volat
111 #define LS7A_DPM_STS_REG (volat
112 #define LS7A_DPM_CNT_REG (volat
113
114 typedef enum {
115 ACPI_PCI_HOTPLUG_STATUS = 1 << 1,
116 ACPI_CPU_HOTPLUG_STATUS = 1 << 2,
117 ACPI_MEM_HOTPLUG_STATUS = 1 << 3,
118 ACPI_POWERBUTTON_STATUS = 1 << 8,
119 ACPI_RTC_WAKE_STATUS = 1 << 10,
120 ACPI_PCI_WAKE_STATUS = 1 << 14,
121 ACPI_ANY_WAKE_STATUS = 1 << 15,
122 } AcpiEventStatusBits;
123
124 #define HT1LO_OFFSET 0xe0000000000U
125
126 /* PCI Configuration Space Base */
127 #define MCFG_EXT_PCICFG_BASE 0xefe0
128
129 /* REG ACCESS*/
130 #define ls7a_readb(addr) (*(volatile un
131 #define ls7a_readw(addr) (*(volatile un
132 #define ls7a_readl(addr) (*(volatile un
133 #define ls7a_readq(addr) (*(volatile un
134 #define ls7a_writeb(val, addr) *(volatile uns
135 #define ls7a_writew(val, addr) *(volatile uns
136 #define ls7a_writel(val, addr) *(volatile uns
137 #define ls7a_writeq(val, addr) *(volatile uns
138
139 void enable_gpe_wakeup(void);
140 void enable_pci_wakeup(void);
141
142 #endif /* __ASM_LOONGSON_H */
143
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