1 // SPDX-License-Identifier: GPL-2.0 <<
2 /* 1 /*
3 * Author: Huacai Chen <chenhuacai@loongson.cn !! 2 * Copyright (C) 2014 Imagination Technologies
4 * Copyright (C) 2020-2022 Loongson Technology !! 3 * Author: Paul Burton <paul.burton@mips.com>
>> 4 *
>> 5 * This program is free software; you can redistribute it and/or modify it
>> 6 * under the terms of the GNU General Public License as published by the
>> 7 * Free Software Foundation; either version 2 of the License, or (at your
>> 8 * option) any later version.
5 */ 9 */
6 10
7 #include <linux/binfmts.h> 11 #include <linux/binfmts.h>
8 #include <linux/elf.h> 12 #include <linux/elf.h>
9 #include <linux/export.h> 13 #include <linux/export.h>
10 #include <linux/sched.h> 14 #include <linux/sched.h>
11 15
12 #include <asm/cpu-features.h> 16 #include <asm/cpu-features.h>
13 #include <asm/cpu-info.h> 17 #include <asm/cpu-info.h>
14 18
>> 19 #ifdef CONFIG_MIPS_FP_SUPPORT
>> 20
>> 21 /* Whether to accept legacy-NaN and 2008-NaN user binaries. */
>> 22 bool mips_use_nan_legacy;
>> 23 bool mips_use_nan_2008;
>> 24
>> 25 /* FPU modes */
>> 26 enum {
>> 27 FP_FRE,
>> 28 FP_FR0,
>> 29 FP_FR1,
>> 30 };
>> 31
>> 32 /**
>> 33 * struct mode_req - ABI FPU mode requirements
>> 34 * @single: The program being loaded needs an FPU but it will only issue
>> 35 * single precision instructions meaning that it can execute in
>> 36 * either FR0 or FR1.
>> 37 * @soft: The soft(-float) requirement means that the program being
>> 38 * loaded needs has no FPU dependency at all (i.e. it has no
>> 39 * FPU instructions).
>> 40 * @fr1: The program being loaded depends on FPU being in FR=1 mode.
>> 41 * @frdefault: The program being loaded depends on the default FPU mode.
>> 42 * That is FR0 for O32 and FR1 for N32/N64.
>> 43 * @fre: The program being loaded depends on FPU with FRE=1. This mode is
>> 44 * a bridge which uses FR=1 whilst still being able to maintain
>> 45 * full compatibility with pre-existing code using the O32 FP32
>> 46 * ABI.
>> 47 *
>> 48 * More information about the FP ABIs can be found here:
>> 49 *
>> 50 * https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking#10.4.1._Basic_mode_set-up
>> 51 *
>> 52 */
>> 53
>> 54 struct mode_req {
>> 55 bool single;
>> 56 bool soft;
>> 57 bool fr1;
>> 58 bool frdefault;
>> 59 bool fre;
>> 60 };
>> 61
>> 62 static const struct mode_req fpu_reqs[] = {
>> 63 [MIPS_ABI_FP_ANY] = { true, true, true, true, true },
>> 64 [MIPS_ABI_FP_DOUBLE] = { false, false, false, true, true },
>> 65 [MIPS_ABI_FP_SINGLE] = { true, false, false, false, false },
>> 66 [MIPS_ABI_FP_SOFT] = { false, true, false, false, false },
>> 67 [MIPS_ABI_FP_OLD_64] = { false, false, false, false, false },
>> 68 [MIPS_ABI_FP_XX] = { false, false, true, true, true },
>> 69 [MIPS_ABI_FP_64] = { false, false, true, false, false },
>> 70 [MIPS_ABI_FP_64A] = { false, false, true, false, true }
>> 71 };
>> 72
>> 73 /*
>> 74 * Mode requirements when .MIPS.abiflags is not present in the ELF.
>> 75 * Not present means that everything is acceptable except FR1.
>> 76 */
>> 77 static struct mode_req none_req = { true, true, false, true, true };
>> 78
15 int arch_elf_pt_proc(void *_ehdr, void *_phdr, 79 int arch_elf_pt_proc(void *_ehdr, void *_phdr, struct file *elf,
16 bool is_interp, struct ar 80 bool is_interp, struct arch_elf_state *state)
17 { 81 {
>> 82 union {
>> 83 struct elf32_hdr e32;
>> 84 struct elf64_hdr e64;
>> 85 } *ehdr = _ehdr;
>> 86 struct elf32_phdr *phdr32 = _phdr;
>> 87 struct elf64_phdr *phdr64 = _phdr;
>> 88 struct mips_elf_abiflags_v0 abiflags;
>> 89 bool elf32;
>> 90 u32 flags;
>> 91 int ret;
>> 92 loff_t pos;
>> 93
>> 94 elf32 = ehdr->e32.e_ident[EI_CLASS] == ELFCLASS32;
>> 95 flags = elf32 ? ehdr->e32.e_flags : ehdr->e64.e_flags;
>> 96
>> 97 /* Let's see if this is an O32 ELF */
>> 98 if (elf32) {
>> 99 if (flags & EF_MIPS_FP64) {
>> 100 /*
>> 101 * Set MIPS_ABI_FP_OLD_64 for EF_MIPS_FP64. We will override it
>> 102 * later if needed
>> 103 */
>> 104 if (is_interp)
>> 105 state->interp_fp_abi = MIPS_ABI_FP_OLD_64;
>> 106 else
>> 107 state->fp_abi = MIPS_ABI_FP_OLD_64;
>> 108 }
>> 109 if (phdr32->p_type != PT_MIPS_ABIFLAGS)
>> 110 return 0;
>> 111
>> 112 if (phdr32->p_filesz < sizeof(abiflags))
>> 113 return -EINVAL;
>> 114 pos = phdr32->p_offset;
>> 115 } else {
>> 116 if (phdr64->p_type != PT_MIPS_ABIFLAGS)
>> 117 return 0;
>> 118 if (phdr64->p_filesz < sizeof(abiflags))
>> 119 return -EINVAL;
>> 120 pos = phdr64->p_offset;
>> 121 }
>> 122
>> 123 ret = kernel_read(elf, &abiflags, sizeof(abiflags), &pos);
>> 124 if (ret < 0)
>> 125 return ret;
>> 126 if (ret != sizeof(abiflags))
>> 127 return -EIO;
>> 128
>> 129 /* Record the required FP ABIs for use by mips_check_elf */
>> 130 if (is_interp)
>> 131 state->interp_fp_abi = abiflags.fp_abi;
>> 132 else
>> 133 state->fp_abi = abiflags.fp_abi;
>> 134
18 return 0; 135 return 0;
19 } 136 }
20 137
21 int arch_check_elf(void *_ehdr, bool has_inter 138 int arch_check_elf(void *_ehdr, bool has_interpreter, void *_interp_ehdr,
22 struct arch_elf_state *stat 139 struct arch_elf_state *state)
23 { 140 {
>> 141 union {
>> 142 struct elf32_hdr e32;
>> 143 struct elf64_hdr e64;
>> 144 } *ehdr = _ehdr;
>> 145 union {
>> 146 struct elf32_hdr e32;
>> 147 struct elf64_hdr e64;
>> 148 } *iehdr = _interp_ehdr;
>> 149 struct mode_req prog_req, interp_req;
>> 150 int fp_abi, interp_fp_abi, abi0, abi1, max_abi;
>> 151 bool elf32;
>> 152 u32 flags;
>> 153
>> 154 elf32 = ehdr->e32.e_ident[EI_CLASS] == ELFCLASS32;
>> 155 flags = elf32 ? ehdr->e32.e_flags : ehdr->e64.e_flags;
>> 156
>> 157 /*
>> 158 * Determine the NaN personality, reject the binary if not allowed.
>> 159 * Also ensure that any interpreter matches the executable.
>> 160 */
>> 161 if (flags & EF_MIPS_NAN2008) {
>> 162 if (mips_use_nan_2008)
>> 163 state->nan_2008 = 1;
>> 164 else
>> 165 return -ENOEXEC;
>> 166 } else {
>> 167 if (mips_use_nan_legacy)
>> 168 state->nan_2008 = 0;
>> 169 else
>> 170 return -ENOEXEC;
>> 171 }
>> 172 if (has_interpreter) {
>> 173 bool ielf32;
>> 174 u32 iflags;
>> 175
>> 176 ielf32 = iehdr->e32.e_ident[EI_CLASS] == ELFCLASS32;
>> 177 iflags = ielf32 ? iehdr->e32.e_flags : iehdr->e64.e_flags;
>> 178
>> 179 if ((flags ^ iflags) & EF_MIPS_NAN2008)
>> 180 return -ELIBBAD;
>> 181 }
>> 182
>> 183 if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
>> 184 return 0;
>> 185
>> 186 fp_abi = state->fp_abi;
>> 187
>> 188 if (has_interpreter) {
>> 189 interp_fp_abi = state->interp_fp_abi;
>> 190
>> 191 abi0 = min(fp_abi, interp_fp_abi);
>> 192 abi1 = max(fp_abi, interp_fp_abi);
>> 193 } else {
>> 194 abi0 = abi1 = fp_abi;
>> 195 }
>> 196
>> 197 if (elf32 && !(flags & EF_MIPS_ABI2)) {
>> 198 /* Default to a mode capable of running code expecting FR=0 */
>> 199 state->overall_fp_mode = cpu_has_mips_r6 ? FP_FRE : FP_FR0;
>> 200
>> 201 /* Allow all ABIs we know about */
>> 202 max_abi = MIPS_ABI_FP_64A;
>> 203 } else {
>> 204 /* MIPS64 code always uses FR=1, thus the default is easy */
>> 205 state->overall_fp_mode = FP_FR1;
>> 206
>> 207 /* Disallow access to the various FPXX & FP64 ABIs */
>> 208 max_abi = MIPS_ABI_FP_SOFT;
>> 209 }
>> 210
>> 211 if ((abi0 > max_abi && abi0 != MIPS_ABI_FP_UNKNOWN) ||
>> 212 (abi1 > max_abi && abi1 != MIPS_ABI_FP_UNKNOWN))
>> 213 return -ELIBBAD;
>> 214
>> 215 /* It's time to determine the FPU mode requirements */
>> 216 prog_req = (abi0 == MIPS_ABI_FP_UNKNOWN) ? none_req : fpu_reqs[abi0];
>> 217 interp_req = (abi1 == MIPS_ABI_FP_UNKNOWN) ? none_req : fpu_reqs[abi1];
>> 218
>> 219 /*
>> 220 * Check whether the program's and interp's ABIs have a matching FPU
>> 221 * mode requirement.
>> 222 */
>> 223 prog_req.single = interp_req.single && prog_req.single;
>> 224 prog_req.soft = interp_req.soft && prog_req.soft;
>> 225 prog_req.fr1 = interp_req.fr1 && prog_req.fr1;
>> 226 prog_req.frdefault = interp_req.frdefault && prog_req.frdefault;
>> 227 prog_req.fre = interp_req.fre && prog_req.fre;
>> 228
>> 229 /*
>> 230 * Determine the desired FPU mode
>> 231 *
>> 232 * Decision making:
>> 233 *
>> 234 * - We want FR_FRE if FRE=1 and both FR=1 and FR=0 are false. This
>> 235 * means that we have a combination of program and interpreter
>> 236 * that inherently require the hybrid FP mode.
>> 237 * - If FR1 and FRDEFAULT is true, that means we hit the any-abi or
>> 238 * fpxx case. This is because, in any-ABI (or no-ABI) we have no FPU
>> 239 * instructions so we don't care about the mode. We will simply use
>> 240 * the one preferred by the hardware. In fpxx case, that ABI can
>> 241 * handle both FR=1 and FR=0, so, again, we simply choose the one
>> 242 * preferred by the hardware. Next, if we only use single-precision
>> 243 * FPU instructions, and the default ABI FPU mode is not good
>> 244 * (ie single + any ABI combination), we set again the FPU mode to the
>> 245 * one is preferred by the hardware. Next, if we know that the code
>> 246 * will only use single-precision instructions, shown by single being
>> 247 * true but frdefault being false, then we again set the FPU mode to
>> 248 * the one that is preferred by the hardware.
>> 249 * - We want FP_FR1 if that's the only matching mode and the default one
>> 250 * is not good.
>> 251 * - Return with -ELIBADD if we can't find a matching FPU mode.
>> 252 */
>> 253 if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1)
>> 254 state->overall_fp_mode = FP_FRE;
>> 255 else if ((prog_req.fr1 && prog_req.frdefault) ||
>> 256 (prog_req.single && !prog_req.frdefault))
>> 257 /* Make sure 64-bit MIPS III/IV/64R1 will not pick FR1 */
>> 258 state->overall_fp_mode = ((raw_current_cpu_data.fpu_id & MIPS_FPIR_F64) &&
>> 259 cpu_has_mips_r2_r6) ?
>> 260 FP_FR1 : FP_FR0;
>> 261 else if (prog_req.fr1)
>> 262 state->overall_fp_mode = FP_FR1;
>> 263 else if (!prog_req.fre && !prog_req.frdefault &&
>> 264 !prog_req.fr1 && !prog_req.single && !prog_req.soft)
>> 265 return -ELIBBAD;
>> 266
>> 267 return 0;
>> 268 }
>> 269
>> 270 static inline void set_thread_fp_mode(int hybrid, int regs32)
>> 271 {
>> 272 if (hybrid)
>> 273 set_thread_flag(TIF_HYBRID_FPREGS);
>> 274 else
>> 275 clear_thread_flag(TIF_HYBRID_FPREGS);
>> 276 if (regs32)
>> 277 set_thread_flag(TIF_32BIT_FPREGS);
>> 278 else
>> 279 clear_thread_flag(TIF_32BIT_FPREGS);
>> 280 }
>> 281
>> 282 void mips_set_personality_fp(struct arch_elf_state *state)
>> 283 {
>> 284 /*
>> 285 * This function is only ever called for O32 ELFs so we should
>> 286 * not be worried about N32/N64 binaries.
>> 287 */
>> 288
>> 289 if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
>> 290 return;
>> 291
>> 292 switch (state->overall_fp_mode) {
>> 293 case FP_FRE:
>> 294 set_thread_fp_mode(1, 0);
>> 295 break;
>> 296 case FP_FR0:
>> 297 set_thread_fp_mode(0, 1);
>> 298 break;
>> 299 case FP_FR1:
>> 300 set_thread_fp_mode(0, 0);
>> 301 break;
>> 302 default:
>> 303 BUG();
>> 304 }
>> 305 }
>> 306
>> 307 /*
>> 308 * Select the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
>> 309 * in FCSR according to the ELF NaN personality.
>> 310 */
>> 311 void mips_set_personality_nan(struct arch_elf_state *state)
>> 312 {
>> 313 struct cpuinfo_mips *c = &boot_cpu_data;
>> 314 struct task_struct *t = current;
>> 315
>> 316 t->thread.fpu.fcr31 = c->fpu_csr31;
>> 317 switch (state->nan_2008) {
>> 318 case 0:
>> 319 break;
>> 320 case 1:
>> 321 if (!(c->fpu_msk31 & FPU_CSR_NAN2008))
>> 322 t->thread.fpu.fcr31 |= FPU_CSR_NAN2008;
>> 323 if (!(c->fpu_msk31 & FPU_CSR_ABS2008))
>> 324 t->thread.fpu.fcr31 |= FPU_CSR_ABS2008;
>> 325 break;
>> 326 default:
>> 327 BUG();
>> 328 }
>> 329 }
>> 330
>> 331 #endif /* CONFIG_MIPS_FP_SUPPORT */
>> 332
>> 333 int mips_elf_read_implies_exec(void *elf_ex, int exstack)
>> 334 {
>> 335 if (exstack != EXSTACK_DISABLE_X) {
>> 336 /* The binary doesn't request a non-executable stack */
>> 337 return 1;
>> 338 }
>> 339
>> 340 if (!cpu_has_rixi) {
>> 341 /* The CPU doesn't support non-executable memory */
>> 342 return 1;
>> 343 }
>> 344
24 return 0; 345 return 0;
25 } 346 }
>> 347 EXPORT_SYMBOL(mips_elf_read_implies_exec);
26 348
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