1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* 2 /*
3 * Copyright (C) 2020-2022 Loongson Technology !! 3 * arch/alpha/kernel/head.S
>> 4 *
>> 5 * initial boot stuff.. At this point, the bootloader has already
>> 6 * switched into OSF/1 PAL-code, and loaded us at the correct address
>> 7 * (START_ADDR). So there isn't much left for us to do: just set up
>> 8 * the kernel global pointer and jump to the kernel entry-point.
4 */ 9 */
5 #include <linux/init.h> <<
6 #include <linux/threads.h> <<
7 <<
8 #include <asm/addrspace.h> <<
9 #include <asm/asm.h> <<
10 #include <asm/asmmacro.h> <<
11 #include <asm/bug.h> <<
12 #include <asm/regdef.h> <<
13 #include <asm/loongarch.h> <<
14 #include <asm/stackframe.h> <<
15 <<
16 #ifdef CONFIG_EFI_STUB <<
17 <<
18 #include "efi-header.S" <<
19 <<
20 __HEAD <<
21 <<
22 _head: <<
23 .word MZ_MAGIC /* "MZ <<
24 .org 0x8 <<
25 .dword _kernel_entry /* Ker <<
26 .dword _kernel_asize /* Ker <<
27 .quad PHYS_LINK_KADDR /* Ker <<
28 .org 0x38 /* 0x2 <<
29 .long LINUX_PE_MAGIC <<
30 .long pe_header - _head /* Off <<
31 <<
32 pe_header: <<
33 __EFI_PE_HEADER <<
34 <<
35 SYM_DATA(kernel_asize, .long _kernel_asize); <<
36 SYM_DATA(kernel_fsize, .long _kernel_fsize); <<
37 <<
38 #endif <<
39 <<
40 __REF <<
41 <<
42 .align 12 <<
43 <<
44 SYM_CODE_START(kernel_entry) <<
45 <<
46 /* Config direct window and set PG */ <<
47 SETUP_DMWINS t0 <<
48 JUMP_VIRT_ADDR t0, t1 <<
49 <<
50 /* Enable PG */ <<
51 li.w t0, 0xb0 <<
52 csrwr t0, LOONGARCH_CSR_CRMD <<
53 li.w t0, 0x04 <<
54 csrwr t0, LOONGARCH_CSR_PRMD <<
55 li.w t0, 0x00 <<
56 csrwr t0, LOONGARCH_CSR_EUEN <<
57 <<
58 la.pcrel t0, __bss_start <<
59 st.d zero, t0, 0 <<
60 la.pcrel t1, __bss_stop - LONGS <<
61 1: <<
62 addi.d t0, t0, LONGSIZE <<
63 st.d zero, t0, 0 <<
64 bne t0, t1, 1b <<
65 <<
66 la.pcrel t0, fw_arg0 <<
67 st.d a0, t0, 0 <<
68 la.pcrel t0, fw_arg1 <<
69 st.d a1, t0, 0 <<
70 la.pcrel t0, fw_arg2 <<
71 st.d a2, t0, 0 <<
72 <<
73 #ifdef CONFIG_PAGE_SIZE_4KB <<
74 li.d t0, 0 <<
75 li.d t1, CSR_STFILL <<
76 csrxchg t0, t1, LOONGARCH_CSR_ <<
77 #endif <<
78 /* KSave3 used for percpu base, initia <<
79 csrwr zero, PERCPU_BASE_KS <<
80 /* GPR21 used for percpu base (runtime <<
81 move u0, zero <<
82 <<
83 la.pcrel tp, init_thread_union <<
84 /* Set the SP after an empty pt_regs. <<
85 PTR_LI sp, (_THREAD_SIZE - PT <<
86 PTR_ADD sp, sp, tp <<
87 set_saved_sp sp, t0, t1 <<
88 <<
89 #ifdef CONFIG_RELOCATABLE <<
90 <<
91 bl relocate_kernel <<
92 <<
93 #ifdef CONFIG_RANDOMIZE_BASE <<
94 /* Repoint the sp into the new kernel <<
95 PTR_LI sp, (_THREAD_SIZE - PT <<
96 PTR_ADD sp, sp, tp <<
97 set_saved_sp sp, t0, t1 <<
98 <<
99 /* Jump to the new kernel: new_pc = cu <<
100 pcaddi t0, 0 <<
101 add.d t0, t0, a0 <<
102 jirl zero, t0, 0xc <<
103 #endif /* CONFIG_RANDOMIZE_BASE */ <<
104 <<
105 #endif /* CONFIG_RELOCATABLE */ <<
106 <<
107 #ifdef CONFIG_KASAN <<
108 bl kasan_early_init <<
109 #endif <<
110 <<
111 bl start_kernel <<
112 ASM_BUG() <<
113 10
114 SYM_CODE_END(kernel_entry) !! 11 #include <linux/init.h>
>> 12 #include <asm/asm-offsets.h>
>> 13 #include <asm/pal.h>
>> 14 #include <asm/setup.h>
>> 15
>> 16 __HEAD
>> 17 .globl _stext
>> 18 .set noreorder
>> 19 .globl __start
>> 20 .ent __start
>> 21 _stext:
>> 22 __start:
>> 23 .prologue 0
>> 24 br $27,1f
>> 25 1: ldgp $29,0($27)
>> 26 /* We need to get current_task_info loaded up... */
>> 27 lda $8,init_thread_union
>> 28 /* ... and find our stack ... */
>> 29 lda $30,0x4000 - SIZEOF_PT_REGS($8)
>> 30 /* ... and then we can start the kernel. */
>> 31 jsr $26,start_kernel
>> 32 call_pal PAL_halt
>> 33 .end __start
115 34
116 #ifdef CONFIG_SMP 35 #ifdef CONFIG_SMP
117 !! 36 .align 3
118 /* !! 37 .globl __smp_callin
119 * SMP slave cpus entry point. Board specific !! 38 .ent __smp_callin
120 * function after setting up the stack and tp !! 39 /* On entry here from SRM console, the HWPCB of the per-cpu
121 */ !! 40 slot for this processor has been loaded. We've arranged
122 SYM_CODE_START(smpboot_entry) !! 41 for the UNIQUE value for this process to contain the PCBB
123 !! 42 of the target idle task. */
124 SETUP_DMWINS t0 !! 43 __smp_callin:
125 JUMP_VIRT_ADDR t0, t1 !! 44 .prologue 1
126 !! 45 ldgp $29,0($27) # First order of business, load the GP.
127 #ifdef CONFIG_PAGE_SIZE_4KB !! 46
128 li.d t0, 0 !! 47 call_pal PAL_rduniq # Grab the target PCBB.
129 li.d t1, CSR_STFILL !! 48 mov $0,$16 # Install it.
130 csrxchg t0, t1, LOONGARCH_CSR_ !! 49 call_pal PAL_swpctx
131 #endif !! 50
132 /* Enable PG */ !! 51 lda $8,0x3fff # Find "current".
133 li.w t0, 0xb0 !! 52 bic $30,$8,$8
134 csrwr t0, LOONGARCH_CSR_CRMD !! 53
135 li.w t0, 0x04 !! 54 jsr $26,smp_callin
136 csrwr t0, LOONGARCH_CSR_PRMD !! 55 call_pal PAL_halt
137 li.w t0, 0x00 !! 56 .end __smp_callin
138 csrwr t0, LOONGARCH_CSR_EUEN <<
139 <<
140 la.pcrel t0, cpuboot_data <<
141 ld.d sp, t0, CPU_BOOT_STACK <<
142 ld.d tp, t0, CPU_BOOT_TINFO <<
143 <<
144 bl start_secondary <<
145 ASM_BUG() <<
146 <<
147 SYM_CODE_END(smpboot_entry) <<
148 <<
149 #endif /* CONFIG_SMP */ 57 #endif /* CONFIG_SMP */
150 58
151 SYM_ENTRY(kernel_entry_end, SYM_L_GLOBAL, SYM_ !! 59 #
>> 60 # The following two functions are needed for supporting SRM PALcode
>> 61 # on the PC164 (at least), since that PALcode manages the interrupt
>> 62 # masking, and we cannot duplicate the effort without causing problems
>> 63 #
>> 64
>> 65 .align 3
>> 66 .globl cserve_ena
>> 67 .ent cserve_ena
>> 68 cserve_ena:
>> 69 .prologue 0
>> 70 bis $16,$16,$17
>> 71 lda $16,52($31)
>> 72 call_pal PAL_cserve
>> 73 ret ($26)
>> 74 .end cserve_ena
>> 75
>> 76 .align 3
>> 77 .globl cserve_dis
>> 78 .ent cserve_dis
>> 79 cserve_dis:
>> 80 .prologue 0
>> 81 bis $16,$16,$17
>> 82 lda $16,53($31)
>> 83 call_pal PAL_cserve
>> 84 ret ($26)
>> 85 .end cserve_dis
>> 86
>> 87 #
>> 88 # It is handy, on occasion, to make halt actually just loop.
>> 89 # Putting it here means we dont have to recompile the whole
>> 90 # kernel.
>> 91 #
>> 92
>> 93 .align 3
>> 94 .globl halt
>> 95 .ent halt
>> 96 halt:
>> 97 .prologue 0
>> 98 call_pal PAL_halt
>> 99 .end halt
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