1 /* SPDX-License-Identifier: GPL-2.0 */ <<
2 /* 1 /*
3 * Copyright (C) 2020-2022 Loongson Technology !! 2 * This file is subject to the terms and conditions of the GNU General Public
>> 3 * License. See the file "COPYING" in the main directory of this archive
>> 4 * for more details.
>> 5 *
>> 6 * Copyright (C) 1998, 1999, 2000 by Ralf Baechle
>> 7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
>> 8 * Copyright (C) 2007 by Maciej W. Rozycki
>> 9 * Copyright (C) 2011, 2012 MIPS Technologies, Inc.
4 */ 10 */
5 <<
6 #include <linux/export.h> <<
7 #include <asm/alternative-asm.h> <<
8 #include <asm/asm.h> 11 #include <asm/asm.h>
9 #include <asm/asmmacro.h> !! 12 #include <asm/asm-offsets.h>
10 #include <asm/cpu.h> !! 13 #include <asm/export.h>
11 #include <asm/regdef.h> 14 #include <asm/regdef.h>
12 #include <asm/unwind_hints.h> <<
13 <<
14 .macro fill_to_64 r0 <<
15 bstrins.d \r0, \r0, 15, 8 <<
16 bstrins.d \r0, \r0, 31, 16 <<
17 bstrins.d \r0, \r0, 63, 32 <<
18 .endm <<
19 15
20 .section .noinstr.text, "ax" !! 16 #if LONGSIZE == 4
>> 17 #define LONG_S_L swl
>> 18 #define LONG_S_R swr
>> 19 #else
>> 20 #define LONG_S_L sdl
>> 21 #define LONG_S_R sdr
>> 22 #endif
>> 23
>> 24 #ifdef CONFIG_CPU_MICROMIPS
>> 25 #define STORSIZE (LONGSIZE * 2)
>> 26 #define STORMASK (STORSIZE - 1)
>> 27 #define FILL64RG t8
>> 28 #define FILLPTRG t7
>> 29 #undef LONG_S
>> 30 #define LONG_S LONG_SP
>> 31 #else
>> 32 #define STORSIZE LONGSIZE
>> 33 #define STORMASK LONGMASK
>> 34 #define FILL64RG a1
>> 35 #define FILLPTRG t0
>> 36 #endif
21 37
22 SYM_FUNC_START(memset) !! 38 #define LEGACY_MODE 1
23 /* !! 39 #define EVA_MODE 2
24 * Some CPUs support hardware unaligne <<
25 */ <<
26 ALTERNATIVE "b __memset_generic", <<
27 "b __memset_fast", CPU <<
28 SYM_FUNC_END(memset) <<
29 SYM_FUNC_ALIAS(__memset, memset) <<
30 <<
31 EXPORT_SYMBOL(memset) <<
32 EXPORT_SYMBOL(__memset) <<
33 <<
34 _ASM_NOKPROBE(memset) <<
35 _ASM_NOKPROBE(__memset) <<
36 40
37 /* 41 /*
38 * void *__memset_generic(void *s, int c, size !! 42 * No need to protect it with EVA #ifdefery. The generated block of code
39 * !! 43 * will never be assembled if EVA is not enabled.
40 * a0: s <<
41 * a1: c <<
42 * a2: n <<
43 */ 44 */
44 SYM_FUNC_START(__memset_generic) !! 45 #define __EVAFY(insn, reg, addr) __BUILD_EVA_INSN(insn##e, reg, addr)
45 move a3, a0 !! 46 #define ___BUILD_EVA_INSN(insn, reg, addr) __EVAFY(insn, reg, addr)
46 beqz a2, 2f <<
47 <<
48 1: st.b a1, a0, 0 <<
49 addi.d a0, a0, 1 <<
50 addi.d a2, a2, -1 <<
51 bgt a2, zero, 1b <<
52 47
53 2: move a0, a3 !! 48 #define EX(insn,reg,addr,handler) \
54 jr ra !! 49 .if \mode == LEGACY_MODE; \
55 SYM_FUNC_END(__memset_generic) !! 50 9: insn reg, addr; \
56 _ASM_NOKPROBE(__memset_generic) !! 51 .else; \
57 !! 52 9: ___BUILD_EVA_INSN(insn, reg, addr); \
58 /* !! 53 .endif; \
59 * void *__memset_fast(void *s, int c, size_t !! 54 .section __ex_table,"a"; \
60 * !! 55 PTR 9b, handler; \
61 * a0: s !! 56 .previous
62 * a1: c !! 57
63 * a2: n !! 58 .macro f_fill64 dst, offset, val, fixup, mode
64 */ !! 59 EX(LONG_S, \val, (\offset + 0 * STORSIZE)(\dst), \fixup)
65 SYM_FUNC_START(__memset_fast) !! 60 EX(LONG_S, \val, (\offset + 1 * STORSIZE)(\dst), \fixup)
66 /* fill a1 to 64 bits */ !! 61 EX(LONG_S, \val, (\offset + 2 * STORSIZE)(\dst), \fixup)
67 fill_to_64 a1 !! 62 EX(LONG_S, \val, (\offset + 3 * STORSIZE)(\dst), \fixup)
68 !! 63 #if ((defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4)) || !defined(CONFIG_CPU_MICROMIPS))
69 sltui t0, a2, 9 !! 64 EX(LONG_S, \val, (\offset + 4 * STORSIZE)(\dst), \fixup)
70 bnez t0, .Lsmall !! 65 EX(LONG_S, \val, (\offset + 5 * STORSIZE)(\dst), \fixup)
71 !! 66 EX(LONG_S, \val, (\offset + 6 * STORSIZE)(\dst), \fixup)
72 add.d a2, a0, a2 !! 67 EX(LONG_S, \val, (\offset + 7 * STORSIZE)(\dst), \fixup)
73 st.d a1, a0, 0 !! 68 #endif
74 !! 69 #if (!defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4))
75 /* align up address */ !! 70 EX(LONG_S, \val, (\offset + 8 * STORSIZE)(\dst), \fixup)
76 addi.d a3, a0, 8 !! 71 EX(LONG_S, \val, (\offset + 9 * STORSIZE)(\dst), \fixup)
77 bstrins.d a3, zero, 2, 0 !! 72 EX(LONG_S, \val, (\offset + 10 * STORSIZE)(\dst), \fixup)
78 !! 73 EX(LONG_S, \val, (\offset + 11 * STORSIZE)(\dst), \fixup)
79 addi.d a4, a2, -64 !! 74 EX(LONG_S, \val, (\offset + 12 * STORSIZE)(\dst), \fixup)
80 bgeu a3, a4, .Llt64 !! 75 EX(LONG_S, \val, (\offset + 13 * STORSIZE)(\dst), \fixup)
81 !! 76 EX(LONG_S, \val, (\offset + 14 * STORSIZE)(\dst), \fixup)
82 /* set 64 bytes at a time */ !! 77 EX(LONG_S, \val, (\offset + 15 * STORSIZE)(\dst), \fixup)
83 .Lloop64: !! 78 #endif
84 st.d a1, a3, 0 !! 79 .endm
85 st.d a1, a3, 8 <<
86 st.d a1, a3, 16 <<
87 st.d a1, a3, 24 <<
88 st.d a1, a3, 32 <<
89 st.d a1, a3, 40 <<
90 st.d a1, a3, 48 <<
91 st.d a1, a3, 56 <<
92 addi.d a3, a3, 64 <<
93 bltu a3, a4, .Lloop64 <<
94 <<
95 /* set the remaining bytes */ <<
96 .Llt64: <<
97 addi.d a4, a2, -32 <<
98 bgeu a3, a4, .Llt32 <<
99 st.d a1, a3, 0 <<
100 st.d a1, a3, 8 <<
101 st.d a1, a3, 16 <<
102 st.d a1, a3, 24 <<
103 addi.d a3, a3, 32 <<
104 <<
105 .Llt32: <<
106 addi.d a4, a2, -16 <<
107 bgeu a3, a4, .Llt16 <<
108 st.d a1, a3, 0 <<
109 st.d a1, a3, 8 <<
110 addi.d a3, a3, 16 <<
111 <<
112 .Llt16: <<
113 addi.d a4, a2, -8 <<
114 bgeu a3, a4, .Llt8 <<
115 st.d a1, a3, 0 <<
116 <<
117 .Llt8: <<
118 st.d a1, a2, -8 <<
119 <<
120 /* return */ <<
121 jr ra <<
122 80
123 .align 4 !! 81 .set noreorder
124 .Lsmall: !! 82 .align 5
125 pcaddi t0, 4 <<
126 slli.d a2, a2, 4 <<
127 add.d t0, t0, a2 <<
128 jr t0 <<
129 83
130 .align 4 !! 84 /*
131 0: jr ra !! 85 * Macro to generate the __bzero{,_user} symbol
132 !! 86 * Arguments:
133 .align 4 !! 87 * mode: LEGACY_MODE or EVA_MODE
134 1: st.b a1, a0, 0 !! 88 */
135 jr ra !! 89 .macro __BUILD_BZERO mode
136 !! 90 /* Initialize __memset if this is the first time we call this macro */
137 .align 4 !! 91 .ifnotdef __memset
138 2: st.h a1, a0, 0 !! 92 .set __memset, 1
139 jr ra !! 93 .hidden __memset /* Make sure it does not leak */
140 !! 94 .endif
141 .align 4 !! 95
142 3: st.h a1, a0, 0 !! 96 sltiu t0, a2, STORSIZE /* very small region? */
143 st.b a1, a0, 2 !! 97 bnez t0, .Lsmall_memset\@
144 jr ra !! 98 andi t0, a0, STORMASK /* aligned? */
>> 99
>> 100 #ifdef CONFIG_CPU_MICROMIPS
>> 101 move t8, a1 /* used by 'swp' instruction */
>> 102 move t9, a1
>> 103 #endif
>> 104 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
>> 105 beqz t0, 1f
>> 106 PTR_SUBU t0, STORSIZE /* alignment in bytes */
>> 107 #else
>> 108 .set noat
>> 109 li AT, STORSIZE
>> 110 beqz t0, 1f
>> 111 PTR_SUBU t0, AT /* alignment in bytes */
>> 112 .set at
>> 113 #endif
>> 114
>> 115 #ifndef CONFIG_CPU_MIPSR6
>> 116 R10KCBARRIER(0(ra))
>> 117 #ifdef __MIPSEB__
>> 118 EX(LONG_S_L, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
>> 119 #else
>> 120 EX(LONG_S_R, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
>> 121 #endif
>> 122 PTR_SUBU a0, t0 /* long align ptr */
>> 123 PTR_ADDU a2, t0 /* correct size */
>> 124
>> 125 #else /* CONFIG_CPU_MIPSR6 */
>> 126 #define STORE_BYTE(N) \
>> 127 EX(sb, a1, N(a0), .Lbyte_fixup\@); \
>> 128 beqz t0, 0f; \
>> 129 PTR_ADDU t0, 1;
>> 130
>> 131 PTR_ADDU a2, t0 /* correct size */
>> 132 PTR_ADDU t0, 1
>> 133 STORE_BYTE(0)
>> 134 STORE_BYTE(1)
>> 135 #if LONGSIZE == 4
>> 136 EX(sb, a1, 2(a0), .Lbyte_fixup\@)
>> 137 #else
>> 138 STORE_BYTE(2)
>> 139 STORE_BYTE(3)
>> 140 STORE_BYTE(4)
>> 141 STORE_BYTE(5)
>> 142 EX(sb, a1, 6(a0), .Lbyte_fixup\@)
>> 143 #endif
>> 144 0:
>> 145 ori a0, STORMASK
>> 146 xori a0, STORMASK
>> 147 PTR_ADDIU a0, STORSIZE
>> 148 #endif /* CONFIG_CPU_MIPSR6 */
>> 149 1: ori t1, a2, 0x3f /* # of full blocks */
>> 150 xori t1, 0x3f
>> 151 beqz t1, .Lmemset_partial\@ /* no block to fill */
>> 152 andi t0, a2, 0x40-STORSIZE
>> 153
>> 154 PTR_ADDU t1, a0 /* end address */
>> 155 .set reorder
>> 156 1: PTR_ADDIU a0, 64
>> 157 R10KCBARRIER(0(ra))
>> 158 f_fill64 a0, -64, FILL64RG, .Lfwd_fixup\@, \mode
>> 159 bne t1, a0, 1b
>> 160 .set noreorder
>> 161
>> 162 .Lmemset_partial\@:
>> 163 R10KCBARRIER(0(ra))
>> 164 PTR_LA t1, 2f /* where to start */
>> 165 #ifdef CONFIG_CPU_MICROMIPS
>> 166 LONG_SRL t7, t0, 1
>> 167 #endif
>> 168 #if LONGSIZE == 4
>> 169 PTR_SUBU t1, FILLPTRG
>> 170 #else
>> 171 .set noat
>> 172 LONG_SRL AT, FILLPTRG, 1
>> 173 PTR_SUBU t1, AT
>> 174 .set at
>> 175 #endif
>> 176 jr t1
>> 177 PTR_ADDU a0, t0 /* dest ptr */
>> 178
>> 179 .set push
>> 180 .set noreorder
>> 181 .set nomacro
>> 182 /* ... but first do longs ... */
>> 183 f_fill64 a0, -64, FILL64RG, .Lpartial_fixup\@, \mode
>> 184 2: .set pop
>> 185 andi a2, STORMASK /* At most one long to go */
>> 186
>> 187 beqz a2, 1f
>> 188 #ifndef CONFIG_CPU_MIPSR6
>> 189 PTR_ADDU a0, a2 /* What's left */
>> 190 R10KCBARRIER(0(ra))
>> 191 #ifdef __MIPSEB__
>> 192 EX(LONG_S_R, a1, -1(a0), .Llast_fixup\@)
>> 193 #else
>> 194 EX(LONG_S_L, a1, -1(a0), .Llast_fixup\@)
>> 195 #endif
>> 196 #else
>> 197 PTR_SUBU t0, $0, a2
>> 198 PTR_ADDIU t0, 1
>> 199 STORE_BYTE(0)
>> 200 STORE_BYTE(1)
>> 201 #if LONGSIZE == 4
>> 202 EX(sb, a1, 2(a0), .Lbyte_fixup\@)
>> 203 #else
>> 204 STORE_BYTE(2)
>> 205 STORE_BYTE(3)
>> 206 STORE_BYTE(4)
>> 207 STORE_BYTE(5)
>> 208 EX(sb, a1, 6(a0), .Lbyte_fixup\@)
>> 209 #endif
>> 210 0:
>> 211 #endif
>> 212 1: jr ra
>> 213 move a2, zero
>> 214
>> 215 .Lsmall_memset\@:
>> 216 beqz a2, 2f
>> 217 PTR_ADDU t1, a0, a2
>> 218
>> 219 1: PTR_ADDIU a0, 1 /* fill bytewise */
>> 220 R10KCBARRIER(0(ra))
>> 221 bne t1, a0, 1b
>> 222 EX(sb, a1, -1(a0), .Lsmall_fixup\@)
>> 223
>> 224 2: jr ra /* done */
>> 225 move a2, zero
>> 226 .if __memset == 1
>> 227 END(memset)
>> 228 .set __memset, 0
>> 229 .hidden __memset
>> 230 .endif
>> 231
>> 232 #ifdef CONFIG_CPU_MIPSR6
>> 233 .Lbyte_fixup\@:
>> 234 PTR_SUBU a2, $0, t0
>> 235 jr ra
>> 236 PTR_ADDIU a2, 1
>> 237 #endif /* CONFIG_CPU_MIPSR6 */
145 238
146 .align 4 !! 239 .Lfirst_fixup\@:
147 4: st.w a1, a0, 0 <<
148 jr ra 240 jr ra
>> 241 nop
149 242
150 .align 4 !! 243 .Lfwd_fixup\@:
151 5: st.w a1, a0, 0 !! 244 PTR_L t0, TI_TASK($28)
152 st.b a1, a0, 4 !! 245 andi a2, 0x3f
153 jr ra !! 246 LONG_L t0, THREAD_BUADDR(t0)
>> 247 LONG_ADDU a2, t1
>> 248 jr ra
>> 249 LONG_SUBU a2, t0
>> 250
>> 251 .Lpartial_fixup\@:
>> 252 PTR_L t0, TI_TASK($28)
>> 253 andi a2, STORMASK
>> 254 LONG_L t0, THREAD_BUADDR(t0)
>> 255 LONG_ADDU a2, a0
>> 256 jr ra
>> 257 LONG_SUBU a2, t0
>> 258
>> 259 .Llast_fixup\@:
>> 260 jr ra
>> 261 nop
>> 262
>> 263 .Lsmall_fixup\@:
>> 264 PTR_SUBU a2, t1, a0
>> 265 jr ra
>> 266 PTR_ADDIU a2, 1
154 267
155 .align 4 !! 268 .endm
156 6: st.w a1, a0, 0 <<
157 st.h a1, a0, 4 <<
158 jr ra <<
159 269
160 .align 4 !! 270 /*
161 7: st.w a1, a0, 0 !! 271 * memset(void *s, int c, size_t n)
162 st.w a1, a0, 3 !! 272 *
163 jr ra !! 273 * a0: start of area to clear
>> 274 * a1: char to fill with
>> 275 * a2: size of area to clear
>> 276 */
164 277
165 .align 4 !! 278 LEAF(memset)
166 8: st.d a1, a0, 0 !! 279 EXPORT_SYMBOL(memset)
167 jr ra !! 280 beqz a1, 1f
168 SYM_FUNC_END(__memset_fast) !! 281 move v0, a0 /* result */
169 _ASM_NOKPROBE(__memset_fast) <<
170 282
171 STACK_FRAME_NON_STANDARD __memset_fast !! 283 andi a1, 0xff /* spread fillword */
>> 284 LONG_SLL t1, a1, 8
>> 285 or a1, t1
>> 286 LONG_SLL t1, a1, 16
>> 287 #if LONGSIZE == 8
>> 288 or a1, t1
>> 289 LONG_SLL t1, a1, 32
>> 290 #endif
>> 291 or a1, t1
>> 292 1:
>> 293 #ifndef CONFIG_EVA
>> 294 FEXPORT(__bzero)
>> 295 EXPORT_SYMBOL(__bzero)
>> 296 #else
>> 297 FEXPORT(__bzero_kernel)
>> 298 EXPORT_SYMBOL(__bzero_kernel)
>> 299 #endif
>> 300 __BUILD_BZERO LEGACY_MODE
>> 301
>> 302 #ifdef CONFIG_EVA
>> 303 LEAF(__bzero)
>> 304 EXPORT_SYMBOL(__bzero)
>> 305 __BUILD_BZERO EVA_MODE
>> 306 END(__bzero)
>> 307 #endif
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