1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /********************************************* 2 /***************************************************************************/
3 3
4 /* 4 /*
5 * cache.c -- general ColdFire Cache main 5 * cache.c -- general ColdFire Cache maintenance code
6 * 6 *
7 * Copyright (C) 2010, Greg Ungerer (gerg 7 * Copyright (C) 2010, Greg Ungerer (gerg@snapgear.com)
8 */ 8 */
9 9
10 /********************************************* 10 /***************************************************************************/
11 11
12 #include <linux/kernel.h> 12 #include <linux/kernel.h>
13 #include <asm/coldfire.h> 13 #include <asm/coldfire.h>
14 #include <asm/mcfsim.h> 14 #include <asm/mcfsim.h>
15 15
16 /********************************************* 16 /***************************************************************************/
17 #ifdef CACHE_PUSH 17 #ifdef CACHE_PUSH
18 /********************************************* 18 /***************************************************************************/
19 19
20 /* 20 /*
21 * Use cpushl to push all dirty cache lin 21 * Use cpushl to push all dirty cache lines back to memory.
22 * Older versions of GAS don't seem to kn 22 * Older versions of GAS don't seem to know how to generate the
23 * ColdFire cpushl instruction... Oh well 23 * ColdFire cpushl instruction... Oh well, bit stuff it for now.
24 */ 24 */
25 25
26 void mcf_cache_push(void) 26 void mcf_cache_push(void)
27 { 27 {
28 __asm__ __volatile__ ( 28 __asm__ __volatile__ (
29 "clrl %%d0\n\t" 29 "clrl %%d0\n\t"
30 "1:\n\t" 30 "1:\n\t"
31 "movel %%d0,%%a0\n\t" 31 "movel %%d0,%%a0\n\t"
32 "2:\n\t" 32 "2:\n\t"
33 ".word 0xf468\n\t" 33 ".word 0xf468\n\t"
34 "addl %0,%%a0\n\t" 34 "addl %0,%%a0\n\t"
35 "cmpl %1,%%a0\n\t" 35 "cmpl %1,%%a0\n\t"
36 "blt 2b\n\t" 36 "blt 2b\n\t"
37 "addql #1,%%d0\n\t" 37 "addql #1,%%d0\n\t"
38 "cmpil %2,%%d0\n\t" 38 "cmpil %2,%%d0\n\t"
39 "bne 1b\n\t" 39 "bne 1b\n\t"
40 : /* No output */ 40 : /* No output */
41 : "i" (CACHE_LINE_SIZE), 41 : "i" (CACHE_LINE_SIZE),
42 "i" (DCACHE_SIZE / CACHE_WAY 42 "i" (DCACHE_SIZE / CACHE_WAYS),
43 "i" (CACHE_WAYS) 43 "i" (CACHE_WAYS)
44 : "d0", "a0" ); 44 : "d0", "a0" );
45 } 45 }
46 46
47 /********************************************* 47 /***************************************************************************/
48 #endif /* CACHE_PUSH */ 48 #endif /* CACHE_PUSH */
49 /********************************************* 49 /***************************************************************************/
50 50
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