1 /* SPDX-License-Identifier: GPL-2.0 */ <<
2 /********************************************* 1 /*****************************************************************************/
3 2
4 /* 3 /*
5 * head.S -- common startup code for Cold 4 * head.S -- common startup code for ColdFire CPUs.
6 * 5 *
7 * (C) Copyright 1999-2011, Greg Ungerer < 6 * (C) Copyright 1999-2011, Greg Ungerer <gerg@snapgear.com>.
8 */ 7 */
9 8
10 /********************************************* 9 /*****************************************************************************/
11 10
12 #include <linux/linkage.h> 11 #include <linux/linkage.h>
13 #include <linux/init.h> 12 #include <linux/init.h>
14 #include <asm/asm-offsets.h> 13 #include <asm/asm-offsets.h>
15 #include <asm/coldfire.h> 14 #include <asm/coldfire.h>
16 #include <asm/mcfsim.h> 15 #include <asm/mcfsim.h>
17 #include <asm/mcfmmu.h> 16 #include <asm/mcfmmu.h>
18 #include <asm/thread_info.h> 17 #include <asm/thread_info.h>
19 18
20 /********************************************* 19 /*****************************************************************************/
21 20
22 /* 21 /*
23 * If we don't have a fixed memory size, 22 * If we don't have a fixed memory size, then lets build in code
24 * to auto detect the DRAM size. Obviousl 23 * to auto detect the DRAM size. Obviously this is the preferred
25 * method, and should work for most board 24 * method, and should work for most boards. It won't work for those
26 * that do not have their RAM starting at 25 * that do not have their RAM starting at address 0, and it only
27 * works on SDRAM (not boards fitted with 26 * works on SDRAM (not boards fitted with SRAM).
28 */ 27 */
29 #if CONFIG_RAMSIZE != 0 28 #if CONFIG_RAMSIZE != 0
30 .macro GET_MEM_SIZE 29 .macro GET_MEM_SIZE
31 movel #CONFIG_RAMSIZE,%d0 /* har 30 movel #CONFIG_RAMSIZE,%d0 /* hard coded memory size */
32 .endm 31 .endm
33 32
34 #elif defined(CONFIG_M5206) || defined(CONFIG_ 33 #elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
35 defined(CONFIG_M5249) || defined(CONFIG_ 34 defined(CONFIG_M5249) || defined(CONFIG_M525x) || \
36 defined(CONFIG_M527x) || defined(CONFIG_ 35 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
37 defined(CONFIG_M5307) || defined(CONFIG_ 36 defined(CONFIG_M5307) || defined(CONFIG_M5407)
38 /* 37 /*
39 * Not all these devices have exactly the 38 * Not all these devices have exactly the same DRAM controller,
40 * but the DCMR register is virtually ide 39 * but the DCMR register is virtually identical - give or take
41 * a couple of bits. The only exception i 40 * a couple of bits. The only exception is the 5272 devices, their
42 * DRAM controller is quite different. 41 * DRAM controller is quite different.
43 */ 42 */
44 .macro GET_MEM_SIZE 43 .macro GET_MEM_SIZE
45 movel MCFSIM_DMR0,%d0 /* get 44 movel MCFSIM_DMR0,%d0 /* get mask for 1st bank */
46 btst #0,%d0 /* che 45 btst #0,%d0 /* check if region enabled */
47 beq 1f 46 beq 1f
48 andl #0xfffc0000,%d0 47 andl #0xfffc0000,%d0
49 beq 1f 48 beq 1f
50 addl #0x00040000,%d0 /* con 49 addl #0x00040000,%d0 /* convert mask to size */
51 1: 50 1:
52 movel MCFSIM_DMR1,%d1 /* get 51 movel MCFSIM_DMR1,%d1 /* get mask for 2nd bank */
53 btst #0,%d1 /* che 52 btst #0,%d1 /* check if region enabled */
54 beq 2f 53 beq 2f
55 andl #0xfffc0000,%d1 54 andl #0xfffc0000,%d1
56 beq 2f 55 beq 2f
57 addl #0x00040000,%d1 56 addl #0x00040000,%d1
58 addl %d1,%d0 /* tot 57 addl %d1,%d0 /* total mem size in d0 */
59 2: 58 2:
60 .endm 59 .endm
61 60
62 #elif defined(CONFIG_M5272) 61 #elif defined(CONFIG_M5272)
63 .macro GET_MEM_SIZE 62 .macro GET_MEM_SIZE
64 movel MCFSIM_CSOR7,%d0 /* get 63 movel MCFSIM_CSOR7,%d0 /* get SDRAM address mask */
65 andil #0xfffff000,%d0 /* mas 64 andil #0xfffff000,%d0 /* mask out chip select options */
66 negl %d0 /* neg 65 negl %d0 /* negate bits */
67 .endm 66 .endm
68 67
69 #elif defined(CONFIG_M520x) 68 #elif defined(CONFIG_M520x)
70 .macro GET_MEM_SIZE 69 .macro GET_MEM_SIZE
71 clrl %d0 70 clrl %d0
72 movel MCFSIM_SDCS0, %d2 /* Get 71 movel MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */
73 andl #0x1f, %d2 /* Get 72 andl #0x1f, %d2 /* Get only the chip select size */
74 beq 3f /* Che 73 beq 3f /* Check if it is enabled */
75 addql #1, %d2 /* For 74 addql #1, %d2 /* Form exponent */
76 moveql #1, %d0 75 moveql #1, %d0
77 lsll %d2, %d0 /* 2 ^ 76 lsll %d2, %d0 /* 2 ^ exponent */
78 3: 77 3:
79 movel MCFSIM_SDCS1, %d2 /* Get 78 movel MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */
80 andl #0x1f, %d2 /* Get 79 andl #0x1f, %d2 /* Get only the chip select size */
81 beq 4f /* Che 80 beq 4f /* Check if it is enabled */
82 addql #1, %d2 /* For 81 addql #1, %d2 /* Form exponent */
83 moveql #1, %d1 82 moveql #1, %d1
84 lsll %d2, %d1 /* 2 ^ 83 lsll %d2, %d1 /* 2 ^ exponent */
85 addl %d1, %d0 /* Tot 84 addl %d1, %d0 /* Total size of SDRAM in d0 */
86 4: 85 4:
87 .endm 86 .endm
88 87
89 #else 88 #else
90 #error "ERROR: I don't know how to probe your 89 #error "ERROR: I don't know how to probe your boards memory size?"
91 #endif 90 #endif
92 91
93 /********************************************* 92 /*****************************************************************************/
94 93
95 /* 94 /*
96 * Boards and platforms can do specific e 95 * Boards and platforms can do specific early hardware setup if
97 * they need to. Most don't need this, de 96 * they need to. Most don't need this, define away if not required.
98 */ 97 */
99 #ifndef PLATFORM_SETUP 98 #ifndef PLATFORM_SETUP
100 #define PLATFORM_SETUP 99 #define PLATFORM_SETUP
101 #endif 100 #endif
102 101
103 /********************************************* 102 /*****************************************************************************/
104 103
105 .global _start 104 .global _start
106 .global _rambase 105 .global _rambase
107 .global _ramvec 106 .global _ramvec
108 .global _ramstart 107 .global _ramstart
109 .global _ramend 108 .global _ramend
110 #if defined(CONFIG_UBOOT) 109 #if defined(CONFIG_UBOOT)
111 .global _init_sp 110 .global _init_sp
112 #endif 111 #endif
113 112
114 /********************************************* 113 /*****************************************************************************/
115 114
116 .data 115 .data
117 116
118 /* 117 /*
119 * During startup we store away the RAM s 118 * During startup we store away the RAM setup. These are not in the
120 * bss, since their values are determined 119 * bss, since their values are determined and written before the bss
121 * has been cleared. 120 * has been cleared.
122 */ 121 */
123 _rambase: 122 _rambase:
124 .long 0 123 .long 0
125 _ramvec: 124 _ramvec:
126 .long 0 125 .long 0
127 _ramstart: 126 _ramstart:
128 .long 0 127 .long 0
129 _ramend: 128 _ramend:
130 .long 0 129 .long 0
131 #if defined(CONFIG_UBOOT) 130 #if defined(CONFIG_UBOOT)
132 _init_sp: 131 _init_sp:
133 .long 0 132 .long 0
134 #endif 133 #endif
135 134
136 /********************************************* 135 /*****************************************************************************/
137 136
138 __HEAD 137 __HEAD
139 138
140 #ifdef CONFIG_MMU 139 #ifdef CONFIG_MMU
141 _start0: 140 _start0:
142 jmp _start 141 jmp _start
143 .global kernel_pg_dir 142 .global kernel_pg_dir
144 .equ kernel_pg_dir,_start0 143 .equ kernel_pg_dir,_start0
145 .equ .,_start0+0x1000 144 .equ .,_start0+0x1000
146 #endif 145 #endif
147 146
148 /* 147 /*
149 * This is the codes first entry point. T 148 * This is the codes first entry point. This is where it all
150 * begins... 149 * begins...
151 */ 150 */
152 151
153 _start: 152 _start:
154 nop 153 nop /* filler */
155 movew #0x2700, %sr 154 movew #0x2700, %sr /* no interrupts */
156 movel #CACHE_INIT,%d0 155 movel #CACHE_INIT,%d0 /* disable cache */
157 movec %d0,%CACR 156 movec %d0,%CACR
158 nop 157 nop
159 #if defined(CONFIG_UBOOT) 158 #if defined(CONFIG_UBOOT)
160 movel %sp,_init_sp 159 movel %sp,_init_sp /* save initial stack pointer */
161 #endif 160 #endif
162 #ifdef CONFIG_MBAR 161 #ifdef CONFIG_MBAR
163 movel #CONFIG_MBAR+1,%d0 162 movel #CONFIG_MBAR+1,%d0 /* configured MBAR address */
164 movec %d0,%MBAR 163 movec %d0,%MBAR /* set it */
165 #endif 164 #endif
166 165
167 /* 166 /*
168 * Do any platform or board speci 167 * Do any platform or board specific setup now. Most boards
169 * don't need anything. Those exc 168 * don't need anything. Those exceptions are define this in
170 * their board specific includes. 169 * their board specific includes.
171 */ 170 */
172 PLATFORM_SETUP 171 PLATFORM_SETUP
173 172
174 /* 173 /*
175 * Create basic memory configurat 174 * Create basic memory configuration. Set VBR accordingly,
176 * and size memory. 175 * and size memory.
177 */ 176 */
178 movel #CONFIG_VECTORBASE,%a7 177 movel #CONFIG_VECTORBASE,%a7
179 movec %a7,%VBR 178 movec %a7,%VBR /* set vectors addr */
180 movel %a7,_ramvec 179 movel %a7,_ramvec
181 180
182 movel #CONFIG_RAMBASE,%a7 181 movel #CONFIG_RAMBASE,%a7 /* mark the base of RAM */
183 movel %a7,_rambase 182 movel %a7,_rambase
184 183
185 GET_MEM_SIZE 184 GET_MEM_SIZE /* macro code determines size */
186 addl %a7,%d0 185 addl %a7,%d0
187 movel %d0,_ramend 186 movel %d0,_ramend /* set end ram addr */
188 187
189 /* 188 /*
190 * Now that we know what the memo 189 * Now that we know what the memory is, lets enable cache
191 * and get things moving. This is 190 * and get things moving. This is Coldfire CPU specific. Not
192 * all version cores have identic 191 * all version cores have identical cache register setup. But
193 * it is very similar. Define the 192 * it is very similar. Define the exact settings in the headers
194 * then the code here is the same 193 * then the code here is the same for all.
195 */ 194 */
196 movel #ACR0_MODE,%d0 195 movel #ACR0_MODE,%d0 /* set RAM region for caching */
197 movec %d0,%ACR0 196 movec %d0,%ACR0
198 movel #ACR1_MODE,%d0 197 movel #ACR1_MODE,%d0 /* anything else to cache? */
199 movec %d0,%ACR1 198 movec %d0,%ACR1
200 #ifdef ACR2_MODE 199 #ifdef ACR2_MODE
201 movel #ACR2_MODE,%d0 200 movel #ACR2_MODE,%d0
202 movec %d0,%ACR2 201 movec %d0,%ACR2
203 movel #ACR3_MODE,%d0 202 movel #ACR3_MODE,%d0
204 movec %d0,%ACR3 203 movec %d0,%ACR3
205 #endif 204 #endif
206 movel #CACHE_MODE,%d0 205 movel #CACHE_MODE,%d0 /* enable cache */
207 movec %d0,%CACR 206 movec %d0,%CACR
208 nop 207 nop
209 208
210 #ifdef CONFIG_MMU 209 #ifdef CONFIG_MMU
211 /* 210 /*
212 * Identity mapping for the kerne 211 * Identity mapping for the kernel region.
213 */ 212 */
214 movel #(MMUBASE+1),%d0 213 movel #(MMUBASE+1),%d0 /* enable MMUBAR registers */
215 movec %d0,%MMUBAR 214 movec %d0,%MMUBAR
216 movel #MMUOR_CA,%d0 215 movel #MMUOR_CA,%d0 /* clear TLB entries */
217 movel %d0,MMUOR 216 movel %d0,MMUOR
218 movel #0,%d0 217 movel #0,%d0 /* set ASID to 0 */
219 movec %d0,%asid 218 movec %d0,%asid
220 219
221 movel #MMUCR_EN,%d0 220 movel #MMUCR_EN,%d0 /* Enable the identity map */
222 movel %d0,MMUCR 221 movel %d0,MMUCR
223 nop 222 nop /* sync i-pipeline */
224 223
225 movel #_vstart,%a0 224 movel #_vstart,%a0 /* jump to "virtual" space */
226 jmp %a0@ 225 jmp %a0@
227 _vstart: 226 _vstart:
228 #endif /* CONFIG_MMU */ 227 #endif /* CONFIG_MMU */
229 228
230 #ifdef CONFIG_ROMFS_FS 229 #ifdef CONFIG_ROMFS_FS
231 /* 230 /*
232 * Move ROM filesystem above bss 231 * Move ROM filesystem above bss :-)
233 */ 232 */
234 lea __bss_start,%a0 233 lea __bss_start,%a0 /* get start of bss */
235 lea __bss_stop,%a1 234 lea __bss_stop,%a1 /* set up destination */
236 movel %a0,%a2 235 movel %a0,%a2 /* copy of bss start */
237 236
238 movel 8(%a0),%d0 237 movel 8(%a0),%d0 /* get size of ROMFS */
239 addql #8,%d0 238 addql #8,%d0 /* allow for rounding */
240 andl #0xfffffffc, %d0 239 andl #0xfffffffc, %d0 /* whole words */
241 240
242 addl %d0,%a0 241 addl %d0,%a0 /* copy from end */
243 addl %d0,%a1 242 addl %d0,%a1 /* copy from end */
244 movel %a1,_ramstart 243 movel %a1,_ramstart /* set start of ram */
245 244
246 _copy_romfs: 245 _copy_romfs:
247 movel -(%a0),%d0 246 movel -(%a0),%d0 /* copy dword */
248 movel %d0,-(%a1) 247 movel %d0,-(%a1)
249 cmpl %a0,%a2 248 cmpl %a0,%a2 /* check if at end */
250 bne _copy_romfs 249 bne _copy_romfs
251 250
252 #else /* CONFIG_ROMFS_FS */ 251 #else /* CONFIG_ROMFS_FS */
253 lea __bss_stop,%a1 252 lea __bss_stop,%a1
254 movel %a1,_ramstart 253 movel %a1,_ramstart
255 #endif /* CONFIG_ROMFS_FS */ 254 #endif /* CONFIG_ROMFS_FS */
256 255
257 256
258 /* 257 /*
259 * Zero out the bss region. 258 * Zero out the bss region.
260 */ 259 */
261 lea __bss_start,%a0 260 lea __bss_start,%a0 /* get start of bss */
262 lea __bss_stop,%a1 261 lea __bss_stop,%a1 /* get end of bss */
263 clrl %d0 262 clrl %d0 /* set value */
264 _clear_bss: 263 _clear_bss:
265 movel %d0,(%a0)+ 264 movel %d0,(%a0)+ /* clear each word */
266 cmpl %a0,%a1 265 cmpl %a0,%a1 /* check if at end */
267 bne _clear_bss 266 bne _clear_bss
268 267
269 /* 268 /*
270 * Load the current task pointer 269 * Load the current task pointer and stack.
271 */ 270 */
272 lea init_thread_union,%a0 271 lea init_thread_union,%a0
273 lea THREAD_SIZE(%a0),%sp 272 lea THREAD_SIZE(%a0),%sp
274 273
275 #ifdef CONFIG_MMU 274 #ifdef CONFIG_MMU
276 .global m68k_cputype 275 .global m68k_cputype
277 .global m68k_mmutype 276 .global m68k_mmutype
278 .global m68k_fputype 277 .global m68k_fputype
279 .global m68k_machtype 278 .global m68k_machtype
280 movel #CPU_COLDFIRE,%d0 279 movel #CPU_COLDFIRE,%d0
281 movel %d0,m68k_cputype 280 movel %d0,m68k_cputype /* Mark us as a ColdFire */
282 movel #MMU_COLDFIRE,%d0 281 movel #MMU_COLDFIRE,%d0
283 movel %d0,m68k_mmutype 282 movel %d0,m68k_mmutype
284 movel #FPUTYPE,%d0 !! 283 movel #FPU_COLDFIRE,%d0
285 movel %d0,m68k_fputype !! 284 movel %d0,m68k_fputype
286 movel #MACHINE,%d0 !! 285 movel #MACH_M54XX,%d0
287 movel %d0,m68k_machtype !! 286 movel %d0,m68k_machtype /* Mark us as a 54xx machine */
288 lea init_task,%a2 287 lea init_task,%a2 /* Set "current" init task */
289 #endif 288 #endif
290 289
291 /* 290 /*
292 * Assembler start up done, start !! 291 * Assember start up done, start code proper.
293 */ 292 */
294 jsr start_kernel 293 jsr start_kernel /* start Linux kernel */
295 294
296 _exit: 295 _exit:
297 jmp _exit 296 jmp _exit /* should never get here */
298 297
299 /********************************************* 298 /*****************************************************************************/
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