1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /********************************************* 2 /*****************************************************************************/
3 3
4 /* 4 /*
5 * head.S -- common startup code for Cold 5 * head.S -- common startup code for ColdFire CPUs.
6 * 6 *
7 * (C) Copyright 1999-2011, Greg Ungerer < 7 * (C) Copyright 1999-2011, Greg Ungerer <gerg@snapgear.com>.
8 */ 8 */
9 9
10 /********************************************* 10 /*****************************************************************************/
11 11
12 #include <linux/linkage.h> 12 #include <linux/linkage.h>
13 #include <linux/init.h> 13 #include <linux/init.h>
14 #include <asm/asm-offsets.h> 14 #include <asm/asm-offsets.h>
15 #include <asm/coldfire.h> 15 #include <asm/coldfire.h>
16 #include <asm/mcfsim.h> 16 #include <asm/mcfsim.h>
17 #include <asm/mcfmmu.h> 17 #include <asm/mcfmmu.h>
18 #include <asm/thread_info.h> 18 #include <asm/thread_info.h>
19 19
20 /********************************************* 20 /*****************************************************************************/
21 21
22 /* 22 /*
23 * If we don't have a fixed memory size, 23 * If we don't have a fixed memory size, then lets build in code
24 * to auto detect the DRAM size. Obviousl 24 * to auto detect the DRAM size. Obviously this is the preferred
25 * method, and should work for most board 25 * method, and should work for most boards. It won't work for those
26 * that do not have their RAM starting at 26 * that do not have their RAM starting at address 0, and it only
27 * works on SDRAM (not boards fitted with 27 * works on SDRAM (not boards fitted with SRAM).
28 */ 28 */
29 #if CONFIG_RAMSIZE != 0 29 #if CONFIG_RAMSIZE != 0
30 .macro GET_MEM_SIZE 30 .macro GET_MEM_SIZE
31 movel #CONFIG_RAMSIZE,%d0 /* har 31 movel #CONFIG_RAMSIZE,%d0 /* hard coded memory size */
32 .endm 32 .endm
33 33
34 #elif defined(CONFIG_M5206) || defined(CONFIG_ 34 #elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
35 defined(CONFIG_M5249) || defined(CONFIG_ 35 defined(CONFIG_M5249) || defined(CONFIG_M525x) || \
36 defined(CONFIG_M527x) || defined(CONFIG_ 36 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
37 defined(CONFIG_M5307) || defined(CONFIG_ 37 defined(CONFIG_M5307) || defined(CONFIG_M5407)
38 /* 38 /*
39 * Not all these devices have exactly the 39 * Not all these devices have exactly the same DRAM controller,
40 * but the DCMR register is virtually ide 40 * but the DCMR register is virtually identical - give or take
41 * a couple of bits. The only exception i 41 * a couple of bits. The only exception is the 5272 devices, their
42 * DRAM controller is quite different. 42 * DRAM controller is quite different.
43 */ 43 */
44 .macro GET_MEM_SIZE 44 .macro GET_MEM_SIZE
45 movel MCFSIM_DMR0,%d0 /* get 45 movel MCFSIM_DMR0,%d0 /* get mask for 1st bank */
46 btst #0,%d0 /* che 46 btst #0,%d0 /* check if region enabled */
47 beq 1f 47 beq 1f
48 andl #0xfffc0000,%d0 48 andl #0xfffc0000,%d0
49 beq 1f 49 beq 1f
50 addl #0x00040000,%d0 /* con 50 addl #0x00040000,%d0 /* convert mask to size */
51 1: 51 1:
52 movel MCFSIM_DMR1,%d1 /* get 52 movel MCFSIM_DMR1,%d1 /* get mask for 2nd bank */
53 btst #0,%d1 /* che 53 btst #0,%d1 /* check if region enabled */
54 beq 2f 54 beq 2f
55 andl #0xfffc0000,%d1 55 andl #0xfffc0000,%d1
56 beq 2f 56 beq 2f
57 addl #0x00040000,%d1 57 addl #0x00040000,%d1
58 addl %d1,%d0 /* tot 58 addl %d1,%d0 /* total mem size in d0 */
59 2: 59 2:
60 .endm 60 .endm
61 61
62 #elif defined(CONFIG_M5272) 62 #elif defined(CONFIG_M5272)
63 .macro GET_MEM_SIZE 63 .macro GET_MEM_SIZE
64 movel MCFSIM_CSOR7,%d0 /* get 64 movel MCFSIM_CSOR7,%d0 /* get SDRAM address mask */
65 andil #0xfffff000,%d0 /* mas 65 andil #0xfffff000,%d0 /* mask out chip select options */
66 negl %d0 /* neg 66 negl %d0 /* negate bits */
67 .endm 67 .endm
68 68
69 #elif defined(CONFIG_M520x) 69 #elif defined(CONFIG_M520x)
70 .macro GET_MEM_SIZE 70 .macro GET_MEM_SIZE
71 clrl %d0 71 clrl %d0
72 movel MCFSIM_SDCS0, %d2 /* Get 72 movel MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */
73 andl #0x1f, %d2 /* Get 73 andl #0x1f, %d2 /* Get only the chip select size */
74 beq 3f /* Che 74 beq 3f /* Check if it is enabled */
75 addql #1, %d2 /* For 75 addql #1, %d2 /* Form exponent */
76 moveql #1, %d0 76 moveql #1, %d0
77 lsll %d2, %d0 /* 2 ^ 77 lsll %d2, %d0 /* 2 ^ exponent */
78 3: 78 3:
79 movel MCFSIM_SDCS1, %d2 /* Get 79 movel MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */
80 andl #0x1f, %d2 /* Get 80 andl #0x1f, %d2 /* Get only the chip select size */
81 beq 4f /* Che 81 beq 4f /* Check if it is enabled */
82 addql #1, %d2 /* For 82 addql #1, %d2 /* Form exponent */
83 moveql #1, %d1 83 moveql #1, %d1
84 lsll %d2, %d1 /* 2 ^ 84 lsll %d2, %d1 /* 2 ^ exponent */
85 addl %d1, %d0 /* Tot 85 addl %d1, %d0 /* Total size of SDRAM in d0 */
86 4: 86 4:
87 .endm 87 .endm
88 88
89 #else 89 #else
90 #error "ERROR: I don't know how to probe your 90 #error "ERROR: I don't know how to probe your boards memory size?"
91 #endif 91 #endif
92 92
93 /********************************************* 93 /*****************************************************************************/
94 94
95 /* 95 /*
96 * Boards and platforms can do specific e 96 * Boards and platforms can do specific early hardware setup if
97 * they need to. Most don't need this, de 97 * they need to. Most don't need this, define away if not required.
98 */ 98 */
99 #ifndef PLATFORM_SETUP 99 #ifndef PLATFORM_SETUP
100 #define PLATFORM_SETUP 100 #define PLATFORM_SETUP
101 #endif 101 #endif
102 102
103 /********************************************* 103 /*****************************************************************************/
104 104
105 .global _start 105 .global _start
106 .global _rambase 106 .global _rambase
107 .global _ramvec 107 .global _ramvec
108 .global _ramstart 108 .global _ramstart
109 .global _ramend 109 .global _ramend
110 #if defined(CONFIG_UBOOT) 110 #if defined(CONFIG_UBOOT)
111 .global _init_sp 111 .global _init_sp
112 #endif 112 #endif
113 113
114 /********************************************* 114 /*****************************************************************************/
115 115
116 .data 116 .data
117 117
118 /* 118 /*
119 * During startup we store away the RAM s 119 * During startup we store away the RAM setup. These are not in the
120 * bss, since their values are determined 120 * bss, since their values are determined and written before the bss
121 * has been cleared. 121 * has been cleared.
122 */ 122 */
123 _rambase: 123 _rambase:
124 .long 0 124 .long 0
125 _ramvec: 125 _ramvec:
126 .long 0 126 .long 0
127 _ramstart: 127 _ramstart:
128 .long 0 128 .long 0
129 _ramend: 129 _ramend:
130 .long 0 130 .long 0
131 #if defined(CONFIG_UBOOT) 131 #if defined(CONFIG_UBOOT)
132 _init_sp: 132 _init_sp:
133 .long 0 133 .long 0
134 #endif 134 #endif
135 135
136 /********************************************* 136 /*****************************************************************************/
137 137
138 __HEAD 138 __HEAD
139 139
140 #ifdef CONFIG_MMU 140 #ifdef CONFIG_MMU
141 _start0: 141 _start0:
142 jmp _start 142 jmp _start
143 .global kernel_pg_dir 143 .global kernel_pg_dir
144 .equ kernel_pg_dir,_start0 144 .equ kernel_pg_dir,_start0
145 .equ .,_start0+0x1000 145 .equ .,_start0+0x1000
146 #endif 146 #endif
147 147
148 /* 148 /*
149 * This is the codes first entry point. T 149 * This is the codes first entry point. This is where it all
150 * begins... 150 * begins...
151 */ 151 */
152 152
153 _start: 153 _start:
154 nop 154 nop /* filler */
155 movew #0x2700, %sr 155 movew #0x2700, %sr /* no interrupts */
156 movel #CACHE_INIT,%d0 156 movel #CACHE_INIT,%d0 /* disable cache */
157 movec %d0,%CACR 157 movec %d0,%CACR
158 nop 158 nop
159 #if defined(CONFIG_UBOOT) 159 #if defined(CONFIG_UBOOT)
160 movel %sp,_init_sp 160 movel %sp,_init_sp /* save initial stack pointer */
161 #endif 161 #endif
162 #ifdef CONFIG_MBAR 162 #ifdef CONFIG_MBAR
163 movel #CONFIG_MBAR+1,%d0 163 movel #CONFIG_MBAR+1,%d0 /* configured MBAR address */
164 movec %d0,%MBAR 164 movec %d0,%MBAR /* set it */
165 #endif 165 #endif
166 166
167 /* 167 /*
168 * Do any platform or board speci 168 * Do any platform or board specific setup now. Most boards
169 * don't need anything. Those exc 169 * don't need anything. Those exceptions are define this in
170 * their board specific includes. 170 * their board specific includes.
171 */ 171 */
172 PLATFORM_SETUP 172 PLATFORM_SETUP
173 173
174 /* 174 /*
175 * Create basic memory configurat 175 * Create basic memory configuration. Set VBR accordingly,
176 * and size memory. 176 * and size memory.
177 */ 177 */
178 movel #CONFIG_VECTORBASE,%a7 178 movel #CONFIG_VECTORBASE,%a7
179 movec %a7,%VBR 179 movec %a7,%VBR /* set vectors addr */
180 movel %a7,_ramvec 180 movel %a7,_ramvec
181 181
182 movel #CONFIG_RAMBASE,%a7 182 movel #CONFIG_RAMBASE,%a7 /* mark the base of RAM */
183 movel %a7,_rambase 183 movel %a7,_rambase
184 184
185 GET_MEM_SIZE 185 GET_MEM_SIZE /* macro code determines size */
186 addl %a7,%d0 186 addl %a7,%d0
187 movel %d0,_ramend 187 movel %d0,_ramend /* set end ram addr */
188 188
189 /* 189 /*
190 * Now that we know what the memo 190 * Now that we know what the memory is, lets enable cache
191 * and get things moving. This is 191 * and get things moving. This is Coldfire CPU specific. Not
192 * all version cores have identic 192 * all version cores have identical cache register setup. But
193 * it is very similar. Define the 193 * it is very similar. Define the exact settings in the headers
194 * then the code here is the same 194 * then the code here is the same for all.
195 */ 195 */
196 movel #ACR0_MODE,%d0 196 movel #ACR0_MODE,%d0 /* set RAM region for caching */
197 movec %d0,%ACR0 197 movec %d0,%ACR0
198 movel #ACR1_MODE,%d0 198 movel #ACR1_MODE,%d0 /* anything else to cache? */
199 movec %d0,%ACR1 199 movec %d0,%ACR1
200 #ifdef ACR2_MODE 200 #ifdef ACR2_MODE
201 movel #ACR2_MODE,%d0 201 movel #ACR2_MODE,%d0
202 movec %d0,%ACR2 202 movec %d0,%ACR2
203 movel #ACR3_MODE,%d0 203 movel #ACR3_MODE,%d0
204 movec %d0,%ACR3 204 movec %d0,%ACR3
205 #endif 205 #endif
206 movel #CACHE_MODE,%d0 206 movel #CACHE_MODE,%d0 /* enable cache */
207 movec %d0,%CACR 207 movec %d0,%CACR
208 nop 208 nop
209 209
210 #ifdef CONFIG_MMU 210 #ifdef CONFIG_MMU
211 /* 211 /*
212 * Identity mapping for the kerne 212 * Identity mapping for the kernel region.
213 */ 213 */
214 movel #(MMUBASE+1),%d0 214 movel #(MMUBASE+1),%d0 /* enable MMUBAR registers */
215 movec %d0,%MMUBAR 215 movec %d0,%MMUBAR
216 movel #MMUOR_CA,%d0 216 movel #MMUOR_CA,%d0 /* clear TLB entries */
217 movel %d0,MMUOR 217 movel %d0,MMUOR
218 movel #0,%d0 218 movel #0,%d0 /* set ASID to 0 */
219 movec %d0,%asid 219 movec %d0,%asid
220 220
221 movel #MMUCR_EN,%d0 221 movel #MMUCR_EN,%d0 /* Enable the identity map */
222 movel %d0,MMUCR 222 movel %d0,MMUCR
223 nop 223 nop /* sync i-pipeline */
224 224
225 movel #_vstart,%a0 225 movel #_vstart,%a0 /* jump to "virtual" space */
226 jmp %a0@ 226 jmp %a0@
227 _vstart: 227 _vstart:
228 #endif /* CONFIG_MMU */ 228 #endif /* CONFIG_MMU */
229 229
230 #ifdef CONFIG_ROMFS_FS 230 #ifdef CONFIG_ROMFS_FS
231 /* 231 /*
232 * Move ROM filesystem above bss 232 * Move ROM filesystem above bss :-)
233 */ 233 */
234 lea __bss_start,%a0 234 lea __bss_start,%a0 /* get start of bss */
235 lea __bss_stop,%a1 235 lea __bss_stop,%a1 /* set up destination */
236 movel %a0,%a2 236 movel %a0,%a2 /* copy of bss start */
237 237
238 movel 8(%a0),%d0 238 movel 8(%a0),%d0 /* get size of ROMFS */
239 addql #8,%d0 239 addql #8,%d0 /* allow for rounding */
240 andl #0xfffffffc, %d0 240 andl #0xfffffffc, %d0 /* whole words */
241 241
242 addl %d0,%a0 242 addl %d0,%a0 /* copy from end */
243 addl %d0,%a1 243 addl %d0,%a1 /* copy from end */
244 movel %a1,_ramstart 244 movel %a1,_ramstart /* set start of ram */
245 245
246 _copy_romfs: 246 _copy_romfs:
247 movel -(%a0),%d0 247 movel -(%a0),%d0 /* copy dword */
248 movel %d0,-(%a1) 248 movel %d0,-(%a1)
249 cmpl %a0,%a2 249 cmpl %a0,%a2 /* check if at end */
250 bne _copy_romfs 250 bne _copy_romfs
251 251
252 #else /* CONFIG_ROMFS_FS */ 252 #else /* CONFIG_ROMFS_FS */
253 lea __bss_stop,%a1 253 lea __bss_stop,%a1
254 movel %a1,_ramstart 254 movel %a1,_ramstart
255 #endif /* CONFIG_ROMFS_FS */ 255 #endif /* CONFIG_ROMFS_FS */
256 256
257 257
258 /* 258 /*
259 * Zero out the bss region. 259 * Zero out the bss region.
260 */ 260 */
261 lea __bss_start,%a0 261 lea __bss_start,%a0 /* get start of bss */
262 lea __bss_stop,%a1 262 lea __bss_stop,%a1 /* get end of bss */
263 clrl %d0 263 clrl %d0 /* set value */
264 _clear_bss: 264 _clear_bss:
265 movel %d0,(%a0)+ 265 movel %d0,(%a0)+ /* clear each word */
266 cmpl %a0,%a1 266 cmpl %a0,%a1 /* check if at end */
267 bne _clear_bss 267 bne _clear_bss
268 268
269 /* 269 /*
270 * Load the current task pointer 270 * Load the current task pointer and stack.
271 */ 271 */
272 lea init_thread_union,%a0 272 lea init_thread_union,%a0
273 lea THREAD_SIZE(%a0),%sp 273 lea THREAD_SIZE(%a0),%sp
274 274
275 #ifdef CONFIG_MMU 275 #ifdef CONFIG_MMU
276 .global m68k_cputype 276 .global m68k_cputype
277 .global m68k_mmutype 277 .global m68k_mmutype
278 .global m68k_fputype 278 .global m68k_fputype
279 .global m68k_machtype 279 .global m68k_machtype
280 movel #CPU_COLDFIRE,%d0 280 movel #CPU_COLDFIRE,%d0
281 movel %d0,m68k_cputype 281 movel %d0,m68k_cputype /* Mark us as a ColdFire */
282 movel #MMU_COLDFIRE,%d0 282 movel #MMU_COLDFIRE,%d0
283 movel %d0,m68k_mmutype 283 movel %d0,m68k_mmutype
284 movel #FPUTYPE,%d0 284 movel #FPUTYPE,%d0
285 movel %d0,m68k_fputype 285 movel %d0,m68k_fputype /* Mark FPU type */
286 movel #MACHINE,%d0 286 movel #MACHINE,%d0
287 movel %d0,m68k_machtype 287 movel %d0,m68k_machtype /* Mark machine type */
288 lea init_task,%a2 288 lea init_task,%a2 /* Set "current" init task */
289 #endif 289 #endif
290 290
291 /* 291 /*
292 * Assembler start up done, start 292 * Assembler start up done, start code proper.
293 */ 293 */
294 jsr start_kernel 294 jsr start_kernel /* start Linux kernel */
295 295
296 _exit: 296 _exit:
297 jmp _exit 297 jmp _exit /* should never get here */
298 298
299 /********************************************* 299 /*****************************************************************************/
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