1 // SPDX-License-Identifier: GPL-2.0 <<
2 /********************************************* 1 /***************************************************************************/
3 2
4 /* 3 /*
5 * m528x.c -- platform support for ColdF 4 * m528x.c -- platform support for ColdFire 528x based boards
6 * 5 *
7 * Sub-architcture dependent initializati 6 * Sub-architcture dependent initialization code for the Freescale
8 * 5280, 5281 and 5282 CPUs. 7 * 5280, 5281 and 5282 CPUs.
9 * 8 *
10 * Copyright (C) 1999-2003, Greg Ungerer 9 * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
11 * Copyright (C) 2001-2003, SnapGear Inc. 10 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
12 */ 11 */
13 12
14 /********************************************* 13 /***************************************************************************/
15 14
16 #include <linux/clkdev.h> <<
17 #include <linux/kernel.h> 15 #include <linux/kernel.h>
18 #include <linux/param.h> 16 #include <linux/param.h>
19 #include <linux/init.h> 17 #include <linux/init.h>
20 #include <linux/platform_device.h> 18 #include <linux/platform_device.h>
21 #include <linux/io.h> 19 #include <linux/io.h>
22 #include <asm/machdep.h> 20 #include <asm/machdep.h>
23 #include <asm/coldfire.h> 21 #include <asm/coldfire.h>
24 #include <asm/mcfsim.h> 22 #include <asm/mcfsim.h>
25 #include <asm/mcfuart.h> 23 #include <asm/mcfuart.h>
26 #include <asm/mcfclk.h> 24 #include <asm/mcfclk.h>
27 25
28 /********************************************* 26 /***************************************************************************/
29 27
30 DEFINE_CLK(pll, "pll.0", MCF_CLK); 28 DEFINE_CLK(pll, "pll.0", MCF_CLK);
31 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); 29 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
32 !! 30 DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
33 static struct clk_lookup m528x_clk_lookup[] = !! 31 DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
34 CLKDEV_INIT(NULL, "pll.0", &clk_pll), !! 32 DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
35 CLKDEV_INIT(NULL, "sys.0", &clk_sys), !! 33 DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
36 CLKDEV_INIT("mcfpit.0", NULL, &clk_pll !! 34 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
37 CLKDEV_INIT("mcfpit.1", NULL, &clk_pll !! 35 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
38 CLKDEV_INIT("mcfpit.2", NULL, &clk_pll !! 36 DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
39 CLKDEV_INIT("mcfpit.3", NULL, &clk_pll !! 37 DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
40 CLKDEV_INIT("mcfuart.0", NULL, &clk_sy !! 38 DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
41 CLKDEV_INIT("mcfuart.1", NULL, &clk_sy !! 39
42 CLKDEV_INIT("mcfuart.2", NULL, &clk_sy !! 40 struct clk *mcf_clks[] = {
43 CLKDEV_INIT("mcfqspi.0", NULL, &clk_sy !! 41 &clk_pll,
44 CLKDEV_INIT("fec.0", NULL, &clk_sys), !! 42 &clk_sys,
45 CLKDEV_INIT("imx1-i2c.0", NULL, &clk_s !! 43 &clk_mcfpit0,
>> 44 &clk_mcfpit1,
>> 45 &clk_mcfpit2,
>> 46 &clk_mcfpit3,
>> 47 &clk_mcfuart0,
>> 48 &clk_mcfuart1,
>> 49 &clk_mcfuart2,
>> 50 &clk_mcfqspi0,
>> 51 &clk_fec0,
>> 52 NULL
46 }; 53 };
47 54
48 /********************************************* 55 /***************************************************************************/
49 56
50 static void __init m528x_qspi_init(void) 57 static void __init m528x_qspi_init(void)
51 { 58 {
52 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 59 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
53 /* setup Port QS for QSPI with gpio CS 60 /* setup Port QS for QSPI with gpio CS control */
54 __raw_writeb(0x07, MCFGPIO_PQSPAR); 61 __raw_writeb(0x07, MCFGPIO_PQSPAR);
55 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 62 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
56 } 63 }
57 64
58 /********************************************* 65 /***************************************************************************/
59 66
60 static void __init m528x_i2c_init(void) <<
61 { <<
62 #if IS_ENABLED(CONFIG_I2C_IMX) <<
63 u16 paspar; <<
64 <<
65 /* setup Port AS Pin Assignment Regist <<
66 /* set PASPA0 to SCL and PASPA1 to SD <<
67 paspar = readw(MCFGPIO_PASPAR); <<
68 paspar |= 0xF; <<
69 writew(paspar, MCFGPIO_PASPAR); <<
70 #endif /* IS_ENABLED(CONFIG_I2C_IMX) */ <<
71 } <<
72 <<
73 /********************************************* <<
74 <<
75 static void __init m528x_uarts_init(void) 67 static void __init m528x_uarts_init(void)
76 { 68 {
77 u8 port; 69 u8 port;
78 70
79 /* make sure PUAPAR is set for UART0 a 71 /* make sure PUAPAR is set for UART0 and UART1 */
80 port = readb(MCFGPIO_PUAPAR); 72 port = readb(MCFGPIO_PUAPAR);
81 port |= 0x03 | (0x03 << 2); 73 port |= 0x03 | (0x03 << 2);
82 writeb(port, MCFGPIO_PUAPAR); 74 writeb(port, MCFGPIO_PUAPAR);
83 } 75 }
84 76
85 /********************************************* 77 /***************************************************************************/
86 78
87 static void __init m528x_fec_init(void) 79 static void __init m528x_fec_init(void)
88 { 80 {
89 u16 v16; 81 u16 v16;
90 82
91 /* Set multi-function pins to ethernet 83 /* Set multi-function pins to ethernet mode for fec0 */
92 v16 = readw(MCFGPIO_PASPAR); 84 v16 = readw(MCFGPIO_PASPAR);
93 writew(v16 | 0xf00, MCFGPIO_PASPAR); 85 writew(v16 | 0xf00, MCFGPIO_PASPAR);
94 writeb(0xc0, MCFGPIO_PEHLPAR); 86 writeb(0xc0, MCFGPIO_PEHLPAR);
95 } 87 }
96 88
97 /********************************************* 89 /***************************************************************************/
98 90
99 #ifdef CONFIG_WILDFIRE 91 #ifdef CONFIG_WILDFIRE
100 void wildfire_halt(void) 92 void wildfire_halt(void)
101 { 93 {
102 writeb(0, 0x30000007); 94 writeb(0, 0x30000007);
103 writeb(0x2, 0x30000007); 95 writeb(0x2, 0x30000007);
104 } 96 }
105 #endif 97 #endif
106 98
107 #ifdef CONFIG_WILDFIREMOD 99 #ifdef CONFIG_WILDFIREMOD
108 void wildfiremod_halt(void) 100 void wildfiremod_halt(void)
109 { 101 {
110 printk(KERN_INFO "WildFireMod hibernat 102 printk(KERN_INFO "WildFireMod hibernating...\n");
111 103
112 /* Set portE.5 to Digital IO */ 104 /* Set portE.5 to Digital IO */
113 writew(readw(MCFGPIO_PEPAR) & ~(1 << ( 105 writew(readw(MCFGPIO_PEPAR) & ~(1 << (5 * 2)), MCFGPIO_PEPAR);
114 106
115 /* Make portE.5 an output */ 107 /* Make portE.5 an output */
116 writeb(readb(MCFGPIO_PDDR_E) | (1 << 5 108 writeb(readb(MCFGPIO_PDDR_E) | (1 << 5), MCFGPIO_PDDR_E);
117 109
118 /* Now toggle portE.5 from low to high 110 /* Now toggle portE.5 from low to high */
119 writeb(readb(MCFGPIO_PODR_E) & ~(1 << 111 writeb(readb(MCFGPIO_PODR_E) & ~(1 << 5), MCFGPIO_PODR_E);
120 writeb(readb(MCFGPIO_PODR_E) | (1 << 5 112 writeb(readb(MCFGPIO_PODR_E) | (1 << 5), MCFGPIO_PODR_E);
121 113
122 printk(KERN_EMERG "Failed to hibernate 114 printk(KERN_EMERG "Failed to hibernate. Halting!\n");
123 } 115 }
124 #endif 116 #endif
125 117
126 void __init config_BSP(char *commandp, int siz 118 void __init config_BSP(char *commandp, int size)
127 { 119 {
128 #ifdef CONFIG_WILDFIRE 120 #ifdef CONFIG_WILDFIRE
129 mach_halt = wildfire_halt; 121 mach_halt = wildfire_halt;
130 #endif 122 #endif
131 #ifdef CONFIG_WILDFIREMOD 123 #ifdef CONFIG_WILDFIREMOD
132 mach_halt = wildfiremod_halt; 124 mach_halt = wildfiremod_halt;
133 #endif 125 #endif
134 mach_sched_init = hw_timer_init; 126 mach_sched_init = hw_timer_init;
135 m528x_uarts_init(); 127 m528x_uarts_init();
136 m528x_fec_init(); 128 m528x_fec_init();
137 m528x_qspi_init(); 129 m528x_qspi_init();
138 m528x_i2c_init(); <<
139 <<
140 clkdev_add_table(m528x_clk_lookup, ARR <<
141 } 130 }
142 131
143 /********************************************* 132 /***************************************************************************/
144 133
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