1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /********************************************* 2 /***************************************************************************/
3 3
4 /* 4 /*
5 * m528x.c -- platform support for ColdF 5 * m528x.c -- platform support for ColdFire 528x based boards
6 * 6 *
7 * Sub-architcture dependent initializati 7 * Sub-architcture dependent initialization code for the Freescale
8 * 5280, 5281 and 5282 CPUs. 8 * 5280, 5281 and 5282 CPUs.
9 * 9 *
10 * Copyright (C) 1999-2003, Greg Ungerer 10 * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
11 * Copyright (C) 2001-2003, SnapGear Inc. 11 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
12 */ 12 */
13 13
14 /********************************************* 14 /***************************************************************************/
15 15
16 #include <linux/clkdev.h> <<
17 #include <linux/kernel.h> 16 #include <linux/kernel.h>
18 #include <linux/param.h> 17 #include <linux/param.h>
19 #include <linux/init.h> 18 #include <linux/init.h>
20 #include <linux/platform_device.h> 19 #include <linux/platform_device.h>
21 #include <linux/io.h> 20 #include <linux/io.h>
22 #include <asm/machdep.h> 21 #include <asm/machdep.h>
23 #include <asm/coldfire.h> 22 #include <asm/coldfire.h>
24 #include <asm/mcfsim.h> 23 #include <asm/mcfsim.h>
25 #include <asm/mcfuart.h> 24 #include <asm/mcfuart.h>
26 #include <asm/mcfclk.h> 25 #include <asm/mcfclk.h>
27 26
28 /********************************************* 27 /***************************************************************************/
29 28
30 DEFINE_CLK(pll, "pll.0", MCF_CLK); 29 DEFINE_CLK(pll, "pll.0", MCF_CLK);
31 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); 30 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
32 !! 31 DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
33 static struct clk_lookup m528x_clk_lookup[] = !! 32 DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
34 CLKDEV_INIT(NULL, "pll.0", &clk_pll), !! 33 DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
35 CLKDEV_INIT(NULL, "sys.0", &clk_sys), !! 34 DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
36 CLKDEV_INIT("mcfpit.0", NULL, &clk_pll !! 35 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
37 CLKDEV_INIT("mcfpit.1", NULL, &clk_pll !! 36 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
38 CLKDEV_INIT("mcfpit.2", NULL, &clk_pll !! 37 DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
39 CLKDEV_INIT("mcfpit.3", NULL, &clk_pll !! 38 DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
40 CLKDEV_INIT("mcfuart.0", NULL, &clk_sy !! 39 DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
41 CLKDEV_INIT("mcfuart.1", NULL, &clk_sy !! 40 DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
42 CLKDEV_INIT("mcfuart.2", NULL, &clk_sy !! 41
43 CLKDEV_INIT("mcfqspi.0", NULL, &clk_sy !! 42 struct clk *mcf_clks[] = {
44 CLKDEV_INIT("fec.0", NULL, &clk_sys), !! 43 &clk_pll,
45 CLKDEV_INIT("imx1-i2c.0", NULL, &clk_s !! 44 &clk_sys,
>> 45 &clk_mcfpit0,
>> 46 &clk_mcfpit1,
>> 47 &clk_mcfpit2,
>> 48 &clk_mcfpit3,
>> 49 &clk_mcfuart0,
>> 50 &clk_mcfuart1,
>> 51 &clk_mcfuart2,
>> 52 &clk_mcfqspi0,
>> 53 &clk_fec0,
>> 54 &clk_mcfi2c0,
>> 55 NULL
46 }; 56 };
47 57
48 /********************************************* 58 /***************************************************************************/
49 59
50 static void __init m528x_qspi_init(void) 60 static void __init m528x_qspi_init(void)
51 { 61 {
52 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 62 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
53 /* setup Port QS for QSPI with gpio CS 63 /* setup Port QS for QSPI with gpio CS control */
54 __raw_writeb(0x07, MCFGPIO_PQSPAR); 64 __raw_writeb(0x07, MCFGPIO_PQSPAR);
55 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 65 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
56 } 66 }
57 67
58 /********************************************* 68 /***************************************************************************/
59 69
60 static void __init m528x_i2c_init(void) 70 static void __init m528x_i2c_init(void)
61 { 71 {
62 #if IS_ENABLED(CONFIG_I2C_IMX) 72 #if IS_ENABLED(CONFIG_I2C_IMX)
63 u16 paspar; 73 u16 paspar;
64 74
65 /* setup Port AS Pin Assignment Regist 75 /* setup Port AS Pin Assignment Register for I2C */
66 /* set PASPA0 to SCL and PASPA1 to SD 76 /* set PASPA0 to SCL and PASPA1 to SDA */
67 paspar = readw(MCFGPIO_PASPAR); 77 paspar = readw(MCFGPIO_PASPAR);
68 paspar |= 0xF; 78 paspar |= 0xF;
69 writew(paspar, MCFGPIO_PASPAR); 79 writew(paspar, MCFGPIO_PASPAR);
70 #endif /* IS_ENABLED(CONFIG_I2C_IMX) */ 80 #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
71 } 81 }
72 82
73 /********************************************* 83 /***************************************************************************/
74 84
75 static void __init m528x_uarts_init(void) 85 static void __init m528x_uarts_init(void)
76 { 86 {
77 u8 port; 87 u8 port;
78 88
79 /* make sure PUAPAR is set for UART0 a 89 /* make sure PUAPAR is set for UART0 and UART1 */
80 port = readb(MCFGPIO_PUAPAR); 90 port = readb(MCFGPIO_PUAPAR);
81 port |= 0x03 | (0x03 << 2); 91 port |= 0x03 | (0x03 << 2);
82 writeb(port, MCFGPIO_PUAPAR); 92 writeb(port, MCFGPIO_PUAPAR);
83 } 93 }
84 94
85 /********************************************* 95 /***************************************************************************/
86 96
87 static void __init m528x_fec_init(void) 97 static void __init m528x_fec_init(void)
88 { 98 {
89 u16 v16; 99 u16 v16;
90 100
91 /* Set multi-function pins to ethernet 101 /* Set multi-function pins to ethernet mode for fec0 */
92 v16 = readw(MCFGPIO_PASPAR); 102 v16 = readw(MCFGPIO_PASPAR);
93 writew(v16 | 0xf00, MCFGPIO_PASPAR); 103 writew(v16 | 0xf00, MCFGPIO_PASPAR);
94 writeb(0xc0, MCFGPIO_PEHLPAR); 104 writeb(0xc0, MCFGPIO_PEHLPAR);
95 } 105 }
96 106
97 /********************************************* 107 /***************************************************************************/
98 108
99 #ifdef CONFIG_WILDFIRE 109 #ifdef CONFIG_WILDFIRE
100 void wildfire_halt(void) 110 void wildfire_halt(void)
101 { 111 {
102 writeb(0, 0x30000007); 112 writeb(0, 0x30000007);
103 writeb(0x2, 0x30000007); 113 writeb(0x2, 0x30000007);
104 } 114 }
105 #endif 115 #endif
106 116
107 #ifdef CONFIG_WILDFIREMOD 117 #ifdef CONFIG_WILDFIREMOD
108 void wildfiremod_halt(void) 118 void wildfiremod_halt(void)
109 { 119 {
110 printk(KERN_INFO "WildFireMod hibernat 120 printk(KERN_INFO "WildFireMod hibernating...\n");
111 121
112 /* Set portE.5 to Digital IO */ 122 /* Set portE.5 to Digital IO */
113 writew(readw(MCFGPIO_PEPAR) & ~(1 << ( 123 writew(readw(MCFGPIO_PEPAR) & ~(1 << (5 * 2)), MCFGPIO_PEPAR);
114 124
115 /* Make portE.5 an output */ 125 /* Make portE.5 an output */
116 writeb(readb(MCFGPIO_PDDR_E) | (1 << 5 126 writeb(readb(MCFGPIO_PDDR_E) | (1 << 5), MCFGPIO_PDDR_E);
117 127
118 /* Now toggle portE.5 from low to high 128 /* Now toggle portE.5 from low to high */
119 writeb(readb(MCFGPIO_PODR_E) & ~(1 << 129 writeb(readb(MCFGPIO_PODR_E) & ~(1 << 5), MCFGPIO_PODR_E);
120 writeb(readb(MCFGPIO_PODR_E) | (1 << 5 130 writeb(readb(MCFGPIO_PODR_E) | (1 << 5), MCFGPIO_PODR_E);
121 131
122 printk(KERN_EMERG "Failed to hibernate 132 printk(KERN_EMERG "Failed to hibernate. Halting!\n");
123 } 133 }
124 #endif 134 #endif
125 135
126 void __init config_BSP(char *commandp, int siz 136 void __init config_BSP(char *commandp, int size)
127 { 137 {
128 #ifdef CONFIG_WILDFIRE 138 #ifdef CONFIG_WILDFIRE
129 mach_halt = wildfire_halt; 139 mach_halt = wildfire_halt;
130 #endif 140 #endif
131 #ifdef CONFIG_WILDFIREMOD 141 #ifdef CONFIG_WILDFIREMOD
132 mach_halt = wildfiremod_halt; 142 mach_halt = wildfiremod_halt;
133 #endif 143 #endif
134 mach_sched_init = hw_timer_init; 144 mach_sched_init = hw_timer_init;
135 m528x_uarts_init(); 145 m528x_uarts_init();
136 m528x_fec_init(); 146 m528x_fec_init();
137 m528x_qspi_init(); 147 m528x_qspi_init();
138 m528x_i2c_init(); 148 m528x_i2c_init();
139 <<
140 clkdev_add_table(m528x_clk_lookup, ARR <<
141 } 149 }
142 150
143 /********************************************* 151 /***************************************************************************/
144 152
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