1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2 MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GR
3 M68000 Hi-Performance Microprocessor Division
4 M68060 Software Package
5 Production Release P1.00 -- October 10, 1994
6
7 M68060 Software Package Copyright © 1993, 199
8
9 THE SOFTWARE is provided on an "AS IS" basis a
10 To the maximum extent permitted by applicable
11 MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPR
12 INCLUDING IMPLIED WARRANTIES OF MERCHANTABILIT
13 and any warranty against infringement with reg
14 (INCLUDING ANY MODIFIED VERSIONS THEREOF) and
15
16 To the maximum extent permitted by applicable
17 IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY D
18 (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOS
19 BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORM
20 ARISING OF THE USE OR INABILITY TO USE THE SOF
21 Motorola assumes no responsibility for the mai
22
23 You are hereby granted a copyright license to
24 so long as this entire notice is retained with
25 redistributed versions, and that such modified
26 No licenses are granted by implication, estopp
27 or trademarks of Motorola, Inc.
28 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
29
30 CHANGES SINCE LAST RELEASE:
31 ---------------------------
32
33 1) "movep" emulation where data was being read
34 was reading the intermediate bytes. Emulation
35 reads the required bytes.
36
37 2) "flogn", "flog2", and "flog10" of "1" was s
38 Inexact FPSR bit. Emulation now does not set I
39 this case.
40
41 3) For an opclass three FP instruction where t
42 mode was pre-decrement or post-increment and t
43 was A0 or A1, the address register was not bei
44 of the operation. This has been corrected.
45
46 4) Beta B.2 version had the following erratum:
47
48 Scenario:
49 ---------
50 If {i,d}mem_{read,write}_{byte,word,lo
51 a failing value to the 68060SP, the pa
52 this return value and continues with p
53 as if it never received a failing valu
54
55 Effect:
56 -------
57 For example, if a user executed "fsin.
58 ADDR should cause a "segmentation viol
59 requested by the package should return
60 to the package. Since the package curr
61 return value, the user program will co
62 next instruction, and the result creat
63 undefined.
64
65 Fix:
66 ----
67 This has been fixed in the current rel
68
69 Notes:
70 ------
71 Upon receiving a non-zero (failing) re
72 a {i,d}mem_{read,write}_{byte,word,lon
73 the package creates a 16-byte access e
74 from the current exception stack frame
75 through the "call-out" _real_access().
76 as described in the MC68060 User's Man
77
78 For instruction read access errors, th
79 SR = SR at time of except
80 PC = PC of instruction be
81 VOFF = $4008 (stack frame f
82 ADDRESS = PC of instruction be
83 FSLW = FAULT STATUS LONGWOR
84
85 The valid FSLW bits are:
86 bit 27 = 1 (misal
87 bit 24 = 1 (read)
88 bit 23 = 0 (write
89 bit 22:21 = 10 (SIZE
90 bit 20:19 = 00 (TT)
91 bit 18:16 = x10 (TM; x
92 bit 15 = 1 (IO)
93 bit 0 = 1 (Softw
94
95 all other bits are EQUAL TO ZERO and c
96 "call-out" stub by the user as appropr
97 stated that ONLY "bit 0" would be set.
98 other bits.
99
100 For data read/write access errors, the
101 SR = SR at time of except
102 PC = PC of instruction be
103 VOFF = $4008 (stack frame f
104 ADDRESS = Address of source or
105 FSLW = FAULT STATUS LONGWOR
106
107 The valid FSLW bits are:
108 bit 27 = 0 (misal
109 bit 24 = x (read;
110 bit 23 = x (write
111 bit 22:21 = xx (SIZE;
112 bit 20:19 = 00 (TT)
113 bit 18:16 = x01 (TM; x
114 bit 15 = 0 (IO)
115 bit 0 = 1 (Softw
116
117 all other bits are EQUAL TO ZERO and c
118 "call-out" stub by the user as appropr
119 stated that ONLY "bit 0" would be set.
120 other bits.
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