1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 c
4 *
5 * Copyright (c) 2000-2001 Lineo Inc. <ww
6 * Copyright (c) 2000-2001 Lineo Canada C
7 * Copyright (C) 1999 Vladimir Gurev
8 * Bare & Hare So
9 * Based on include/asm-m68knommu/MC68332.h
10 * Copyright (C) 1998 Kenneth Albanowski <kja
11 * The Silver Hammer Group
12 *
13 * M68VZ328 fixes by Evan Stawnyczy <evan@line
14 * vz multiport fixes by Michael Leslie <mlesl
15 */
16
17 #ifndef _MC68VZ328_H_
18 #define _MC68VZ328_H_
19
20 #define BYTE_REF(addr) (*((volatile unsigned c
21 #define WORD_REF(addr) (*((volatile unsigned s
22 #define LONG_REF(addr) (*((volatile unsigned l
23
24 #define PUT_FIELD(field, val) (((val) << field
25 #define GET_FIELD(reg, field) (((reg) & field#
26
27 /**********
28 *
29 * 0xFFFFF0xx -- System Control
30 *
31 **********/
32
33 /*
34 * System Control Register (SCR)
35 */
36 #define SCR_ADDR 0xfffff000
37 #define SCR BYTE_REF(SCR_ADDR)
38
39 #define SCR_WDTH8 0x01 /* 8-Bit Width
40 #define SCR_DMAP 0x04 /* Double Map
41 #define SCR_SO 0x08 /* Supervisor
42 #define SCR_BETEN 0x10 /* Bus-Error T
43 #define SCR_PRV 0x20 /* Privilege V
44 #define SCR_WPV 0x40 /* Write Prote
45 #define SCR_BETO 0x80 /* Bus-Error T
46
47 /*
48 * Silicon ID Register (Mask Revision Register
49 */
50 #define MRR_ADDR 0xfffff004
51 #define MRR LONG_REF(MRR_ADDR)
52
53 /**********
54 *
55 * 0xFFFFF1xx -- Chip-Select logic
56 *
57 **********/
58
59 /*
60 * Chip Select Group Base Registers
61 */
62 #define CSGBA_ADDR 0xfffff100
63 #define CSGBB_ADDR 0xfffff102
64
65 #define CSGBC_ADDR 0xfffff104
66 #define CSGBD_ADDR 0xfffff106
67
68 #define CSGBA WORD_REF(CSGBA_ADDR)
69 #define CSGBB WORD_REF(CSGBB_ADDR)
70 #define CSGBC WORD_REF(CSGBC_ADDR)
71 #define CSGBD WORD_REF(CSGBD_ADDR)
72
73 /*
74 * Chip Select Registers
75 */
76 #define CSA_ADDR 0xfffff110
77 #define CSB_ADDR 0xfffff112
78 #define CSC_ADDR 0xfffff114
79 #define CSD_ADDR 0xfffff116
80
81 #define CSA WORD_REF(CSA_ADDR)
82 #define CSB WORD_REF(CSB_ADDR)
83 #define CSC WORD_REF(CSC_ADDR)
84 #define CSD WORD_REF(CSD_ADDR)
85
86 #define CSA_EN 0x0001 /* Chi
87 #define CSA_SIZ_MASK 0x000e /* Chi
88 #define CSA_SIZ_SHIFT 1
89 #define CSA_WS_MASK 0x0070 /* Wai
90 #define CSA_WS_SHIFT 4
91 #define CSA_BSW 0x0080 /* Dat
92 #define CSA_FLASH 0x0100 /* FLA
93 #define CSA_RO 0x8000 /* Rea
94
95 #define CSB_EN 0x0001 /* Chi
96 #define CSB_SIZ_MASK 0x000e /* Chi
97 #define CSB_SIZ_SHIFT 1
98 #define CSB_WS_MASK 0x0070 /* Wai
99 #define CSB_WS_SHIFT 4
100 #define CSB_BSW 0x0080 /* Dat
101 #define CSB_FLASH 0x0100 /* FLA
102 #define CSB_UPSIZ_MASK 0x1800 /* Unp
103 #define CSB_UPSIZ_SHIFT 11
104 #define CSB_ROP 0x2000 /* Rea
105 #define CSB_SOP 0x4000 /* Sup
106 #define CSB_RO 0x8000 /* Rea
107
108 #define CSC_EN 0x0001 /* Chi
109 #define CSC_SIZ_MASK 0x000e /* Chi
110 #define CSC_SIZ_SHIFT 1
111 #define CSC_WS_MASK 0x0070 /* Wai
112 #define CSC_WS_SHIFT 4
113 #define CSC_BSW 0x0080 /* Dat
114 #define CSC_FLASH 0x0100 /* FLA
115 #define CSC_UPSIZ_MASK 0x1800 /* Unp
116 #define CSC_UPSIZ_SHIFT 11
117 #define CSC_ROP 0x2000 /* Rea
118 #define CSC_SOP 0x4000 /* Sup
119 #define CSC_RO 0x8000 /* Rea
120
121 #define CSD_EN 0x0001 /* Chi
122 #define CSD_SIZ_MASK 0x000e /* Chi
123 #define CSD_SIZ_SHIFT 1
124 #define CSD_WS_MASK 0x0070 /* Wai
125 #define CSD_WS_SHIFT 4
126 #define CSD_BSW 0x0080 /* Dat
127 #define CSD_FLASH 0x0100 /* FLA
128 #define CSD_DRAM 0x0200 /* Dra
129 #define CSD_COMB 0x0400 /* Com
130 #define CSD_UPSIZ_MASK 0x1800 /* Unp
131 #define CSD_UPSIZ_SHIFT 11
132 #define CSD_ROP 0x2000 /* Rea
133 #define CSD_SOP 0x4000 /* Sup
134 #define CSD_RO 0x8000 /* Rea
135
136 /*
137 * Emulation Chip-Select Register
138 */
139 #define EMUCS_ADDR 0xfffff118
140 #define EMUCS WORD_REF(EMUCS_ADDR)
141
142 #define EMUCS_WS_MASK 0x0070
143 #define EMUCS_WS_SHIFT 4
144
145 /**********
146 *
147 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Pow
148 *
149 **********/
150
151 /*
152 * PLL Control Register
153 */
154 #define PLLCR_ADDR 0xfffff200
155 #define PLLCR WORD_REF(PLLCR_ADDR)
156
157 #define PLLCR_DISPLL 0x0008 /* Dis
158 #define PLLCR_CLKEN 0x0010 /* Clo
159 #define PLLCR_PRESC 0x0020 /* VCO
160 #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* Sys
161 #define PLLCR_SYSCLK_SEL_SHIFT 8
162 #define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD
163 #define PLLCR_LCDCLK_SEL_SHIFT 11
164
165 /* '328-compatible definitions */
166 #define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_S
167 #define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_S
168
169 /*
170 * PLL Frequency Select Register
171 */
172 #define PLLFSR_ADDR 0xfffff202
173 #define PLLFSR WORD_REF(PLLFSR_ADDR)
174
175 #define PLLFSR_PC_MASK 0x00ff /* P C
176 #define PLLFSR_PC_SHIFT 0
177 #define PLLFSR_QC_MASK 0x0f00 /* Q C
178 #define PLLFSR_QC_SHIFT 8
179 #define PLLFSR_PROT 0x4000 /* Pro
180 #define PLLFSR_CLK32 0x8000 /* Clo
181
182 /*
183 * Power Control Register
184 */
185 #define PCTRL_ADDR 0xfffff207
186 #define PCTRL BYTE_REF(PCTRL_ADDR)
187
188 #define PCTRL_WIDTH_MASK 0x1f /* CPU
189 #define PCTRL_WIDTH_SHIFT 0
190 #define PCTRL_PCEN 0x80 /* Pow
191
192 /**********
193 *
194 * 0xFFFFF3xx -- Interrupt Controller
195 *
196 **********/
197
198 /*
199 * Interrupt Vector Register
200 */
201 #define IVR_ADDR 0xfffff300
202 #define IVR BYTE_REF(IVR_ADDR)
203
204 #define IVR_VECTOR_MASK 0xF8
205
206 /*
207 * Interrupt control Register
208 */
209 #define ICR_ADDR 0xfffff302
210 #define ICR WORD_REF(ICR_ADDR)
211
212 #define ICR_POL5 0x0080 /* Polarity Co
213 #define ICR_ET6 0x0100 /* Edge Trigge
214 #define ICR_ET3 0x0200 /* Edge Trigge
215 #define ICR_ET2 0x0400 /* Edge Trigge
216 #define ICR_ET1 0x0800 /* Edge Trigge
217 #define ICR_POL6 0x1000 /* Polarity Co
218 #define ICR_POL3 0x2000 /* Polarity Co
219 #define ICR_POL2 0x4000 /* Polarity Co
220 #define ICR_POL1 0x8000 /* Polarity Co
221
222 /*
223 * Interrupt Mask Register
224 */
225 #define IMR_ADDR 0xfffff304
226 #define IMR LONG_REF(IMR_ADDR)
227
228 /*
229 * Define the names for bit positions first. T
230 * request_irq
231 */
232 #define SPI2_IRQ_NUM 0 /* SPI 2 inter
233 #define TMR_IRQ_NUM 1 /* Timer 1 int
234 #define UART1_IRQ_NUM 2 /* UART 1 inte
235 #define WDT_IRQ_NUM 3 /* Watchdog Ti
236 #define RTC_IRQ_NUM 4 /* RTC interru
237 #define TMR2_IRQ_NUM 5 /* Timer 2 int
238 #define KB_IRQ_NUM 6 /* Keyboard In
239 #define PWM1_IRQ_NUM 7 /* Pulse-Width
240 #define INT0_IRQ_NUM 8 /* External IN
241 #define INT1_IRQ_NUM 9 /* External IN
242 #define INT2_IRQ_NUM 10 /* External IN
243 #define INT3_IRQ_NUM 11 /* External IN
244 #define UART2_IRQ_NUM 12 /* UART 2 inte
245 #define PWM2_IRQ_NUM 13 /* Pulse-Width
246 #define IRQ1_IRQ_NUM 16 /* IRQ1 */
247 #define IRQ2_IRQ_NUM 17 /* IRQ2 */
248 #define IRQ3_IRQ_NUM 18 /* IRQ3 */
249 #define IRQ6_IRQ_NUM 19 /* IRQ6 */
250 #define IRQ5_IRQ_NUM 20 /* IRQ5 */
251 #define SPI1_IRQ_NUM 21 /* SPI 1 inter
252 #define SAM_IRQ_NUM 22 /* Sampling Ti
253 #define EMIQ_IRQ_NUM 23 /* Emulator In
254
255 #define SPI_IRQ_NUM SPI2_IRQ_NUM
256
257 /* '328-compatible definitions */
258 #define SPIM_IRQ_NUM SPI_IRQ_NUM
259 #define TMR1_IRQ_NUM TMR_IRQ_NUM
260 #define UART_IRQ_NUM UART1_IRQ_NUM
261
262 /*
263 * Here go the bitmasks themselves
264 */
265 #define IMR_MSPI (1 << SPI_IRQ_NUM)
266 #define IMR_MTMR (1 << TMR_IRQ_NUM)
267 #define IMR_MUART (1 << UART_IRQ_NUM)
268 #define IMR_MWDT (1 << WDT_IRQ_NUM)
269 #define IMR_MRTC (1 << RTC_IRQ_NUM)
270 #define IMR_MKB (1 << KB_IRQ_NUM)
271 #define IMR_MPWM (1 << PWM_IRQ_NUM)
272 #define IMR_MINT0 (1 << INT0_IRQ_NUM)
273 #define IMR_MINT1 (1 << INT1_IRQ_NUM)
274 #define IMR_MINT2 (1 << INT2_IRQ_NUM)
275 #define IMR_MINT3 (1 << INT3_IRQ_NUM)
276 #define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM)
277 #define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM)
278 #define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM)
279 #define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM)
280 #define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM)
281 #define IMR_MSAM (1 << SAM_IRQ_NUM)
282 #define IMR_MEMIQ (1 << EMIQ_IRQ_NUM)
283
284 /* '328-compatible definitions */
285 #define IMR_MSPIM IMR_MSPI
286 #define IMR_MTMR1 IMR_MTMR
287
288 /*
289 * Interrupt Status Register
290 */
291 #define ISR_ADDR 0xfffff30c
292 #define ISR LONG_REF(ISR_ADDR)
293
294 #define ISR_SPI (1 << SPI_IRQ_NUM)
295 #define ISR_TMR (1 << TMR_IRQ_NUM)
296 #define ISR_UART (1 << UART_IRQ_NUM)
297 #define ISR_WDT (1 << WDT_IRQ_NUM)
298 #define ISR_RTC (1 << RTC_IRQ_NUM)
299 #define ISR_KB (1 << KB_IRQ_NUM)
300 #define ISR_PWM (1 << PWM_IRQ_NUM)
301 #define ISR_INT0 (1 << INT0_IRQ_NUM)
302 #define ISR_INT1 (1 << INT1_IRQ_NUM)
303 #define ISR_INT2 (1 << INT2_IRQ_NUM)
304 #define ISR_INT3 (1 << INT3_IRQ_NUM)
305 #define ISR_IRQ1 (1 << IRQ1_IRQ_NUM)
306 #define ISR_IRQ2 (1 << IRQ2_IRQ_NUM)
307 #define ISR_IRQ3 (1 << IRQ3_IRQ_NUM)
308 #define ISR_IRQ6 (1 << IRQ6_IRQ_NUM)
309 #define ISR_IRQ5 (1 << IRQ5_IRQ_NUM)
310 #define ISR_SAM (1 << SAM_IRQ_NUM)
311 #define ISR_EMIQ (1 << EMIQ_IRQ_NUM)
312
313 /* '328-compatible definitions */
314 #define ISR_SPIM ISR_SPI
315 #define ISR_TMR1 ISR_TMR
316
317 /*
318 * Interrupt Pending Register
319 */
320 #define IPR_ADDR 0xfffff30c
321 #define IPR LONG_REF(IPR_ADDR)
322
323 #define IPR_SPI (1 << SPI_IRQ_NUM)
324 #define IPR_TMR (1 << TMR_IRQ_NUM)
325 #define IPR_UART (1 << UART_IRQ_NUM)
326 #define IPR_WDT (1 << WDT_IRQ_NUM)
327 #define IPR_RTC (1 << RTC_IRQ_NUM)
328 #define IPR_KB (1 << KB_IRQ_NUM)
329 #define IPR_PWM (1 << PWM_IRQ_NUM)
330 #define IPR_INT0 (1 << INT0_IRQ_NUM)
331 #define IPR_INT1 (1 << INT1_IRQ_NUM)
332 #define IPR_INT2 (1 << INT2_IRQ_NUM)
333 #define IPR_INT3 (1 << INT3_IRQ_NUM)
334 #define IPR_IRQ1 (1 << IRQ1_IRQ_NUM)
335 #define IPR_IRQ2 (1 << IRQ2_IRQ_NUM)
336 #define IPR_IRQ3 (1 << IRQ3_IRQ_NUM)
337 #define IPR_IRQ6 (1 << IRQ6_IRQ_NUM)
338 #define IPR_IRQ5 (1 << IRQ5_IRQ_NUM)
339 #define IPR_SAM (1 << SAM_IRQ_NUM)
340 #define IPR_EMIQ (1 << EMIQ_IRQ_NUM)
341
342 /* '328-compatible definitions */
343 #define IPR_SPIM IPR_SPI
344 #define IPR_TMR1 IPR_TMR
345
346 /**********
347 *
348 * 0xFFFFF4xx -- Parallel Ports
349 *
350 **********/
351
352 /*
353 * Port A
354 */
355 #define PADIR_ADDR 0xfffff400
356 #define PADATA_ADDR 0xfffff401
357 #define PAPUEN_ADDR 0xfffff402
358
359 #define PADIR BYTE_REF(PADIR_ADDR)
360 #define PADATA BYTE_REF(PADATA_ADDR)
361 #define PAPUEN BYTE_REF(PAPUEN_ADDR)
362
363 #define PA(x) (1 << (x))
364
365 /*
366 * Port B
367 */
368 #define PBDIR_ADDR 0xfffff408
369 #define PBDATA_ADDR 0xfffff409
370 #define PBPUEN_ADDR 0xfffff40a
371 #define PBSEL_ADDR 0xfffff40b
372
373 #define PBDIR BYTE_REF(PBDIR_ADDR)
374 #define PBDATA BYTE_REF(PBDATA_ADDR)
375 #define PBPUEN BYTE_REF(PBPUEN_ADDR)
376 #define PBSEL BYTE_REF(PBSEL_ADDR)
377
378 #define PB(x) (1 << (x))
379
380 #define PB_CSB0 0x01 /* Use CSB0
381 #define PB_CSB1 0x02 /* Use CSB1
382 #define PB_CSC0_RAS0 0x04 /* Use CSC0/RA
383 #define PB_CSC1_RAS1 0x08 /* Use CSC1/RA
384 #define PB_CSD0_CAS0 0x10 /* Use CSD0/CA
385 #define PB_CSD1_CAS1 0x20 /* Use CSD1/CA
386 #define PB_TIN_TOUT 0x40 /* Use TIN/TOU
387 #define PB_PWMO 0x80 /* Use PWMO
388
389 /*
390 * Port C
391 */
392 #define PCDIR_ADDR 0xfffff410
393 #define PCDATA_ADDR 0xfffff411
394 #define PCPDEN_ADDR 0xfffff412
395 #define PCSEL_ADDR 0xfffff413
396
397 #define PCDIR BYTE_REF(PCDIR_ADDR)
398 #define PCDATA BYTE_REF(PCDATA_ADDR)
399 #define PCPDEN BYTE_REF(PCPDEN_ADDR)
400 #define PCSEL BYTE_REF(PCSEL_ADDR)
401
402 #define PC(x) (1 << (x))
403
404 #define PC_LD0 0x01 /* Use LD0 as
405 #define PC_LD1 0x02 /* Use LD1 as
406 #define PC_LD2 0x04 /* Use LD2 as
407 #define PC_LD3 0x08 /* Use LD3 as
408 #define PC_LFLM 0x10 /* Use LFLM as
409 #define PC_LLP 0x20 /* Use LLP as
410 #define PC_LCLK 0x40 /* Use LCLK as
411 #define PC_LACD 0x80 /* Use LACD as
412
413 /*
414 * Port D
415 */
416 #define PDDIR_ADDR 0xfffff418
417 #define PDDATA_ADDR 0xfffff419
418 #define PDPUEN_ADDR 0xfffff41a
419 #define PDSEL_ADDR 0xfffff41b
420 #define PDPOL_ADDR 0xfffff41c
421 #define PDIRQEN_ADDR 0xfffff41d
422 #define PDKBEN_ADDR 0xfffff41e
423 #define PDIQEG_ADDR 0xfffff41f
424
425 #define PDDIR BYTE_REF(PDDIR_ADDR)
426 #define PDDATA BYTE_REF(PDDATA_ADDR)
427 #define PDPUEN BYTE_REF(PDPUEN_ADDR)
428 #define PDSEL BYTE_REF(PDSEL_ADDR)
429 #define PDPOL BYTE_REF(PDPOL_ADDR)
430 #define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
431 #define PDKBEN BYTE_REF(PDKBEN_ADDR)
432 #define PDIQEG BYTE_REF(PDIQEG_ADDR)
433
434 #define PD(x) (1 << (x))
435
436 #define PD_INT0 0x01 /* Use INT0 as
437 #define PD_INT1 0x02 /* Use INT1 as
438 #define PD_INT2 0x04 /* Use INT2 as
439 #define PD_INT3 0x08 /* Use INT3 as
440 #define PD_IRQ1 0x10 /* Use IRQ1 as
441 #define PD_IRQ2 0x20 /* Use IRQ2 as
442 #define PD_IRQ3 0x40 /* Use IRQ3 as
443 #define PD_IRQ6 0x80 /* Use IRQ6 as
444
445 /*
446 * Port E
447 */
448 #define PEDIR_ADDR 0xfffff420
449 #define PEDATA_ADDR 0xfffff421
450 #define PEPUEN_ADDR 0xfffff422
451 #define PESEL_ADDR 0xfffff423
452
453 #define PEDIR BYTE_REF(PEDIR_ADDR)
454 #define PEDATA BYTE_REF(PEDATA_ADDR)
455 #define PEPUEN BYTE_REF(PEPUEN_ADDR)
456 #define PESEL BYTE_REF(PESEL_ADDR)
457
458 #define PE(x) (1 << (x))
459
460 #define PE_SPMTXD 0x01 /* Use SPMTXD
461 #define PE_SPMRXD 0x02 /* Use SPMRXD
462 #define PE_SPMCLK 0x04 /* Use SPMCLK
463 #define PE_DWE 0x08 /* Use DWE
464 #define PE_RXD 0x10 /* Use RXD
465 #define PE_TXD 0x20 /* Use TXD
466 #define PE_RTS 0x40 /* Use RTS
467 #define PE_CTS 0x80 /* Use CTS
468
469 /*
470 * Port F
471 */
472 #define PFDIR_ADDR 0xfffff428
473 #define PFDATA_ADDR 0xfffff429
474 #define PFPUEN_ADDR 0xfffff42a
475 #define PFSEL_ADDR 0xfffff42b
476
477 #define PFDIR BYTE_REF(PFDIR_ADDR)
478 #define PFDATA BYTE_REF(PFDATA_ADDR)
479 #define PFPUEN BYTE_REF(PFPUEN_ADDR)
480 #define PFSEL BYTE_REF(PFSEL_ADDR)
481
482 #define PF(x) (1 << (x))
483
484 #define PF_LCONTRAST 0x01 /* Use LCONTRA
485 #define PF_IRQ5 0x02 /* Use IRQ5
486 #define PF_CLKO 0x04 /* Use CLKO
487 #define PF_A20 0x08 /* Use A20
488 #define PF_A21 0x10 /* Use A21
489 #define PF_A22 0x20 /* Use A22
490 #define PF_A23 0x40 /* Use A23
491 #define PF_CSA1 0x80 /* Use CSA1
492
493 /*
494 * Port G
495 */
496 #define PGDIR_ADDR 0xfffff430
497 #define PGDATA_ADDR 0xfffff431
498 #define PGPUEN_ADDR 0xfffff432
499 #define PGSEL_ADDR 0xfffff433
500
501 #define PGDIR BYTE_REF(PGDIR_ADDR)
502 #define PGDATA BYTE_REF(PGDATA_ADDR)
503 #define PGPUEN BYTE_REF(PGPUEN_ADDR)
504 #define PGSEL BYTE_REF(PGSEL_ADDR)
505
506 #define PG(x) (1 << (x))
507
508 #define PG_BUSW_DTACK 0x01 /* Use BUSW/DT
509 #define PG_A0 0x02 /* Use A0
510 #define PG_EMUIRQ 0x04 /* Use EMUIRQ
511 #define PG_HIZ_P_D 0x08 /* Use HIZ/P/D
512 #define PG_EMUCS 0x10 /* Use EMUCS
513 #define PG_EMUBRK 0x20 /* Use EMUBRK
514
515 /*
516 * Port J
517 */
518 #define PJDIR_ADDR 0xfffff438
519 #define PJDATA_ADDR 0xfffff439
520 #define PJPUEN_ADDR 0xfffff43A
521 #define PJSEL_ADDR 0xfffff43B
522
523 #define PJDIR BYTE_REF(PJDIR_ADDR)
524 #define PJDATA BYTE_REF(PJDATA_ADDR)
525 #define PJPUEN BYTE_REF(PJPUEN_ADDR)
526 #define PJSEL BYTE_REF(PJSEL_ADDR)
527
528 #define PJ(x) (1 << (x))
529
530 /*
531 * Port K
532 */
533 #define PKDIR_ADDR 0xfffff440
534 #define PKDATA_ADDR 0xfffff441
535 #define PKPUEN_ADDR 0xfffff442
536 #define PKSEL_ADDR 0xfffff443
537
538 #define PKDIR BYTE_REF(PKDIR_ADDR)
539 #define PKDATA BYTE_REF(PKDATA_ADDR)
540 #define PKPUEN BYTE_REF(PKPUEN_ADDR)
541 #define PKSEL BYTE_REF(PKSEL_ADDR)
542
543 #define PK(x) (1 << (x))
544
545 #define PK_DATAREADY 0x01 /* Use
546 #define PK_PWM2 0x01 /* Use PWM2 a
547 #define PK_R_W 0x02 /* Use R/W as
548 #define PK_LDS 0x04 /* Use /LDS a
549 #define PK_UDS 0x08 /* Use /UDS a
550 #define PK_LD4 0x10 /* Use LD4 as
551 #define PK_LD5 0x20 /* Use LD5 as
552 #define PK_LD6 0x40 /* Use LD6 as
553 #define PK_LD7 0x80 /* Use LD7 as
554
555 #define PJDIR_ADDR 0xfffff438
556 #define PJDATA_ADDR 0xfffff439
557 #define PJPUEN_ADDR 0xfffff43A
558 #define PJSEL_ADDR 0xfffff43B
559
560 #define PJDIR BYTE_REF(PJDIR_ADDR)
561 #define PJDATA BYTE_REF(PJDATA_ADDR)
562 #define PJPUEN BYTE_REF(PJPUEN_ADDR)
563 #define PJSEL BYTE_REF(PJSEL_ADDR)
564
565 #define PJ(x) (1 << (x))
566
567 #define PJ_MOSI 0x01 /* Use MOSI
568 #define PJ_MISO 0x02 /* Use MISO
569 #define PJ_SPICLK1 0x04 /* Use SPICLK1
570 #define PJ_SS 0x08 /* Use SS
571 #define PJ_RXD2 0x10 /* Use RXD2
572 #define PJ_TXD2 0x20 /* Use TXD2
573 #define PJ_RTS2 0x40 /* Use RTS2
574 #define PJ_CTS2 0x80 /* Use CTS2
575
576 /*
577 * Port M
578 */
579 #define PMDIR_ADDR 0xfffff448
580 #define PMDATA_ADDR 0xfffff449
581 #define PMPUEN_ADDR 0xfffff44a
582 #define PMSEL_ADDR 0xfffff44b
583
584 #define PMDIR BYTE_REF(PMDIR_ADDR)
585 #define PMDATA BYTE_REF(PMDATA_ADDR)
586 #define PMPUEN BYTE_REF(PMPUEN_ADDR)
587 #define PMSEL BYTE_REF(PMSEL_ADDR)
588
589 #define PM(x) (1 << (x))
590
591 #define PM_SDCLK 0x01 /* Use SDCLK
592 #define PM_SDCE 0x02 /* Use SDCE
593 #define PM_DQMH 0x04 /* Use DQMH
594 #define PM_DQML 0x08 /* Use DQML
595 #define PM_SDA10 0x10 /* Use SDA10
596 #define PM_DMOE 0x20 /* Use DMOE
597
598 /**********
599 *
600 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
601 *
602 **********/
603
604 /*
605 * PWM Control Register
606 */
607 #define PWMC_ADDR 0xfffff500
608 #define PWMC WORD_REF(PWMC_ADDR)
609
610 #define PWMC_CLKSEL_MASK 0x0003 /* Clo
611 #define PWMC_CLKSEL_SHIFT 0
612 #define PWMC_REPEAT_MASK 0x000c /* Sam
613 #define PWMC_REPEAT_SHIFT 2
614 #define PWMC_EN 0x0010 /* Ena
615 #define PMNC_FIFOAV 0x0020 /* FIF
616 #define PWMC_IRQEN 0x0040 /* Int
617 #define PWMC_IRQ 0x0080 /* Int
618 #define PWMC_PRESCALER_MASK 0x7f00 /* Inc
619 #define PWMC_PRESCALER_SHIFT 8
620 #define PWMC_CLKSRC 0x8000 /* Clo
621
622 /* '328-compatible definitions */
623 #define PWMC_PWMEN PWMC_EN
624
625 /*
626 * PWM Sample Register
627 */
628 #define PWMS_ADDR 0xfffff502
629 #define PWMS WORD_REF(PWMS_ADDR)
630
631 /*
632 * PWM Period Register
633 */
634 #define PWMP_ADDR 0xfffff504
635 #define PWMP BYTE_REF(PWMP_ADDR)
636
637 /*
638 * PWM Counter Register
639 */
640 #define PWMCNT_ADDR 0xfffff505
641 #define PWMCNT BYTE_REF(PWMCNT_ADDR)
642
643 /**********
644 *
645 * 0xFFFFF6xx -- General-Purpose Timer
646 *
647 **********/
648
649 /*
650 * Timer Control register
651 */
652 #define TCTL_ADDR 0xfffff600
653 #define TCTL WORD_REF(TCTL_ADDR)
654
655 #define TCTL_TEN 0x0001 /* Tim
656 #define TCTL_CLKSOURCE_MASK 0x000e /* Clo
657 #define TCTL_CLKSOURCE_STOP 0x0000
658 #define TCTL_CLKSOURCE_SYSCLK 0x0002
659 #define TCTL_CLKSOURCE_SYSCLK_16 0x0004
660 #define TCTL_CLKSOURCE_TIN 0x0006
661 #define TCTL_CLKSOURCE_32KHZ 0x0008
662 #define TCTL_IRQEN 0x0010 /* IRQ
663 #define TCTL_OM 0x0020 /* Out
664 #define TCTL_CAP_MASK 0x00c0 /* Cap
665 #define TCTL_CAP_RE 0x0040
666 #define TCTL_CAP_FE 0x0080
667 #define TCTL_FRR 0x0010 /* Fre
668
669 /* '328-compatible definitions */
670 #define TCTL1_ADDR TCTL_ADDR
671 #define TCTL1 TCTL
672
673 /*
674 * Timer Prescaler Register
675 */
676 #define TPRER_ADDR 0xfffff602
677 #define TPRER WORD_REF(TPRER_ADDR)
678
679 /* '328-compatible definitions */
680 #define TPRER1_ADDR TPRER_ADDR
681 #define TPRER1 TPRER
682
683 /*
684 * Timer Compare Register
685 */
686 #define TCMP_ADDR 0xfffff604
687 #define TCMP WORD_REF(TCMP_ADDR)
688
689 /* '328-compatible definitions */
690 #define TCMP1_ADDR TCMP_ADDR
691 #define TCMP1 TCMP
692
693 /*
694 * Timer Capture register
695 */
696 #define TCR_ADDR 0xfffff606
697 #define TCR WORD_REF(TCR_ADDR)
698
699 /* '328-compatible definitions */
700 #define TCR1_ADDR TCR_ADDR
701 #define TCR1 TCR
702
703 /*
704 * Timer Counter Register
705 */
706 #define TCN_ADDR 0xfffff608
707 #define TCN WORD_REF(TCN_ADDR)
708
709 /* '328-compatible definitions */
710 #define TCN1_ADDR TCN_ADDR
711 #define TCN1 TCN
712
713 /*
714 * Timer Status Register
715 */
716 #define TSTAT_ADDR 0xfffff60a
717 #define TSTAT WORD_REF(TSTAT_ADDR)
718
719 #define TSTAT_COMP 0x0001 /* Com
720 #define TSTAT_CAPT 0x0001 /* Cap
721
722 /* '328-compatible definitions */
723 #define TSTAT1_ADDR TSTAT_ADDR
724 #define TSTAT1 TSTAT
725
726 /**********
727 *
728 * 0xFFFFF8xx -- Serial Peripheral Interface M
729 *
730 **********/
731
732 /*
733 * SPIM Data Register
734 */
735 #define SPIMDATA_ADDR 0xfffff800
736 #define SPIMDATA WORD_REF(SPIMDATA_ADDR
737
738 /*
739 * SPIM Control/Status Register
740 */
741 #define SPIMCONT_ADDR 0xfffff802
742 #define SPIMCONT WORD_REF(SPIMCONT_ADDR
743
744 #define SPIMCONT_BIT_COUNT_MASK 0x000f /* Tra
745 #define SPIMCONT_BIT_COUNT_SHIFT 0
746 #define SPIMCONT_POL 0x0010 /* SPM
747 #define SPIMCONT_PHA 0x0020 /* Clo
748 #define SPIMCONT_IRQEN 0x0040 /* IRQ
749 #define SPIMCONT_IRQ 0x0080 /* Int
750 #define SPIMCONT_XCH 0x0100 /* Exc
751 #define SPIMCONT_ENABLE 0x0200 /* Ena
752 #define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPI
753 #define SPIMCONT_DATA_RATE_SHIFT 13
754
755 /* '328-compatible definitions */
756 #define SPIMCONT_SPIMIRQ SPIMCONT_IRQ
757 #define SPIMCONT_SPIMEN SPIMCONT_ENABL
758
759 /**********
760 *
761 * 0xFFFFF9xx -- UART
762 *
763 **********/
764
765 /*
766 * UART Status/Control Register
767 */
768
769 #define USTCNT_ADDR 0xfffff900
770 #define USTCNT WORD_REF(USTCNT_ADDR)
771
772 #define USTCNT_TXAE 0x0001 /* Transmitter
773 #define USTCNT_TXHE 0x0002 /* Transmitter
774 #define USTCNT_TXEE 0x0004 /* Transmitter
775 #define USTCNT_RXRE 0x0008 /* Receiver Re
776 #define USTCNT_RXHE 0x0010 /* Receiver Ha
777 #define USTCNT_RXFE 0x0020 /* Receiver Fu
778 #define USTCNT_CTSD 0x0040 /* CTS Delta I
779 #define USTCNT_ODEN 0x0080 /* Old Data In
780 #define USTCNT_8_7 0x0100 /* Eight or se
781 #define USTCNT_STOP 0x0200 /* Stop bit tr
782 #define USTCNT_ODD 0x0400 /* Odd Parity
783 #define USTCNT_PEN 0x0800 /* Parity Enab
784 #define USTCNT_CLKM 0x1000 /* Clock Mode
785 #define USTCNT_TXEN 0x2000 /* Transmitter
786 #define USTCNT_RXEN 0x4000 /* Receiver En
787 #define USTCNT_UEN 0x8000 /* UART Enable
788
789 /* '328-compatible definitions */
790 #define USTCNT_TXAVAILEN USTCNT_TXAE
791 #define USTCNT_TXHALFEN USTCNT_TXHE
792 #define USTCNT_TXEMPTYEN USTCNT_TXEE
793 #define USTCNT_RXREADYEN USTCNT_RXRE
794 #define USTCNT_RXHALFEN USTCNT_RXHE
795 #define USTCNT_RXFULLEN USTCNT_RXFE
796 #define USTCNT_CTSDELTAEN USTCNT_CTSD
797 #define USTCNT_ODD_EVEN USTCNT_ODD
798 #define USTCNT_PARITYEN USTCNT_PEN
799 #define USTCNT_CLKMODE USTCNT_CLKM
800 #define USTCNT_UARTEN USTCNT_UEN
801
802 /*
803 * UART Baud Control Register
804 */
805 #define UBAUD_ADDR 0xfffff902
806 #define UBAUD WORD_REF(UBAUD_ADDR)
807
808 #define UBAUD_PRESCALER_MASK 0x003f /* Act
809 #define UBAUD_PRESCALER_SHIFT 0
810 #define UBAUD_DIVIDE_MASK 0x0700 /* Bau
811 #define UBAUD_DIVIDE_SHIFT 8
812 #define UBAUD_BAUD_SRC 0x0800 /* Bau
813 #define UBAUD_UCLKDIR 0x2000 /* UCL
814
815 /*
816 * UART Receiver Register
817 */
818 #define URX_ADDR 0xfffff904
819 #define URX WORD_REF(URX_ADDR)
820
821 #define URX_RXDATA_ADDR 0xfffff905
822 #define URX_RXDATA BYTE_REF(URX_RXDATA_AD
823
824 #define URX_RXDATA_MASK 0x00ff /* Received da
825 #define URX_RXDATA_SHIFT 0
826 #define URX_PARITY_ERROR 0x0100 /* Parity Erro
827 #define URX_BREAK 0x0200 /* Break Detec
828 #define URX_FRAME_ERROR 0x0400 /* Framing Err
829 #define URX_OVRUN 0x0800 /* Serial Over
830 #define URX_OLD_DATA 0x1000 /* Old data in
831 #define URX_DATA_READY 0x2000 /* Data Ready
832 #define URX_FIFO_HALF 0x4000 /* FIFO is Hal
833 #define URX_FIFO_FULL 0x8000 /* FIFO is Ful
834
835 /*
836 * UART Transmitter Register
837 */
838 #define UTX_ADDR 0xfffff906
839 #define UTX WORD_REF(UTX_ADDR)
840
841 #define UTX_TXDATA_ADDR 0xfffff907
842 #define UTX_TXDATA BYTE_REF(UTX_TXDATA_AD
843
844 #define UTX_TXDATA_MASK 0x00ff /* Data to be
845 #define UTX_TXDATA_SHIFT 0
846 #define UTX_CTS_DELTA 0x0100 /* CTS changed
847 #define UTX_CTS_STAT 0x0200 /* CTS State *
848 #define UTX_BUSY 0x0400 /* FIFO is bus
849 #define UTX_NOCTS 0x0800 /* Ignore CTS
850 #define UTX_SEND_BREAK 0x1000 /* Send a BREA
851 #define UTX_TX_AVAIL 0x2000 /* Transmit FI
852 #define UTX_FIFO_HALF 0x4000 /* Transmit FI
853 #define UTX_FIFO_EMPTY 0x8000 /* Transmit FI
854
855 /* '328-compatible definitions */
856 #define UTX_CTS_STATUS UTX_CTS_STAT
857 #define UTX_IGNORE_CTS UTX_NOCTS
858
859 /*
860 * UART Miscellaneous Register
861 */
862 #define UMISC_ADDR 0xfffff908
863 #define UMISC WORD_REF(UMISC_ADDR)
864
865 #define UMISC_TX_POL 0x0004 /* Transmit Po
866 #define UMISC_RX_POL 0x0008 /* Receive Pol
867 #define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopba
868 #define UMISC_IRDA_EN 0x0020 /* Infra-Red E
869 #define UMISC_RTS 0x0040 /* Set RTS sta
870 #define UMISC_RTSCONT 0x0080 /* Choose RTS
871 #define UMISC_IR_TEST 0x0400 /* IRDA Test E
872 #define UMISC_BAUD_RESET 0x0800 /* Reset Baud
873 #define UMISC_LOOP 0x1000 /* Serial Loop
874 #define UMISC_FORCE_PERR 0x2000 /* Force Parit
875 #define UMISC_CLKSRC 0x4000 /* Clock Sourc
876 #define UMISC_BAUD_TEST 0x8000 /* Enable Baud
877
878 /*
879 * UART Non-integer Prescaler Register
880 */
881 #define NIPR_ADDR 0xfffff90a
882 #define NIPR WORD_REF(NIPR_ADDR)
883
884 #define NIPR_STEP_VALUE_MASK 0x00ff /* NI
885 #define NIPR_STEP_VALUE_SHIFT 0
886 #define NIPR_SELECT_MASK 0x0700 /* Tap
887 #define NIPR_SELECT_SHIFT 8
888 #define NIPR_PRE_SEL 0x8000 /* Non
889
890
891 /* generalization of uart control registers to
892 typedef struct {
893 volatile unsigned short int ustcnt;
894 volatile unsigned short int ubaud;
895 union {
896 volatile unsigned short int w;
897 struct {
898 volatile unsigned char status;
899 volatile unsigned char rxdata;
900 } b;
901 } urx;
902 union {
903 volatile unsigned short int w;
904 struct {
905 volatile unsigned char status;
906 volatile unsigned char txdata;
907 } b;
908 } utx;
909 volatile unsigned short int umisc;
910 volatile unsigned short int nipr;
911 volatile unsigned short int hmark;
912 volatile unsigned short int unused;
913 } __packed m68328_uart;
914
915
916
917
918 /**********
919 *
920 * 0xFFFFFAxx -- LCD Controller
921 *
922 **********/
923
924 /*
925 * LCD Screen Starting Address Register
926 */
927 #define LSSA_ADDR 0xfffffa00
928 #define LSSA LONG_REF(LSSA_ADDR)
929
930 #define LSSA_SSA_MASK 0x1ffffffe /* Bit
931
932 /*
933 * LCD Virtual Page Width Register
934 */
935 #define LVPW_ADDR 0xfffffa05
936 #define LVPW BYTE_REF(LVPW_ADDR)
937
938 /*
939 * LCD Screen Width Register (not compatible w
940 */
941 #define LXMAX_ADDR 0xfffffa08
942 #define LXMAX WORD_REF(LXMAX_ADDR)
943
944 #define LXMAX_XM_MASK 0x02f0 /* Bit
945
946 /*
947 * LCD Screen Height Register
948 */
949 #define LYMAX_ADDR 0xfffffa0a
950 #define LYMAX WORD_REF(LYMAX_ADDR)
951
952 #define LYMAX_YM_MASK 0x01ff /* Bit
953
954 /*
955 * LCD Cursor X Position Register
956 */
957 #define LCXP_ADDR 0xfffffa18
958 #define LCXP WORD_REF(LCXP_ADDR)
959
960 #define LCXP_CC_MASK 0xc000 /* Cur
961 #define LCXP_CC_TRAMSPARENT 0x0000
962 #define LCXP_CC_BLACK 0x4000
963 #define LCXP_CC_REVERSED 0x8000
964 #define LCXP_CC_WHITE 0xc000
965 #define LCXP_CXP_MASK 0x02ff /* Cur
966
967 /*
968 * LCD Cursor Y Position Register
969 */
970 #define LCYP_ADDR 0xfffffa1a
971 #define LCYP WORD_REF(LCYP_ADDR)
972
973 #define LCYP_CYP_MASK 0x01ff /* Cur
974
975 /*
976 * LCD Cursor Width and Heigth Register
977 */
978 #define LCWCH_ADDR 0xfffffa1c
979 #define LCWCH WORD_REF(LCWCH_ADDR)
980
981 #define LCWCH_CH_MASK 0x001f /* Cur
982 #define LCWCH_CH_SHIFT 0
983 #define LCWCH_CW_MASK 0x1f00 /* Cur
984 #define LCWCH_CW_SHIFT 8
985
986 /*
987 * LCD Blink Control Register
988 */
989 #define LBLKC_ADDR 0xfffffa1f
990 #define LBLKC BYTE_REF(LBLKC_ADDR)
991
992 #define LBLKC_BD_MASK 0x7f /* Blink Divis
993 #define LBLKC_BD_SHIFT 0
994 #define LBLKC_BKEN 0x80 /* Blink Enabl
995
996 /*
997 * LCD Panel Interface Configuration Register
998 */
999 #define LPICF_ADDR 0xfffffa20
1000 #define LPICF BYTE_REF(LPICF_ADDR)
1001
1002 #define LPICF_GS_MASK 0x03 /* Gray-Scal
1003 #define LPICF_GS_BW 0x00
1004 #define LPICF_GS_GRAY_4 0x01
1005 #define LPICF_GS_GRAY_16 0x02
1006 #define LPICF_PBSIZ_MASK 0x0c /* Panel Bus
1007 #define LPICF_PBSIZ_1 0x00
1008 #define LPICF_PBSIZ_2 0x04
1009 #define LPICF_PBSIZ_4 0x08
1010
1011 /*
1012 * LCD Polarity Configuration Register
1013 */
1014 #define LPOLCF_ADDR 0xfffffa21
1015 #define LPOLCF BYTE_REF(LPOLCF_ADDR)
1016
1017 #define LPOLCF_PIXPOL 0x01 /* Pixel Pola
1018 #define LPOLCF_LPPOL 0x02 /* Line Pulse
1019 #define LPOLCF_FLMPOL 0x04 /* Frame Mark
1020 #define LPOLCF_LCKPOL 0x08 /* LCD Shift
1021
1022 /*
1023 * LACD (LCD Alternate Crystal Direction) Rat
1024 */
1025 #define LACDRC_ADDR 0xfffffa23
1026 #define LACDRC BYTE_REF(LACDRC_ADDR)
1027
1028 #define LACDRC_ACDSLT 0x80 /* Signal Sou
1029 #define LACDRC_ACD_MASK 0x0f /* Alternate
1030 #define LACDRC_ACD_SHIFT 0
1031
1032 /*
1033 * LCD Pixel Clock Divider Register
1034 */
1035 #define LPXCD_ADDR 0xfffffa25
1036 #define LPXCD BYTE_REF(LPXCD_ADDR)
1037
1038 #define LPXCD_PCD_MASK 0x3f /* Pixel Cloc
1039 #define LPXCD_PCD_SHIFT 0
1040
1041 /*
1042 * LCD Clocking Control Register
1043 */
1044 #define LCKCON_ADDR 0xfffffa27
1045 #define LCKCON BYTE_REF(LCKCON_ADDR)
1046
1047 #define LCKCON_DWS_MASK 0x0f /* Display Wa
1048 #define LCKCON_DWS_SHIFT 0
1049 #define LCKCON_DWIDTH 0x40 /* Display Me
1050 #define LCKCON_LCDON 0x80 /* Enable LCD
1051
1052 /* '328-compatible definitions */
1053 #define LCKCON_DW_MASK LCKCON_DWS_MASK
1054 #define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
1055
1056 /*
1057 * LCD Refresh Rate Adjustment Register
1058 */
1059 #define LRRA_ADDR 0xfffffa29
1060 #define LRRA BYTE_REF(LRRA_ADDR)
1061
1062 /*
1063 * LCD Panning Offset Register
1064 */
1065 #define LPOSR_ADDR 0xfffffa2d
1066 #define LPOSR BYTE_REF(LPOSR_ADDR)
1067
1068 #define LPOSR_POS_MASK 0x0f /* Pixel Offs
1069 #define LPOSR_POS_SHIFT 0
1070
1071 /*
1072 * LCD Frame Rate Control Modulation Register
1073 */
1074 #define LFRCM_ADDR 0xfffffa31
1075 #define LFRCM BYTE_REF(LFRCM_ADDR)
1076
1077 #define LFRCM_YMOD_MASK 0x0f /* Vertical M
1078 #define LFRCM_YMOD_SHIFT 0
1079 #define LFRCM_XMOD_MASK 0xf0 /* Horizontal
1080 #define LFRCM_XMOD_SHIFT 4
1081
1082 /*
1083 * LCD Gray Palette Mapping Register
1084 */
1085 #define LGPMR_ADDR 0xfffffa33
1086 #define LGPMR BYTE_REF(LGPMR_ADDR)
1087
1088 #define LGPMR_G1_MASK 0x0f
1089 #define LGPMR_G1_SHIFT 0
1090 #define LGPMR_G2_MASK 0xf0
1091 #define LGPMR_G2_SHIFT 4
1092
1093 /*
1094 * PWM Contrast Control Register
1095 */
1096 #define PWMR_ADDR 0xfffffa36
1097 #define PWMR WORD_REF(PWMR_ADDR)
1098
1099 #define PWMR_PW_MASK 0x00ff /* Pulse Widt
1100 #define PWMR_PW_SHIFT 0
1101 #define PWMR_CCPEN 0x0100 /* Contrast C
1102 #define PWMR_SRC_MASK 0x0600 /* Input Cloc
1103 #define PWMR_SRC_LINE 0x0000 /* Li
1104 #define PWMR_SRC_PIXEL 0x0200 /* Pi
1105 #define PWMR_SRC_LCD 0x4000 /* LC
1106
1107 /**********
1108 *
1109 * 0xFFFFFBxx -- Real-Time Clock (RTC)
1110 *
1111 **********/
1112
1113 /*
1114 * RTC Hours Minutes and Seconds Register
1115 */
1116 #define RTCTIME_ADDR 0xfffffb00
1117 #define RTCTIME LONG_REF(RTCTIME_ADDR
1118
1119 #define RTCTIME_SECONDS_MASK 0x0000003f
1120 #define RTCTIME_SECONDS_SHIFT 0
1121 #define RTCTIME_MINUTES_MASK 0x003f0000
1122 #define RTCTIME_MINUTES_SHIFT 16
1123 #define RTCTIME_HOURS_MASK 0x1f000000
1124 #define RTCTIME_HOURS_SHIFT 24
1125
1126 /*
1127 * RTC Alarm Register
1128 */
1129 #define RTCALRM_ADDR 0xfffffb04
1130 #define RTCALRM LONG_REF(RTCALRM_ADDR
1131
1132 #define RTCALRM_SECONDS_MASK 0x0000003f
1133 #define RTCALRM_SECONDS_SHIFT 0
1134 #define RTCALRM_MINUTES_MASK 0x003f0000
1135 #define RTCALRM_MINUTES_SHIFT 16
1136 #define RTCALRM_HOURS_MASK 0x1f000000
1137 #define RTCALRM_HOURS_SHIFT 24
1138
1139 /*
1140 * Watchdog Timer Register
1141 */
1142 #define WATCHDOG_ADDR 0xfffffb0a
1143 #define WATCHDOG WORD_REF(WATCHDOG_ADD
1144
1145 #define WATCHDOG_EN 0x0001 /* Watchdog E
1146 #define WATCHDOG_ISEL 0x0002 /* Select the
1147 #define WATCHDOG_INTF 0x0080 /* Watchdog i
1148 #define WATCHDOG_CNT_MASK 0x0300 /* Wa
1149 #define WATCHDOG_CNT_SHIFT 8
1150
1151 /*
1152 * RTC Control Register
1153 */
1154 #define RTCCTL_ADDR 0xfffffb0c
1155 #define RTCCTL WORD_REF(RTCCTL_ADDR)
1156
1157 #define RTCCTL_XTL 0x0020 /* Crystal Se
1158 #define RTCCTL_EN 0x0080 /* RTC Enable
1159
1160 /* '328-compatible definitions */
1161 #define RTCCTL_384 RTCCTL_XTL
1162 #define RTCCTL_ENABLE RTCCTL_EN
1163
1164 /*
1165 * RTC Interrupt Status Register
1166 */
1167 #define RTCISR_ADDR 0xfffffb0e
1168 #define RTCISR WORD_REF(RTCISR_ADDR)
1169
1170 #define RTCISR_SW 0x0001 /* Stopwatch
1171 #define RTCISR_MIN 0x0002 /* 1-minute i
1172 #define RTCISR_ALM 0x0004 /* Alarm inte
1173 #define RTCISR_DAY 0x0008 /* 24-hour ro
1174 #define RTCISR_1HZ 0x0010 /* 1Hz interr
1175 #define RTCISR_HR 0x0020 /* 1-hour int
1176 #define RTCISR_SAM0 0x0100 /* 4Hz /
1177 #define RTCISR_SAM1 0x0200 /* 8Hz /
1178 #define RTCISR_SAM2 0x0400 /* 16Hz / 1
1179 #define RTCISR_SAM3 0x0800 /* 32Hz / 3
1180 #define RTCISR_SAM4 0x1000 /* 64Hz / 7
1181 #define RTCISR_SAM5 0x2000 /* 128Hz / 15
1182 #define RTCISR_SAM6 0x4000 /* 256Hz / 30
1183 #define RTCISR_SAM7 0x8000 /* 512Hz / 60
1184
1185 /*
1186 * RTC Interrupt Enable Register
1187 */
1188 #define RTCIENR_ADDR 0xfffffb10
1189 #define RTCIENR WORD_REF(RTCIENR_ADDR
1190
1191 #define RTCIENR_SW 0x0001 /* Stopwatch
1192 #define RTCIENR_MIN 0x0002 /* 1-minute i
1193 #define RTCIENR_ALM 0x0004 /* Alarm inte
1194 #define RTCIENR_DAY 0x0008 /* 24-hour ro
1195 #define RTCIENR_1HZ 0x0010 /* 1Hz interr
1196 #define RTCIENR_HR 0x0020 /* 1-hour int
1197 #define RTCIENR_SAM0 0x0100 /* 4Hz /
1198 #define RTCIENR_SAM1 0x0200 /* 8Hz /
1199 #define RTCIENR_SAM2 0x0400 /* 16Hz / 1
1200 #define RTCIENR_SAM3 0x0800 /* 32Hz / 3
1201 #define RTCIENR_SAM4 0x1000 /* 64Hz / 7
1202 #define RTCIENR_SAM5 0x2000 /* 128Hz / 15
1203 #define RTCIENR_SAM6 0x4000 /* 256Hz / 30
1204 #define RTCIENR_SAM7 0x8000 /* 512Hz / 60
1205
1206 /*
1207 * Stopwatch Minutes Register
1208 */
1209 #define STPWCH_ADDR 0xfffffb12
1210 #define STPWCH WORD_REF(STPWCH_ADDR)
1211
1212 #define STPWCH_CNT_MASK 0x003f /* Stopwatch
1213 #define SPTWCH_CNT_SHIFT 0
1214
1215 /*
1216 * RTC Day Count Register
1217 */
1218 #define DAYR_ADDR 0xfffffb1a
1219 #define DAYR WORD_REF(DAYR_ADDR)
1220
1221 #define DAYR_DAYS_MASK 0x1ff /* Day Settin
1222 #define DAYR_DAYS_SHIFT 0
1223
1224 /*
1225 * RTC Day Alarm Register
1226 */
1227 #define DAYALARM_ADDR 0xfffffb1c
1228 #define DAYALARM WORD_REF(DAYALARM_ADD
1229
1230 #define DAYALARM_DAYSAL_MASK 0x01ff /* Da
1231 #define DAYALARM_DAYSAL_SHIFT 0
1232
1233 /**********
1234 *
1235 * 0xFFFFFCxx -- DRAM Controller
1236 *
1237 **********/
1238
1239 /*
1240 * DRAM Memory Configuration Register
1241 */
1242 #define DRAMMC_ADDR 0xfffffc00
1243 #define DRAMMC WORD_REF(DRAMMC_ADDR)
1244
1245 #define DRAMMC_ROW12_MASK 0xc000 /* Ro
1246 #define DRAMMC_ROW12_PA10 0x0000
1247 #define DRAMMC_ROW12_PA21 0x4000
1248 #define DRAMMC_ROW12_PA23 0x8000
1249 #define DRAMMC_ROW0_MASK 0x3000 /* Ro
1250 #define DRAMMC_ROW0_PA11 0x0000
1251 #define DRAMMC_ROW0_PA22 0x1000
1252 #define DRAMMC_ROW0_PA23 0x2000
1253 #define DRAMMC_ROW11 0x0800 /* Ro
1254 #define DRAMMC_ROW10 0x0400 /* Ro
1255 #define DRAMMC_ROW9 0x0200 /* Ro
1256 #define DRAMMC_ROW8 0x0100 /* Ro
1257 #define DRAMMC_COL10 0x0080 /* Co
1258 #define DRAMMC_COL9 0x0040 /* Co
1259 #define DRAMMC_COL8 0x0020 /* Co
1260 #define DRAMMC_REF_MASK 0x001f /* Re
1261 #define DRAMMC_REF_SHIFT 0
1262
1263 /*
1264 * DRAM Control Register
1265 */
1266 #define DRAMC_ADDR 0xfffffc02
1267 #define DRAMC WORD_REF(DRAMC_ADDR)
1268
1269 #define DRAMC_DWE 0x0001 /* DR
1270 #define DRAMC_RST 0x0002 /* Re
1271 #define DRAMC_LPR 0x0004 /* Lo
1272 #define DRAMC_SLW 0x0008 /* Sl
1273 #define DRAMC_LSP 0x0010 /* Li
1274 #define DRAMC_MSW 0x0020 /* Sl
1275 #define DRAMC_WS_MASK 0x00c0 /* Wa
1276 #define DRAMC_WS_SHIFT 6
1277 #define DRAMC_PGSZ_MASK 0x0300 /* Pa
1278 #define DRAMC_PGSZ_SHIFT 8
1279 #define DRAMC_PGSZ_256K 0x0000
1280 #define DRAMC_PGSZ_512K 0x0100
1281 #define DRAMC_PGSZ_1024K 0x0200
1282 #define DRAMC_PGSZ_2048K 0x0300
1283 #define DRAMC_EDO 0x0400 /* ED
1284 #define DRAMC_CLK 0x0800 /* Re
1285 #define DRAMC_BC_MASK 0x3000 /* Pa
1286 #define DRAMC_BC_SHIFT 12
1287 #define DRAMC_RM 0x4000 /* Re
1288 #define DRAMC_EN 0x8000 /* DR
1289
1290
1291 /**********
1292 *
1293 * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
1294 *
1295 **********/
1296
1297 /*
1298 * ICE Module Address Compare Register
1299 */
1300 #define ICEMACR_ADDR 0xfffffd00
1301 #define ICEMACR LONG_REF(ICEMACR_ADDR
1302
1303 /*
1304 * ICE Module Address Mask Register
1305 */
1306 #define ICEMAMR_ADDR 0xfffffd04
1307 #define ICEMAMR LONG_REF(ICEMAMR_ADDR
1308
1309 /*
1310 * ICE Module Control Compare Register
1311 */
1312 #define ICEMCCR_ADDR 0xfffffd08
1313 #define ICEMCCR WORD_REF(ICEMCCR_ADDR
1314
1315 #define ICEMCCR_PD 0x0001 /* Program/Da
1316 #define ICEMCCR_RW 0x0002 /* Read/Write
1317
1318 /*
1319 * ICE Module Control Mask Register
1320 */
1321 #define ICEMCMR_ADDR 0xfffffd0a
1322 #define ICEMCMR WORD_REF(ICEMCMR_ADDR
1323
1324 #define ICEMCMR_PDM 0x0001 /* Program/Da
1325 #define ICEMCMR_RWM 0x0002 /* Read/Write
1326
1327 /*
1328 * ICE Module Control Register
1329 */
1330 #define ICEMCR_ADDR 0xfffffd0c
1331 #define ICEMCR WORD_REF(ICEMCR_ADDR)
1332
1333 #define ICEMCR_CEN 0x0001 /* Compare En
1334 #define ICEMCR_PBEN 0x0002 /* Program Br
1335 #define ICEMCR_SB 0x0004 /* Single Bre
1336 #define ICEMCR_HMDIS 0x0008 /* HardMap di
1337 #define ICEMCR_BBIEN 0x0010 /* Bus Break
1338
1339 /*
1340 * ICE Module Status Register
1341 */
1342 #define ICEMSR_ADDR 0xfffffd0e
1343 #define ICEMSR WORD_REF(ICEMSR_ADDR)
1344
1345 #define ICEMSR_EMUEN 0x0001 /* Emulation
1346 #define ICEMSR_BRKIRQ 0x0002 /* A-Line Vec
1347 #define ICEMSR_BBIRQ 0x0004 /* Bus Break
1348 #define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Fal
1349
1350 #endif /* _MC68VZ328_H_ */
1351
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