1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /********************************************* 3 4 /* 5 * m5206sim.h -- ColdFire 5206 System Int 6 * 7 * (C) Copyright 1999, Greg Ungerer (gerg 8 * (C) Copyright 2000, Lineo Inc. (www.li 9 */ 10 11 /********************************************* 12 #ifndef m5206sim_h 13 #define m5206sim_h 14 /********************************************* 15 16 #define CPU_NAME "COLDFIRE(m520 17 #define CPU_INSTR_PER_JIFFY 3 18 #define MCF_BUSCLK MCF_CLK 19 20 #include <asm/m52xxacr.h> 21 22 /* 23 * Define the 5206 SIM register set addre 24 */ 25 #define MCFSIM_SIMR (MCF_MBAR + 0x 26 #define MCFSIM_ICR1 (MCF_MBAR + 0x 27 #define MCFSIM_ICR2 (MCF_MBAR + 0x 28 #define MCFSIM_ICR3 (MCF_MBAR + 0x 29 #define MCFSIM_ICR4 (MCF_MBAR + 0x 30 #define MCFSIM_ICR5 (MCF_MBAR + 0x 31 #define MCFSIM_ICR6 (MCF_MBAR + 0x 32 #define MCFSIM_ICR7 (MCF_MBAR + 0x 33 #define MCFSIM_ICR8 (MCF_MBAR + 0x 34 #define MCFSIM_ICR9 (MCF_MBAR + 0x 35 #define MCFSIM_ICR10 (MCF_MBAR + 0x 36 #define MCFSIM_ICR11 (MCF_MBAR + 0x 37 #define MCFSIM_ICR12 (MCF_MBAR + 0x 38 #define MCFSIM_ICR13 (MCF_MBAR + 0x 39 #ifdef CONFIG_M5206e 40 #define MCFSIM_ICR14 (MCF_MBAR + 0x 41 #define MCFSIM_ICR15 (MCF_MBAR + 0x 42 #endif 43 44 #define MCFSIM_IMR (MCF_MBAR + 0x 45 #define MCFSIM_IPR (MCF_MBAR + 0x 46 47 #define MCFSIM_RSR (MCF_MBAR + 0x 48 #define MCFSIM_SYPCR (MCF_MBAR + 0x 49 50 #define MCFSIM_SWIVR (MCF_MBAR + 0x 51 #define MCFSIM_SWSR (MCF_MBAR + 0x 52 53 #define MCFSIM_DCRR (MCF_MBAR + 0x 54 #define MCFSIM_DCTR (MCF_MBAR + 0x 55 #define MCFSIM_DAR0 (MCF_MBAR + 0x 56 #define MCFSIM_DMR0 (MCF_MBAR + 0x 57 #define MCFSIM_DCR0 (MCF_MBAR + 0x 58 #define MCFSIM_DAR1 (MCF_MBAR + 0x 59 #define MCFSIM_DMR1 (MCF_MBAR + 0x 60 #define MCFSIM_DCR1 (MCF_MBAR + 0x 61 62 #define MCFSIM_CSAR0 (MCF_MBAR + 0x 63 #define MCFSIM_CSMR0 (MCF_MBAR + 0x 64 #define MCFSIM_CSCR0 (MCF_MBAR + 0x 65 #define MCFSIM_CSAR1 (MCF_MBAR + 0x 66 #define MCFSIM_CSMR1 (MCF_MBAR + 0x 67 #define MCFSIM_CSCR1 (MCF_MBAR + 0x 68 #define MCFSIM_CSAR2 (MCF_MBAR + 0x 69 #define MCFSIM_CSMR2 (MCF_MBAR + 0x 70 #define MCFSIM_CSCR2 (MCF_MBAR + 0x 71 #define MCFSIM_CSAR3 (MCF_MBAR + 0x 72 #define MCFSIM_CSMR3 (MCF_MBAR + 0x 73 #define MCFSIM_CSCR3 (MCF_MBAR + 0x 74 #define MCFSIM_CSAR4 (MCF_MBAR + 0x 75 #define MCFSIM_CSMR4 (MCF_MBAR + 0x 76 #define MCFSIM_CSCR4 (MCF_MBAR + 0x 77 #define MCFSIM_CSAR5 (MCF_MBAR + 0x 78 #define MCFSIM_CSMR5 (MCF_MBAR + 0x 79 #define MCFSIM_CSCR5 (MCF_MBAR + 0x 80 #define MCFSIM_CSAR6 (MCF_MBAR + 0x 81 #define MCFSIM_CSMR6 (MCF_MBAR + 0x 82 #define MCFSIM_CSCR6 (MCF_MBAR + 0x 83 #define MCFSIM_CSAR7 (MCF_MBAR + 0x 84 #define MCFSIM_CSMR7 (MCF_MBAR + 0x 85 #define MCFSIM_CSCR7 (MCF_MBAR + 0x 86 #define MCFSIM_DMCR (MCF_MBAR + 0x 87 88 #ifdef CONFIG_M5206e 89 #define MCFSIM_PAR (MCF_MBAR + 0x 90 #else 91 #define MCFSIM_PAR (MCF_MBAR + 0x 92 #endif 93 94 #define MCFTIMER_BASE1 (MCF_MBAR + 0x 95 #define MCFTIMER_BASE2 (MCF_MBAR + 0x 96 97 #define MCFSIM_PADDR (MCF_MBAR + 0x 98 #define MCFSIM_PADAT (MCF_MBAR + 0x 99 100 #define MCFDMA_BASE0 (MCF_MBAR + 0x 101 #define MCFDMA_BASE1 (MCF_MBAR + 0x 102 103 #if defined(CONFIG_NETtel) 104 #define MCFUART_BASE0 (MCF_MBAR + 0x 105 #define MCFUART_BASE1 (MCF_MBAR + 0x 106 #else 107 #define MCFUART_BASE0 (MCF_MBAR + 0x 108 #define MCFUART_BASE1 (MCF_MBAR + 0x 109 #endif 110 111 /* 112 * Define system peripheral IRQ usage. 113 */ 114 #define MCF_IRQ_I2C0 29 115 #define MCF_IRQ_TIMER 30 116 #define MCF_IRQ_PROFILER 31 117 #define MCF_IRQ_UART0 73 118 #define MCF_IRQ_UART1 74 119 120 /* 121 * Generic GPIO 122 */ 123 #define MCFGPIO_PIN_MAX 8 124 #define MCFGPIO_IRQ_VECBASE -1 125 #define MCFGPIO_IRQ_MAX -1 126 127 /* 128 * Some symbol defines for the Parallel P 129 */ 130 #ifdef CONFIG_M5206e 131 #define MCFSIM_PAR_DREQ0 0x100 132 133 #define MCFSIM_PAR_DREQ1 0x200 134 135 #endif 136 137 /* 138 * Some symbol defines for the Interrupt 139 */ 140 #define MCFSIM_SWDICR MCFSIM_ICR8 141 #define MCFSIM_TIMER1ICR MCFSIM_ICR9 142 #define MCFSIM_TIMER2ICR MCFSIM_ICR10 143 #define MCFSIM_I2CICR MCFSIM_ICR11 144 #define MCFSIM_UART1ICR MCFSIM_ICR12 145 #define MCFSIM_UART2ICR MCFSIM_ICR13 146 #ifdef CONFIG_M5206e 147 #define MCFSIM_DMA1ICR MCFSIM_ICR14 148 #define MCFSIM_DMA2ICR MCFSIM_ICR15 149 #endif 150 151 /* 152 * I2C Controller 153 */ 154 #define MCFI2C_BASE0 (MCF_MBAR + 0x 155 #define MCFI2C_SIZE0 0x40 156 157 /********************************************* 158 #endif /* m5206sim_h */ 159
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