1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /********************************************* 3 4 /* 5 * m527xsim.h -- ColdFire 5270/5271 Syste 6 * 7 * (C) Copyright 2004, Greg Ungerer (gerg 8 */ 9 10 /********************************************* 11 #ifndef m527xsim_h 12 #define m527xsim_h 13 /********************************************* 14 15 #define CPU_NAME "COLDFIRE(m527 16 #define CPU_INSTR_PER_JIFFY 3 17 #define MCF_BUSCLK (MCF_CLK / 2) 18 19 #include <asm/m52xxacr.h> 20 21 /* 22 * Define the 5270/5271 SIM register set 23 */ 24 #define MCFICM_INTC0 (MCF_IPSBAR + 25 #define MCFICM_INTC1 (MCF_IPSBAR + 26 27 #define MCFINTC_IPRH 0x00 28 #define MCFINTC_IPRL 0x04 29 #define MCFINTC_IMRH 0x08 30 #define MCFINTC_IMRL 0x0c 31 #define MCFINTC_INTFRCH 0x10 32 #define MCFINTC_INTFRCL 0x14 33 #define MCFINTC_IRLR 0x18 34 #define MCFINTC_IACKL 0x19 35 #define MCFINTC_ICR0 0x40 36 37 #define MCFINT_VECBASE 64 38 #define MCFINT_UART0 13 39 #define MCFINT_UART1 14 40 #define MCFINT_UART2 15 41 #define MCFINT_I2C0 17 42 #define MCFINT_QSPI 18 43 #define MCFINT_FECRX0 23 44 #define MCFINT_FECTX0 27 45 #define MCFINT_FECENTC0 29 46 #define MCFINT_PIT1 36 47 48 #define MCFINT2_VECBASE 128 49 #define MCFINT2_FECRX1 23 50 #define MCFINT2_FECTX1 27 51 #define MCFINT2_FECENTC1 29 52 53 #define MCF_IRQ_UART0 (MCFINT_VECBAS 54 #define MCF_IRQ_UART1 (MCFINT_VECBAS 55 #define MCF_IRQ_UART2 (MCFINT_VECBAS 56 57 #define MCF_IRQ_FECRX0 (MCFINT_VECBAS 58 #define MCF_IRQ_FECTX0 (MCFINT_VECBAS 59 #define MCF_IRQ_FECENTC0 (MCFINT_VECBAS 60 #define MCF_IRQ_FECRX1 (MCFINT2_VECBA 61 #define MCF_IRQ_FECTX1 (MCFINT2_VECBA 62 #define MCF_IRQ_FECENTC1 (MCFINT2_VECBA 63 64 #define MCF_IRQ_QSPI (MCFINT_VECBAS 65 #define MCF_IRQ_PIT1 (MCFINT_VECBAS 66 #define MCF_IRQ_I2C0 (MCFINT_VECBAS 67 68 /* 69 * SDRAM configuration registers. 70 */ 71 #ifdef CONFIG_M5271 72 #define MCFSIM_DCR (MCF_IPSBAR + 73 #define MCFSIM_DACR0 (MCF_IPSBAR + 74 #define MCFSIM_DMR0 (MCF_IPSBAR + 75 #define MCFSIM_DACR1 (MCF_IPSBAR + 76 #define MCFSIM_DMR1 (MCF_IPSBAR + 77 #endif 78 #ifdef CONFIG_M5275 79 #define MCFSIM_DMR (MCF_IPSBAR + 80 #define MCFSIM_DCR (MCF_IPSBAR + 81 #define MCFSIM_DCFG1 (MCF_IPSBAR + 82 #define MCFSIM_DCFG2 (MCF_IPSBAR + 83 #define MCFSIM_DBAR0 (MCF_IPSBAR + 84 #define MCFSIM_DMR0 (MCF_IPSBAR + 85 #define MCFSIM_DBAR1 (MCF_IPSBAR + 86 #define MCFSIM_DMR1 (MCF_IPSBAR + 87 #endif 88 89 /* 90 * DMA unit base addresses. 91 */ 92 #define MCFDMA_BASE0 (MCF_IPSBAR + 93 #define MCFDMA_BASE1 (MCF_IPSBAR + 94 #define MCFDMA_BASE2 (MCF_IPSBAR + 95 #define MCFDMA_BASE3 (MCF_IPSBAR + 96 97 /* 98 * UART module. 99 */ 100 #define MCFUART_BASE0 (MCF_IPSBAR + 101 #define MCFUART_BASE1 (MCF_IPSBAR + 102 #define MCFUART_BASE2 (MCF_IPSBAR + 103 104 /* 105 * FEC ethernet module. 106 */ 107 #define MCFFEC_BASE0 (MCF_IPSBAR + 108 #define MCFFEC_SIZE0 0x800 109 #ifdef CONFIG_M5275 110 #define MCFFEC_BASE1 (MCF_IPSBAR + 111 #define MCFFEC_SIZE1 0x800 112 #endif 113 114 /* 115 * QSPI module. 116 */ 117 #define MCFQSPI_BASE (MCF_IPSBAR + 118 #define MCFQSPI_SIZE 0x40 119 120 #ifdef CONFIG_M5271 121 #define MCFQSPI_CS0 91 122 #define MCFQSPI_CS1 92 123 #define MCFQSPI_CS2 99 124 #define MCFQSPI_CS3 103 125 #endif 126 #ifdef CONFIG_M5275 127 #define MCFQSPI_CS0 59 128 #define MCFQSPI_CS1 60 129 #define MCFQSPI_CS2 61 130 #define MCFQSPI_CS3 62 131 #endif 132 133 /* 134 * GPIO module. 135 */ 136 #ifdef CONFIG_M5271 137 #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 138 #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 139 #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 140 #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 141 #define MCFGPIO_PODR_BS (MCF_IPSBAR + 142 #define MCFGPIO_PODR_CS (MCF_IPSBAR + 143 #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 144 #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 145 #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 146 #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 147 #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 148 #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 149 150 #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 151 #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 152 #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 153 #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 154 #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 155 #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 156 #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 157 #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 158 #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 159 #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 160 #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 161 #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 162 163 #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 164 #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 165 #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 166 #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 167 #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 168 #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 169 #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 170 #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 171 #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 172 #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 173 #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 174 #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 175 176 #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 177 #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 178 #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 179 #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 180 #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 181 #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 182 #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 183 #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 184 #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 185 #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 186 #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 187 #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 188 189 /* 190 * Generic GPIO support 191 */ 192 #define MCFGPIO_PODR MCFGPIO_PODR_A 193 #define MCFGPIO_PDDR MCFGPIO_PDDR_A 194 #define MCFGPIO_PPDR MCFGPIO_PPDSDR 195 #define MCFGPIO_SETR MCFGPIO_PPDSDR 196 #define MCFGPIO_CLRR MCFGPIO_PCLRR_ 197 198 #define MCFGPIO_PIN_MAX 100 199 #define MCFGPIO_IRQ_MAX 8 200 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 201 202 /* 203 * Port Pin Assignment registers. 204 */ 205 #define MCFGPIO_PAR_AD (MCF_IPSBAR + 206 #define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 207 #define MCFGPIO_PAR_BS (MCF_IPSBAR + 208 #define MCFGPIO_PAR_CS (MCF_IPSBAR + 209 #define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 210 #define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 211 #define MCFGPIO_PAR_UART (MCF_IPSBAR + 212 #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 213 #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 214 215 #define UART0_ENABLE_MASK 0x000f 216 #define UART1_ENABLE_MASK 0x0ff0 217 #define UART2_ENABLE_MASK 0x3000 218 #endif /* CONFIG_M5271 */ 219 220 #ifdef CONFIG_M5275 221 #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 222 #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 223 #define MCFGPIO_PODR_CS (MCF_IPSBAR + 224 #define MCFGPIO_PODR_FEC0H (MCF_IPSBAR + 225 #define MCFGPIO_PODR_FEC0L (MCF_IPSBAR + 226 #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 227 #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 228 #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 229 #define MCFGPIO_PODR_TIMERH (MCF_IPSBAR + 230 #define MCFGPIO_PODR_TIMERL (MCF_IPSBAR + 231 #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 232 #define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 233 #define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 234 #define MCFGPIO_PODR_BS (MCF_IPSBAR + 235 #define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 236 #define MCFGPIO_PODR_USBH (MCF_IPSBAR + 237 #define MCFGPIO_PODR_USBL (MCF_IPSBAR + 238 #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 239 240 #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 241 #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 242 #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 243 #define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 244 #define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 245 #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 246 #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 247 #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 248 #define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 249 #define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 250 #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 251 #define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 252 #define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 253 #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 254 #define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 255 #define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 256 #define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 257 #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 258 259 #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 260 #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 261 #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 262 #define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 263 #define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 264 #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 265 #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 266 #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 267 #define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 268 #define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 269 #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 270 #define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 271 #define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 272 #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 273 #define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 274 #define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 275 #define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 276 #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 277 278 #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 279 #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 280 #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 281 #define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 282 #define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 283 #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 284 #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 285 #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 286 #define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 287 #define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 288 #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 289 #define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 290 #define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 291 #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 292 #define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 293 #define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 294 #define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 295 #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 296 297 298 /* 299 * Generic GPIO support 300 */ 301 #define MCFGPIO_PODR MCFGPIO_PODR_B 302 #define MCFGPIO_PDDR MCFGPIO_PDDR_B 303 #define MCFGPIO_PPDR MCFGPIO_PPDSDR 304 #define MCFGPIO_SETR MCFGPIO_PPDSDR 305 #define MCFGPIO_CLRR MCFGPIO_PCLRR_ 306 307 #define MCFGPIO_PIN_MAX 148 308 #define MCFGPIO_IRQ_MAX 8 309 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 310 311 /* 312 * Port Pin Assignment registers. 313 */ 314 #define MCFGPIO_PAR_AD (MCF_IPSBAR + 315 #define MCFGPIO_PAR_CS (MCF_IPSBAR + 316 #define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 317 #define MCFGPIO_PAR_USB (MCF_IPSBAR + 318 #define MCFGPIO_PAR_FEC0HL (MCF_IPSBAR + 319 #define MCFGPIO_PAR_FEC1HL (MCF_IPSBAR + 320 #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 321 #define MCFGPIO_PAR_UART (MCF_IPSBAR + 322 #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 323 #define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 324 #define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 325 #define MCFGPIO_PAR_BS (MCF_IPSBAR + 326 327 #define UART0_ENABLE_MASK 0x000f 328 #define UART1_ENABLE_MASK 0x00f0 329 #define UART2_ENABLE_MASK 0x3f00 330 #endif /* CONFIG_M5275 */ 331 332 /* 333 * PIT timer base addresses. 334 */ 335 #define MCFPIT_BASE1 (MCF_IPSBAR + 336 #define MCFPIT_BASE2 (MCF_IPSBAR + 337 #define MCFPIT_BASE3 (MCF_IPSBAR + 338 #define MCFPIT_BASE4 (MCF_IPSBAR + 339 340 /* 341 * EPort 342 */ 343 #define MCFEPORT_EPPAR (MCF_IPSBAR + 344 #define MCFEPORT_EPDDR (MCF_IPSBAR + 345 #define MCFEPORT_EPIER (MCF_IPSBAR + 346 #define MCFEPORT_EPDR (MCF_IPSBAR + 347 #define MCFEPORT_EPPDR (MCF_IPSBAR + 348 #define MCFEPORT_EPFR (MCF_IPSBAR + 349 350 /* 351 * Reset Control Unit (relative to IPSBAR). 352 */ 353 #define MCF_RCR (MCF_IPSBAR + 354 #define MCF_RSR (MCF_IPSBAR + 355 356 #define MCF_RCR_SWRESET 0x80 357 #define MCF_RCR_FRCSTOUT 0x40 358 359 /* 360 * I2C module. 361 */ 362 #define MCFI2C_BASE0 (MCF_IPSBAR + 363 #define MCFI2C_SIZE0 0x40 364 365 /********************************************* 366 #endif /* m527xsim_h */ 367
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