1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /********************************************* 3 4 /* 5 * m528xsim.h -- ColdFire 5280/5282 Syste 6 * 7 * (C) Copyright 2003, Greg Ungerer (gerg 8 */ 9 10 /********************************************* 11 #ifndef m528xsim_h 12 #define m528xsim_h 13 /********************************************* 14 15 #define CPU_NAME "COLDFIRE(m528 16 #define CPU_INSTR_PER_JIFFY 3 17 #define MCF_BUSCLK MCF_CLK 18 19 #include <asm/m52xxacr.h> 20 21 /* 22 * Define the 5280/5282 SIM register set 23 */ 24 #define MCFICM_INTC0 (MCF_IPSBAR + 25 #define MCFICM_INTC1 (MCF_IPSBAR + 26 27 #define MCFINTC_IPRH 0x00 28 #define MCFINTC_IPRL 0x04 29 #define MCFINTC_IMRH 0x08 30 #define MCFINTC_IMRL 0x0c 31 #define MCFINTC_INTFRCH 0x10 32 #define MCFINTC_INTFRCL 0x14 33 #define MCFINTC_IRLR 0x18 34 #define MCFINTC_IACKL 0x19 35 #define MCFINTC_ICR0 0x40 36 37 #define MCFINT_VECBASE 64 38 #define MCFINT_UART0 13 39 #define MCFINT_UART1 14 40 #define MCFINT_UART2 15 41 #define MCFINT_I2C0 17 42 #define MCFINT_QSPI 18 43 #define MCFINT_FECRX0 23 44 #define MCFINT_FECTX0 27 45 #define MCFINT_FECENTC0 29 46 #define MCFINT_PIT1 55 47 48 #define MCF_IRQ_UART0 (MCFINT_VECBAS 49 #define MCF_IRQ_UART1 (MCFINT_VECBAS 50 #define MCF_IRQ_UART2 (MCFINT_VECBAS 51 52 #define MCF_IRQ_FECRX0 (MCFINT_VECBAS 53 #define MCF_IRQ_FECTX0 (MCFINT_VECBAS 54 #define MCF_IRQ_FECENTC0 (MCFINT_VECBAS 55 56 #define MCF_IRQ_QSPI (MCFINT_VECBAS 57 #define MCF_IRQ_PIT1 (MCFINT_VECBAS 58 #define MCF_IRQ_I2C0 (MCFINT_VECBAS 59 60 /* 61 * SDRAM configuration registers. 62 */ 63 #define MCFSIM_DCR (MCF_IPSBAR + 64 #define MCFSIM_DACR0 (MCF_IPSBAR + 65 #define MCFSIM_DMR0 (MCF_IPSBAR + 66 #define MCFSIM_DACR1 (MCF_IPSBAR + 67 #define MCFSIM_DMR1 (MCF_IPSBAR + 68 69 /* 70 * DMA unit base addresses. 71 */ 72 #define MCFDMA_BASE0 (MCF_IPSBAR + 73 #define MCFDMA_BASE1 (MCF_IPSBAR + 74 #define MCFDMA_BASE2 (MCF_IPSBAR + 75 #define MCFDMA_BASE3 (MCF_IPSBAR + 76 77 /* 78 * UART module. 79 */ 80 #define MCFUART_BASE0 (MCF_IPSBAR + 81 #define MCFUART_BASE1 (MCF_IPSBAR + 82 #define MCFUART_BASE2 (MCF_IPSBAR + 83 84 /* 85 * FEC ethernet module. 86 */ 87 #define MCFFEC_BASE0 (MCF_IPSBAR + 88 #define MCFFEC_SIZE0 0x800 89 90 /* 91 * QSPI module. 92 */ 93 #define MCFQSPI_BASE (MCF_IPSBAR + 94 #define MCFQSPI_SIZE 0x40 95 96 #define MCFQSPI_CS0 147 97 #define MCFQSPI_CS1 148 98 #define MCFQSPI_CS2 149 99 #define MCFQSPI_CS3 150 100 101 /* 102 * GPIO registers 103 */ 104 #define MCFGPIO_PODR_A (MCF_IPSBAR + 105 #define MCFGPIO_PODR_B (MCF_IPSBAR + 106 #define MCFGPIO_PODR_C (MCF_IPSBAR + 107 #define MCFGPIO_PODR_D (MCF_IPSBAR + 108 #define MCFGPIO_PODR_E (MCF_IPSBAR + 109 #define MCFGPIO_PODR_F (MCF_IPSBAR + 110 #define MCFGPIO_PODR_G (MCF_IPSBAR + 111 #define MCFGPIO_PODR_H (MCF_IPSBAR + 112 #define MCFGPIO_PODR_J (MCF_IPSBAR + 113 #define MCFGPIO_PODR_DD (MCF_IPSBAR + 114 #define MCFGPIO_PODR_EH (MCF_IPSBAR + 115 #define MCFGPIO_PODR_EL (MCF_IPSBAR + 116 #define MCFGPIO_PODR_AS (MCF_IPSBAR + 117 #define MCFGPIO_PODR_QS (MCF_IPSBAR + 118 #define MCFGPIO_PODR_SD (MCF_IPSBAR + 119 #define MCFGPIO_PODR_TC (MCF_IPSBAR + 120 #define MCFGPIO_PODR_TD (MCF_IPSBAR + 121 #define MCFGPIO_PODR_UA (MCF_IPSBAR + 122 123 #define MCFGPIO_PDDR_A (MCF_IPSBAR + 124 #define MCFGPIO_PDDR_B (MCF_IPSBAR + 125 #define MCFGPIO_PDDR_C (MCF_IPSBAR + 126 #define MCFGPIO_PDDR_D (MCF_IPSBAR + 127 #define MCFGPIO_PDDR_E (MCF_IPSBAR + 128 #define MCFGPIO_PDDR_F (MCF_IPSBAR + 129 #define MCFGPIO_PDDR_G (MCF_IPSBAR + 130 #define MCFGPIO_PDDR_H (MCF_IPSBAR + 131 #define MCFGPIO_PDDR_J (MCF_IPSBAR + 132 #define MCFGPIO_PDDR_DD (MCF_IPSBAR + 133 #define MCFGPIO_PDDR_EH (MCF_IPSBAR + 134 #define MCFGPIO_PDDR_EL (MCF_IPSBAR + 135 #define MCFGPIO_PDDR_AS (MCF_IPSBAR + 136 #define MCFGPIO_PDDR_QS (MCF_IPSBAR + 137 #define MCFGPIO_PDDR_SD (MCF_IPSBAR + 138 #define MCFGPIO_PDDR_TC (MCF_IPSBAR + 139 #define MCFGPIO_PDDR_TD (MCF_IPSBAR + 140 #define MCFGPIO_PDDR_UA (MCF_IPSBAR + 141 142 #define MCFGPIO_PPDSDR_A (MCF_IPSBAR + 143 #define MCFGPIO_PPDSDR_B (MCF_IPSBAR + 144 #define MCFGPIO_PPDSDR_C (MCF_IPSBAR + 145 #define MCFGPIO_PPDSDR_D (MCF_IPSBAR + 146 #define MCFGPIO_PPDSDR_E (MCF_IPSBAR + 147 #define MCFGPIO_PPDSDR_F (MCF_IPSBAR + 148 #define MCFGPIO_PPDSDR_G (MCF_IPSBAR + 149 #define MCFGPIO_PPDSDR_H (MCF_IPSBAR + 150 #define MCFGPIO_PPDSDR_J (MCF_IPSBAR + 151 #define MCFGPIO_PPDSDR_DD (MCF_IPSBAR + 152 #define MCFGPIO_PPDSDR_EH (MCF_IPSBAR + 153 #define MCFGPIO_PPDSDR_EL (MCF_IPSBAR + 154 #define MCFGPIO_PPDSDR_AS (MCF_IPSBAR + 155 #define MCFGPIO_PPDSDR_QS (MCF_IPSBAR + 156 #define MCFGPIO_PPDSDR_SD (MCF_IPSBAR + 157 #define MCFGPIO_PPDSDR_TC (MCF_IPSBAR + 158 #define MCFGPIO_PPDSDR_TD (MCF_IPSBAR + 159 #define MCFGPIO_PPDSDR_UA (MCF_IPSBAR + 160 161 #define MCFGPIO_PCLRR_A (MCF_IPSBAR + 162 #define MCFGPIO_PCLRR_B (MCF_IPSBAR + 163 #define MCFGPIO_PCLRR_C (MCF_IPSBAR + 164 #define MCFGPIO_PCLRR_D (MCF_IPSBAR + 165 #define MCFGPIO_PCLRR_E (MCF_IPSBAR + 166 #define MCFGPIO_PCLRR_F (MCF_IPSBAR + 167 #define MCFGPIO_PCLRR_G (MCF_IPSBAR + 168 #define MCFGPIO_PCLRR_H (MCF_IPSBAR + 169 #define MCFGPIO_PCLRR_J (MCF_IPSBAR + 170 #define MCFGPIO_PCLRR_DD (MCF_IPSBAR + 171 #define MCFGPIO_PCLRR_EH (MCF_IPSBAR + 172 #define MCFGPIO_PCLRR_EL (MCF_IPSBAR + 173 #define MCFGPIO_PCLRR_AS (MCF_IPSBAR + 174 #define MCFGPIO_PCLRR_QS (MCF_IPSBAR + 175 #define MCFGPIO_PCLRR_SD (MCF_IPSBAR + 176 #define MCFGPIO_PCLRR_TC (MCF_IPSBAR + 177 #define MCFGPIO_PCLRR_TD (MCF_IPSBAR + 178 #define MCFGPIO_PCLRR_UA (MCF_IPSBAR + 179 180 #define MCFGPIO_PBCDPAR (MCF_IPSBAR + 181 #define MCFGPIO_PFPAR (MCF_IPSBAR + 182 #define MCFGPIO_PEPAR (MCF_IPSBAR + 183 #define MCFGPIO_PJPAR (MCF_IPSBAR + 184 #define MCFGPIO_PSDPAR (MCF_IPSBAR + 185 #define MCFGPIO_PASPAR (MCF_IPSBAR + 186 #define MCFGPIO_PEHLPAR (MCF_IPSBAR + 187 #define MCFGPIO_PQSPAR (MCF_IPSBAR + 188 #define MCFGPIO_PTCPAR (MCF_IPSBAR + 189 #define MCFGPIO_PTDPAR (MCF_IPSBAR + 190 #define MCFGPIO_PUAPAR (MCF_IPSBAR + 191 192 /* 193 * PIT timer base addresses. 194 */ 195 #define MCFPIT_BASE1 (MCF_IPSBAR + 196 #define MCFPIT_BASE2 (MCF_IPSBAR + 197 #define MCFPIT_BASE3 (MCF_IPSBAR + 198 #define MCFPIT_BASE4 (MCF_IPSBAR + 199 200 /* 201 * Edge Port registers 202 */ 203 #define MCFEPORT_EPPAR (MCF_IPSBAR + 204 #define MCFEPORT_EPDDR (MCF_IPSBAR + 205 #define MCFEPORT_EPIER (MCF_IPSBAR + 206 #define MCFEPORT_EPDR (MCF_IPSBAR + 207 #define MCFEPORT_EPPDR (MCF_IPSBAR + 208 #define MCFEPORT_EPFR (MCF_IPSBAR + 209 210 /* 211 * Queued ADC registers 212 */ 213 #define MCFQADC_PORTQA (MCF_IPSBAR + 214 #define MCFQADC_PORTQB (MCF_IPSBAR + 215 #define MCFQADC_DDRQA (MCF_IPSBAR + 216 #define MCFQADC_DDRQB (MCF_IPSBAR + 217 218 /* 219 * General Purpose Timers registers 220 */ 221 #define MCFGPTA_GPTPORT (MCF_IPSBAR + 222 #define MCFGPTA_GPTDDR (MCF_IPSBAR + 223 #define MCFGPTB_GPTPORT (MCF_IPSBAR + 224 #define MCFGPTB_GPTDDR (MCF_IPSBAR + 225 /* 226 * 227 * definitions for generic gpio support 228 * 229 */ 230 #define MCFGPIO_PODR MCFGPIO_PODR_A 231 #define MCFGPIO_PDDR MCFGPIO_PDDR_A 232 #define MCFGPIO_PPDR MCFGPIO_PPDSDR 233 #define MCFGPIO_SETR MCFGPIO_PPDSDR 234 #define MCFGPIO_CLRR MCFGPIO_PCLRR_ 235 236 #define MCFGPIO_IRQ_MAX 8 237 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 238 #define MCFGPIO_PIN_MAX 180 239 240 /* 241 * Reset Control Unit (relative to IPSBAR). 242 */ 243 #define MCF_RCR (MCF_IPSBAR + 244 #define MCF_RSR (MCF_IPSBAR + 245 246 #define MCF_RCR_SWRESET 0x80 247 #define MCF_RCR_FRCSTOUT 0x40 248 249 /* 250 * I2C module 251 */ 252 #define MCFI2C_BASE0 (MCF_IPSBAR + 253 #define MCFI2C_SIZE0 0x40 254 255 /********************************************* 256 #endif /* m528xsim_h */ 257
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