1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /********************************************* 3 4 /* 5 * m52xxacr.h -- ColdFire version 2 core cache 6 * 7 * (C) Copyright 2010, Greg Ungerer <gerg@snap 8 */ 9 10 /********************************************* 11 #ifndef m52xxacr_h 12 #define m52xxacr_h 13 /********************************************* 14 15 /* 16 * All varients of the ColdFire using version 17 * cache setup. Although not absolutely identi 18 * definitions are compatible for all of them. 19 * configurable cache memory that can be instr 20 * or split instruction and data. The exceptio 21 * core based parts, like the 5206(e), 5249 an 22 * cache only. Cache size varies from 2k up to 23 */ 24 25 /* 26 * Define the Cache Control register flags. 27 */ 28 #define CACR_CENB 0x80000000 /* Ena 29 #define CACR_CDPI 0x10000000 /* Dis 30 #define CACR_CFRZ 0x08000000 /* Cac 31 #define CACR_CINV 0x01000000 /* Inv 32 #define CACR_DISI 0x00800000 /* Dis 33 #define CACR_DISD 0x00400000 /* Dis 34 #define CACR_INVI 0x00200000 /* Inv 35 #define CACR_INVD 0x00100000 /* Inv 36 #define CACR_CEIB 0x00000400 /* Non 37 #define CACR_DCM 0x00000200 /* Def 38 #define CACR_DBWE 0x00000100 /* Buf 39 #define CACR_DWP 0x00000020 /* Wri 40 #define CACR_EUSP 0x00000010 /* Ena 41 42 /* 43 * Define the Access Control register flags. 44 */ 45 #define ACR_BASE_POS 24 /* Add 46 #define ACR_MASK_POS 16 /* Add 47 #define ACR_ENABLE 0x00008000 /* Ena 48 #define ACR_USER 0x00000000 /* All 49 #define ACR_SUPER 0x00002000 /* All 50 #define ACR_ANY 0x00004000 /* All 51 #define ACR_CENB 0x00000000 /* Cac 52 #define ACR_CDIS 0x00000040 /* Cac 53 #define ACR_BWE 0x00000020 /* Wri 54 #define ACR_WPROTECT 0x00000004 /* Wri 55 56 /* 57 * Set the cache controller settings we will u 58 * a split cache configuration we allow all th 59 * time. For those cores that only have an ins 60 * that as on. 61 */ 62 #if defined(CONFIG_CACHE_I) 63 #define CACHE_TYPE (CACR_DISD + CACR_EUSP 64 #define CACHE_INVTYPEI 0 65 #elif defined(CONFIG_CACHE_D) 66 #define CACHE_TYPE (CACR_DISI + CACR_EUSP 67 #define CACHE_INVTYPED 0 68 #elif defined(CONFIG_CACHE_BOTH) 69 #define CACHE_TYPE CACR_EUSP 70 #define CACHE_INVTYPEI CACR_INVI 71 #define CACHE_INVTYPED CACR_INVD 72 #else 73 /* This is the instruction cache only devices 74 #define CACHE_TYPE 0 75 #define CACHE_INVTYPEI 0 76 #endif 77 78 #define CACHE_INIT (CACR_CINV + CACHE_TYP 79 #define CACHE_MODE (CACR_CENB + CACHE_TYP 80 81 #define CACHE_INVALIDATE (CACHE_MODE + CACR_C 82 #if defined(CACHE_INVTYPEI) 83 #define CACHE_INVALIDATEI (CACHE_MODE + CACR_C 84 #endif 85 #if defined(CACHE_INVTYPED) 86 #define CACHE_INVALIDATED (CACHE_MODE + CACR_C 87 #endif 88 89 #define ACR0_MODE ((CONFIG_RAMBASE & 0xf 90 (0x000f0000) + \ 91 (ACR_ENABLE + ACR_ANY 92 #define ACR1_MODE 0 93 94 /********************************************* 95 #endif /* m52xxsim_h */ 96
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