1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /********************************************* 3 4 /* 5 * m53xxacr.h -- ColdFire version 3 core cache 6 * 7 * (C) Copyright 2010, Greg Ungerer <gerg@snap 8 */ 9 10 /********************************************* 11 #ifndef m53xxacr_h 12 #define m53xxacr_h 13 /********************************************* 14 15 /* 16 * All varients of the ColdFire using version 17 * cache setup. They have a unified instructio 18 * configurable write-through or copy-back ope 19 */ 20 21 /* 22 * Define the Cache Control register flags. 23 */ 24 #define CACR_EC 0x80000000 /* Ena 25 #define CACR_ESB 0x20000000 /* Ena 26 #define CACR_DPI 0x10000000 /* Dis 27 #define CACR_HLCK 0x08000000 /* Hal 28 #define CACR_CINVA 0x01000000 /* Inv 29 #define CACR_DNFB 0x00000400 /* Inh 30 #define CACR_DCM_WT 0x00000000 /* Cac 31 #define CACR_DCM_CB 0x00000100 /* Cac 32 #define CACR_DCM_PRE 0x00000200 /* Cac 33 #define CACR_DCM_IMPRE 0x00000300 /* Cac 34 #define CACR_WPROTECT 0x00000020 /* Wri 35 #define CACR_EUSP 0x00000010 /* Ean 36 37 /* 38 * Define the Access Control register flags. 39 */ 40 #define ACR_BASE_POS 24 /* Add 41 #define ACR_MASK_POS 16 /* Add 42 #define ACR_ENABLE 0x00008000 /* Ena 43 #define ACR_USER 0x00000000 /* All 44 #define ACR_SUPER 0x00002000 /* All 45 #define ACR_ANY 0x00004000 /* All 46 #define ACR_CM_WT 0x00000000 /* Cac 47 #define ACR_CM_CB 0x00000020 /* Cac 48 #define ACR_CM_PRE 0x00000040 /* Cac 49 #define ACR_CM_IMPRE 0x00000060 /* Cac 50 #define ACR_WPROTECT 0x00000004 /* Wri 51 52 /* 53 * Define the cache type and arrangement (need 54 */ 55 #if defined(CONFIG_M5307) 56 #define CACHE_SIZE 0x2000 /* 8k 57 #define ICACHE_SIZE CACHE_SIZE 58 #define DCACHE_SIZE CACHE_SIZE 59 #elif defined(CONFIG_M53xx) 60 #define CACHE_SIZE 0x4000 /* 16k 61 #define ICACHE_SIZE CACHE_SIZE 62 #define DCACHE_SIZE CACHE_SIZE 63 #endif 64 65 #define CACHE_LINE_SIZE 16 /* 16 66 #define CACHE_WAYS 4 /* 4 w 67 68 /* 69 * Set the cache controller settings we will u 70 * CACR is cache inhibited, we use the ACR reg 71 * enabled on the regions we want (eg RAM). 72 */ 73 #if defined(CONFIG_CACHE_COPYBACK) 74 #define CACHE_TYPE ACR_CM_CB 75 #define CACHE_PUSH 76 #else 77 #define CACHE_TYPE ACR_CM_WT 78 #endif 79 80 #ifdef CONFIG_COLDFIRE_SW_A7 81 #define CACHE_MODE (CACR_EC + CACR_ESB + 82 #else 83 #define CACHE_MODE (CACR_EC + CACR_ESB + 84 #endif 85 86 /* 87 * Unified cache means we will never need to f 88 * instruction fetch. We will need to flush to 89 * coherency though in all cases. And for copy 90 * to push cached data as well. 91 */ 92 #define CACHE_INIT (CACHE_MODE + CACR_C 93 #define CACHE_INVALIDATE (CACHE_MODE + CACR_C 94 #define CACHE_INVALIDATED (CACHE_MODE + CACR_C 95 96 #define ACR0_MODE ((CONFIG_RAMBASE & 0xf 97 (0x000f0000) + \ 98 (ACR_ENABLE + ACR_ANY 99 #define ACR1_MODE 0 100 101 /********************************************* 102 #endif /* m53xxsim_h */ 103
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