1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * Coldfire generic GPIO support.
4 *
5 * (C) Copyright 2009, Steven King <sfking@fdw
6 */
7
8 #ifndef mcfgpio_h
9 #define mcfgpio_h
10
11 int __mcfgpio_get_value(unsigned gpio);
12 void __mcfgpio_set_value(unsigned gpio, int va
13 int __mcfgpio_direction_input(unsigned gpio);
14 int __mcfgpio_direction_output(unsigned gpio,
15 int __mcfgpio_request(unsigned gpio);
16 void __mcfgpio_free(unsigned gpio);
17
18 #ifdef CONFIG_GPIOLIB
19 #include <linux/gpio.h>
20 #else
21
22 /* our alternate 'gpiolib' functions */
23 static inline int __gpio_get_value(unsigned gp
24 {
25 if (gpio < MCFGPIO_PIN_MAX)
26 return __mcfgpio_get_value(gpi
27 else
28 return -EINVAL;
29 }
30
31 static inline void __gpio_set_value(unsigned g
32 {
33 if (gpio < MCFGPIO_PIN_MAX)
34 __mcfgpio_set_value(gpio, valu
35 }
36
37 static inline int __gpio_to_irq(unsigned gpio)
38 {
39 return -EINVAL;
40 }
41
42 static inline int gpio_direction_input(unsigne
43 {
44 if (gpio < MCFGPIO_PIN_MAX)
45 return __mcfgpio_direction_inp
46 else
47 return -EINVAL;
48 }
49
50 static inline int gpio_direction_output(unsign
51 {
52 if (gpio < MCFGPIO_PIN_MAX)
53 return __mcfgpio_direction_out
54 else
55 return -EINVAL;
56 }
57
58 static inline int gpio_request(unsigned gpio,
59 {
60 if (gpio < MCFGPIO_PIN_MAX)
61 return __mcfgpio_request(gpio)
62 else
63 return -EINVAL;
64 }
65
66 static inline void gpio_free(unsigned gpio)
67 {
68 if (gpio < MCFGPIO_PIN_MAX)
69 __mcfgpio_free(gpio);
70 }
71
72 #endif /* CONFIG_GPIOLIB */
73
74
75 /*
76 * The Freescale Coldfire family is quite vari
77 * Some parts have 8 bit ports, some have 16bi
78 * only one port, others have multiple ports;
79 * for both input and output, others have a se
80 * input; some require a read-modify-write acc
81 * have set and clear registers for some of th
82 * GPIOs in a single control area, others have
83 * different modules.
84 *
85 * This implementation attempts accommodate th
86 * a generic interface that will optimize to a
87 */
88 #if defined(CONFIG_M5206) || defined(CONFIG_M5
89 defined(CONFIG_M520x) || defined(CONFIG_M5
90 defined(CONFIG_M527x) || defined(CONFIG_M5
91 defined(CONFIG_M53xx) || defined(CONFIG_M5
92 defined(CONFIG_M5441x)
93
94 /* These parts have GPIO organized by 8 bit po
95
96 #define MCFGPIO_PORTTYPE u8
97 #define MCFGPIO_PORTSIZE 8
98 #define mcfgpio_read(port) __raw_
99 #define mcfgpio_write(data, port) __raw_
100
101 #elif defined(CONFIG_M5307) || defined(CONFIG_
102
103 /* These parts have GPIO organized by 16 bit p
104
105 #define MCFGPIO_PORTTYPE u16
106 #define MCFGPIO_PORTSIZE 16
107 #define mcfgpio_read(port) __raw_
108 #define mcfgpio_write(data, port) __raw_
109
110 #elif defined(CONFIG_M5249) || defined(CONFIG_
111
112 /* These parts have GPIO organized by 32 bit p
113
114 #define MCFGPIO_PORTTYPE u32
115 #define MCFGPIO_PORTSIZE 32
116 #define mcfgpio_read(port) __raw_
117 #define mcfgpio_write(data, port) __raw_
118
119 #endif
120
121 #define mcfgpio_bit(gpio) (1 <<
122 #define mcfgpio_port(gpio) ((gpio
123
124 #if defined(CONFIG_M520x) || defined(CONFIG_M5
125 defined(CONFIG_M527x) || defined(CONFIG_M5
126 defined(CONFIG_M53xx) || defined(CONFIG_M5
127 defined(CONFIG_M5441x)
128 /*
129 * These parts have an 'Edge' Port module (ext
130 * read-modify-write to change an output and a
131 * set/clr registers to directly change output
132 */
133 #if defined(CONFIG_M528x)
134 /*
135 * The 528x also has GPIOs in other modules (G
136 * read-modify-write as well as those controll
137 */
138 #define MCFGPIO_SCR_START 40
139 #elif defined(CONFIGM5441x)
140 /* The m5441x EPORT doesn't have its own GPIO
141 #define MCFGPIO_SCR_START 0
142 #else
143 #define MCFGPIO_SCR_START 8
144 #endif
145
146 #define MCFGPIO_SETR_PORT(gpio) (MCFGP
147 mcfgpi
148
149 #define MCFGPIO_CLRR_PORT(gpio) (MCFGP
150 mcfgpi
151 #else
152
153 #define MCFGPIO_SCR_START MCFGPI
154 /* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these
155 #define MCFGPIO_SETR_PORT(gpio) 0
156 #define MCFGPIO_CLRR_PORT(gpio) 0
157
158 #endif
159 /*
160 * Coldfire specific helper functions
161 */
162
163 /* return the port pin data register for a gpi
164 static inline u32 __mcfgpio_ppdr(unsigned gpio
165 {
166 #if defined(CONFIG_M5206) || defined(CONFIG_M5
167 defined(CONFIG_M5307) || defined(CONFIG_M5
168 return MCFSIM_PADAT;
169 #elif defined(CONFIG_M5272)
170 if (gpio < 16)
171 return MCFSIM_PADAT;
172 else if (gpio < 32)
173 return MCFSIM_PBDAT;
174 else
175 return MCFSIM_PCDAT;
176 #elif defined(CONFIG_M5249) || defined(CONFIG_
177 if (gpio < 32)
178 return MCFSIM2_GPIOREAD;
179 else
180 return MCFSIM2_GPIO1READ;
181 #elif defined(CONFIG_M520x) || defined(CONFIG_
182 defined(CONFIG_M527x) || defined(CONFIG_
183 defined(CONFIG_M53xx) || defined(CONFIG_
184 defined(CONFIG_M5441x)
185 #if !defined(CONFIG_M5441x)
186 if (gpio < 8)
187 return MCFEPORT_EPPDR;
188 #if defined(CONFIG_M528x)
189 else if (gpio < 16)
190 return MCFGPTA_GPTPORT;
191 else if (gpio < 24)
192 return MCFGPTB_GPTPORT;
193 else if (gpio < 32)
194 return MCFQADC_PORTQA;
195 else if (gpio < 40)
196 return MCFQADC_PORTQB;
197 #endif /* defined(CONFIG_M528x) */
198 else
199 #endif /* !defined(CONFIG_M5441x) */
200 return MCFGPIO_PPDR + mcfgpio_
201 #else
202 return 0;
203 #endif
204 }
205
206 /* return the port output data register for a
207 static inline u32 __mcfgpio_podr(unsigned gpio
208 {
209 #if defined(CONFIG_M5206) || defined(CONFIG_M5
210 defined(CONFIG_M5307) || defined(CONFIG_M5
211 return MCFSIM_PADAT;
212 #elif defined(CONFIG_M5272)
213 if (gpio < 16)
214 return MCFSIM_PADAT;
215 else if (gpio < 32)
216 return MCFSIM_PBDAT;
217 else
218 return MCFSIM_PCDAT;
219 #elif defined(CONFIG_M5249) || defined(CONFIG_
220 if (gpio < 32)
221 return MCFSIM2_GPIOWRITE;
222 else
223 return MCFSIM2_GPIO1WRITE;
224 #elif defined(CONFIG_M520x) || defined(CONFIG_
225 defined(CONFIG_M527x) || defined(CONFIG_
226 defined(CONFIG_M53xx) || defined(CONFIG_
227 defined(CONFIG_M5441x)
228 #if !defined(CONFIG_M5441x)
229 if (gpio < 8)
230 return MCFEPORT_EPDR;
231 #if defined(CONFIG_M528x)
232 else if (gpio < 16)
233 return MCFGPTA_GPTPORT;
234 else if (gpio < 24)
235 return MCFGPTB_GPTPORT;
236 else if (gpio < 32)
237 return MCFQADC_PORTQA;
238 else if (gpio < 40)
239 return MCFQADC_PORTQB;
240 #endif /* defined(CONFIG_M528x) */
241 else
242 #endif /* !defined(CONFIG_M5441x) */
243 return MCFGPIO_PODR + mcfgpio_
244 #else
245 return 0;
246 #endif
247 }
248
249 /* return the port direction data register for
250 static inline u32 __mcfgpio_pddr(unsigned gpio
251 {
252 #if defined(CONFIG_M5206) || defined(CONFIG_M5
253 defined(CONFIG_M5307) || defined(CONFIG_M5
254 return MCFSIM_PADDR;
255 #elif defined(CONFIG_M5272)
256 if (gpio < 16)
257 return MCFSIM_PADDR;
258 else if (gpio < 32)
259 return MCFSIM_PBDDR;
260 else
261 return MCFSIM_PCDDR;
262 #elif defined(CONFIG_M5249) || defined(CONFIG_
263 if (gpio < 32)
264 return MCFSIM2_GPIOENABLE;
265 else
266 return MCFSIM2_GPIO1ENABLE;
267 #elif defined(CONFIG_M520x) || defined(CONFIG_
268 defined(CONFIG_M527x) || defined(CONFIG_
269 defined(CONFIG_M53xx) || defined(CONFIG_
270 defined(CONFIG_M5441x)
271 #if !defined(CONFIG_M5441x)
272 if (gpio < 8)
273 return MCFEPORT_EPDDR;
274 #if defined(CONFIG_M528x)
275 else if (gpio < 16)
276 return MCFGPTA_GPTDDR;
277 else if (gpio < 24)
278 return MCFGPTB_GPTDDR;
279 else if (gpio < 32)
280 return MCFQADC_DDRQA;
281 else if (gpio < 40)
282 return MCFQADC_DDRQB;
283 #endif /* defined(CONFIG_M528x) */
284 else
285 #endif /* !defined(CONFIG_M5441x) */
286 return MCFGPIO_PDDR + mcfgpio_
287 #else
288 return 0;
289 #endif
290 }
291
292 #endif /* mcfgpio_h */
293
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