1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Device Tree Generator version: 1.1
4 *
5 * (C) Copyright 2007-2008 Xilinx, Inc.
6 * (C) Copyright 2007-2009 Michal Simek
7 *
8 * Michal SIMEK <monstr@monstr.eu>
9 *
10 * CAUTION: This file is automatically generat
11 * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
12 *
13 * XPS project directory: Xilinx-ML505-ll_tema
14 */
15
16 /dts-v1/;
17 / {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "xlnx,microblaze";
21 model = "testing";
22 DDR2_SDRAM: memory@90000000 {
23 device_type = "memory";
24 reg = < 0x90000000 0x10000000
25 } ;
26 aliases {
27 ethernet0 = &Hard_Ethernet_MAC
28 serial0 = &RS232_Uart_1;
29 } ;
30 chosen {
31 bootargs = "console=ttyUL0,115
32 stdout-path = "/plb@0/serial@8
33 } ;
34 cpus {
35 #address-cells = <1>;
36 #cpus = <0x1>;
37 #size-cells = <0>;
38 microblaze_0: cpu@0 {
39 clock-frequency = <125
40 compatible = "xlnx,mic
41 d-cache-baseaddr = <0x
42 d-cache-highaddr = <0x
43 d-cache-line-size = <0
44 d-cache-size = <0x2000
45 device_type = "cpu";
46 i-cache-baseaddr = <0x
47 i-cache-highaddr = <0x
48 i-cache-line-size = <0
49 i-cache-size = <0x2000
50 model = "microblaze,7.
51 reg = <0>;
52 timebase-frequency = <
53 xlnx,addr-tag-bits = <
54 xlnx,allow-dcache-wr =
55 xlnx,allow-icache-wr =
56 xlnx,area-optimized =
57 xlnx,cache-byte-size =
58 xlnx,d-lmb = <0x1>;
59 xlnx,d-opb = <0x0>;
60 xlnx,d-plb = <0x1>;
61 xlnx,data-size = <0x20
62 xlnx,dcache-addr-tag =
63 xlnx,dcache-always-use
64 xlnx,dcache-byte-size
65 xlnx,dcache-line-len =
66 xlnx,dcache-use-fsl =
67 xlnx,debug-enabled = <
68 xlnx,div-zero-exceptio
69 xlnx,dopb-bus-exceptio
70 xlnx,dynamic-bus-sizin
71 xlnx,edge-is-positive
72 xlnx,family = "virtex5
73 xlnx,endianness = <0x1
74 xlnx,fpu-exception = <
75 xlnx,fsl-data-size = <
76 xlnx,fsl-exception = <
77 xlnx,fsl-links = <0x0>
78 xlnx,i-lmb = <0x1>;
79 xlnx,i-opb = <0x0>;
80 xlnx,i-plb = <0x1>;
81 xlnx,icache-always-use
82 xlnx,icache-line-len =
83 xlnx,icache-use-fsl =
84 xlnx,ill-opcode-except
85 xlnx,instance = "micro
86 xlnx,interconnect = <0
87 xlnx,interrupt-is-edge
88 xlnx,iopb-bus-exceptio
89 xlnx,mmu-dtlb-size = <
90 xlnx,mmu-itlb-size = <
91 xlnx,mmu-tlb-access =
92 xlnx,mmu-zones = <0x10
93 xlnx,number-of-pc-brk
94 xlnx,number-of-rd-addr
95 xlnx,number-of-wr-addr
96 xlnx,opcode-0x0-illega
97 xlnx,pvr = <0x2>;
98 xlnx,pvr-user1 = <0x0>
99 xlnx,pvr-user2 = <0x0>
100 xlnx,reset-msr = <0x0>
101 xlnx,sco = <0x0>;
102 xlnx,unaligned-excepti
103 xlnx,use-barrel = <0x1
104 xlnx,use-dcache = <0x1
105 xlnx,use-div = <0x1>;
106 xlnx,use-ext-brk = <0x
107 xlnx,use-ext-nm-brk =
108 xlnx,use-extended-fsl-
109 xlnx,use-fpu = <0x2>;
110 xlnx,use-hw-mul = <0x2
111 xlnx,use-icache = <0x1
112 xlnx,use-interrupt = <
113 xlnx,use-mmu = <0x3>;
114 xlnx,use-msr-instr = <
115 xlnx,use-pcmp-instr =
116 } ;
117 } ;
118 mb_plb: plb@0 {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 compatible = "xlnx,plb-v46-1.0
122 ranges ;
123 FLASH: flash@a0000000 {
124 bank-width = <2>;
125 compatible = "xlnx,xps
126 reg = < 0xa0000000 0x2
127 xlnx,family = "virtex5
128 xlnx,include-datawidth
129 xlnx,include-datawidth
130 xlnx,include-datawidth
131 xlnx,include-datawidth
132 xlnx,include-negedge-i
133 xlnx,include-plb-ipif
134 xlnx,include-wrbuf = <
135 xlnx,max-mem-width = <
136 xlnx,mch-native-dwidth
137 xlnx,mch-plb-clk-perio
138 xlnx,mch-splb-awidth =
139 xlnx,mch0-accessbuf-de
140 xlnx,mch0-protocol = <
141 xlnx,mch0-rddatabuf-de
142 xlnx,mch1-accessbuf-de
143 xlnx,mch1-protocol = <
144 xlnx,mch1-rddatabuf-de
145 xlnx,mch2-accessbuf-de
146 xlnx,mch2-protocol = <
147 xlnx,mch2-rddatabuf-de
148 xlnx,mch3-accessbuf-de
149 xlnx,mch3-protocol = <
150 xlnx,mch3-rddatabuf-de
151 xlnx,mem0-width = <0x1
152 xlnx,mem1-width = <0x2
153 xlnx,mem2-width = <0x2
154 xlnx,mem3-width = <0x2
155 xlnx,num-banks-mem = <
156 xlnx,num-channels = <0
157 xlnx,priority-mode = <
158 xlnx,synch-mem-0 = <0x
159 xlnx,synch-mem-1 = <0x
160 xlnx,synch-mem-2 = <0x
161 xlnx,synch-mem-3 = <0x
162 xlnx,synch-pipedelay-0
163 xlnx,synch-pipedelay-1
164 xlnx,synch-pipedelay-2
165 xlnx,synch-pipedelay-3
166 xlnx,tavdv-ps-mem-0 =
167 xlnx,tavdv-ps-mem-1 =
168 xlnx,tavdv-ps-mem-2 =
169 xlnx,tavdv-ps-mem-3 =
170 xlnx,tcedv-ps-mem-0 =
171 xlnx,tcedv-ps-mem-1 =
172 xlnx,tcedv-ps-mem-2 =
173 xlnx,tcedv-ps-mem-3 =
174 xlnx,thzce-ps-mem-0 =
175 xlnx,thzce-ps-mem-1 =
176 xlnx,thzce-ps-mem-2 =
177 xlnx,thzce-ps-mem-3 =
178 xlnx,thzoe-ps-mem-0 =
179 xlnx,thzoe-ps-mem-1 =
180 xlnx,thzoe-ps-mem-2 =
181 xlnx,thzoe-ps-mem-3 =
182 xlnx,tlzwe-ps-mem-0 =
183 xlnx,tlzwe-ps-mem-1 =
184 xlnx,tlzwe-ps-mem-2 =
185 xlnx,tlzwe-ps-mem-3 =
186 xlnx,twc-ps-mem-0 = <0
187 xlnx,twc-ps-mem-1 = <0
188 xlnx,twc-ps-mem-2 = <0
189 xlnx,twc-ps-mem-3 = <0
190 xlnx,twp-ps-mem-0 = <0
191 xlnx,twp-ps-mem-1 = <0
192 xlnx,twp-ps-mem-2 = <0
193 xlnx,twp-ps-mem-3 = <0
194 xlnx,xcl0-linesize = <
195 xlnx,xcl0-writexfer =
196 xlnx,xcl1-linesize = <
197 xlnx,xcl1-writexfer =
198 xlnx,xcl2-linesize = <
199 xlnx,xcl2-writexfer =
200 xlnx,xcl3-linesize = <
201 xlnx,xcl3-writexfer =
202 } ;
203 Hard_Ethernet_MAC: xps-ll-tema
204 #address-cells = <1>;
205 #size-cells = <1>;
206 compatible = "xlnx,com
207 ranges ;
208 ethernet@81c00000 {
209 compatible = "
210 interrupt-pare
211 interrupts = <
212 llink-connecte
213 local-mac-addr
214 reg = < 0x81c0
215 xlnx,bus2core-
216 xlnx,phy-type
217 xlnx,phyaddr =
218 xlnx,rxcsum =
219 xlnx,rxfifo =
220 xlnx,temac-typ
221 xlnx,txcsum =
222 xlnx,txfifo =
223 } ;
224 } ;
225 IIC_EEPROM: i2c@81600000 {
226 compatible = "xlnx,xps
227 interrupt-parent = <&x
228 interrupts = < 6 2 >;
229 reg = < 0x81600000 0x1
230 xlnx,clk-freq = <0x773
231 xlnx,family = "virtex5
232 xlnx,gpo-width = <0x1>
233 xlnx,iic-freq = <0x186
234 xlnx,scl-inertial-dela
235 xlnx,sda-inertial-dela
236 xlnx,ten-bit-adr = <0x
237 } ;
238 LEDs_8Bit: gpio@81400000 {
239 compatible = "xlnx,xps
240 interrupt-parent = <&x
241 interrupts = < 7 2 >;
242 reg = < 0x81400000 0x1
243 xlnx,all-inputs = <0x0
244 xlnx,all-inputs-2 = <0
245 xlnx,dout-default = <0
246 xlnx,dout-default-2 =
247 xlnx,family = "virtex5
248 xlnx,gpio-width = <0x8
249 xlnx,interrupt-present
250 xlnx,is-bidir = <0x1>;
251 xlnx,is-bidir-2 = <0x1
252 xlnx,is-dual = <0x0>;
253 xlnx,tri-default = <0x
254 xlnx,tri-default-2 = <
255 #gpio-cells = <2>;
256 gpio-controller;
257 } ;
258
259 gpio-leds {
260 compatible = "gpio-led
261
262 heartbeat {
263 label = "Heart
264 gpios = <&LEDs
265 linux,default-
266 };
267
268 yellow {
269 label = "Yello
270 gpios = <&LEDs
271 };
272
273 red {
274 label = "Red";
275 gpios = <&LEDs
276 };
277
278 green {
279 label = "Green
280 gpios = <&LEDs
281 };
282 } ;
283
284 gpio-restart {
285 compatible = "gpio-res
286 /*
287 * FIXME: is this acti
288 * the current flag (1
289 * delay measures are
290 * to datasheet or tri
291 */
292 gpios = <&LEDs_8Bit 2
293 active-delay = <100>;
294 inactive-delay = <10>;
295 wait-delay = <100>;
296 };
297
298 RS232_Uart_1: serial@84000000
299 clock-frequency = <125
300 compatible = "xlnx,xps
301 current-speed = <11520
302 device_type = "serial"
303 interrupt-parent = <&x
304 interrupts = < 8 0 >;
305 port-number = <0>;
306 reg = < 0x84000000 0x1
307 xlnx,baudrate = <0x1c2
308 xlnx,data-bits = <0x8>
309 xlnx,family = "virtex5
310 xlnx,odd-parity = <0x0
311 xlnx,use-parity = <0x0
312 } ;
313 debug_module: debug@84400000 {
314 compatible = "xlnx,mdm
315 reg = < 0x84400000 0x1
316 xlnx,family = "virtex5
317 xlnx,interconnect = <0
318 xlnx,jtag-chain = <0x2
319 xlnx,mb-dbg-ports = <0
320 xlnx,uart-width = <0x8
321 xlnx,use-uart = <0x1>;
322 xlnx,write-fsl-ports =
323 } ;
324 mpmc@90000000 {
325 #address-cells = <1>;
326 #size-cells = <1>;
327 compatible = "xlnx,mpm
328 ranges ;
329 PIM3: sdma@84600180 {
330 compatible = "
331 interrupt-pare
332 interrupts = <
333 reg = < 0x8460
334 } ;
335 } ;
336 xps_intc_0: interrupt-controll
337 #interrupt-cells = <0x
338 compatible = "xlnx,xps
339 interrupt-controller ;
340 reg = < 0x81800000 0x1
341 xlnx,kind-of-intr = <0
342 xlnx,num-intr-inputs =
343 } ;
344 xps_timer_1: timer@83c00000 {
345 compatible = "xlnx,xps
346 interrupt-parent = <&x
347 interrupts = < 3 2 >;
348 reg = < 0x83c00000 0x1
349 xlnx,count-width = <0x
350 xlnx,one-timer-only =
351 } ;
352 } ;
353 } ;
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