Linux/arch/microblaze/kernel/head.S

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

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>> 1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* 2 /* 2 * Copyright (C) 2007-2009 Michal Simek <monstr !! 3 * arch/alpha/kernel/head.S 3 * Copyright (C) 2007-2009 PetaLogix << 4 * Copyright (C) 2006 Atmark Techno, Inc. << 5 * 4 * 6 * MMU code derived from arch/ppc/kernel/head_ !! 5 * initial boot stuff.. At this point, the bootloader has already 7 * Copyright (c) 1995-1996 Gary Thomas <gdt@ !! 6 * switched into OSF/1 PAL-code, and loaded us at the correct address 8 * Initial PowerPC version. !! 7 * (START_ADDR). So there isn't much left for us to do: just set up 9 * Copyright (c) 1996 Cort Dougan <cort@cs.n !! 8 * the kernel global pointer and jump to the kernel entry-point. 10 * Rewritten for PReP << 11 * Copyright (c) 1996 Paul Mackerras <paulus << 12 * Low-level exception handers, MMU suppo << 13 * Copyright (c) 1997 Dan Malek <dmalek@jlc. << 14 * PowerPC 8xx modifications. << 15 * Copyright (c) 1998-1999 TiVo, Inc. << 16 * PowerPC 403GCX modifications. << 17 * Copyright (c) 1999 Grant Erickson <grant@ << 18 * PowerPC 403GCX/405GP modifications. << 19 * Copyright 2000 MontaVista Software Inc. << 20 * PPC405 modifications << 21 * PowerPC 403GCX/405GP modifications. << 22 * Author: MontaVista Software, Inc. << 23 * frank_rowand@mvista.com or sou << 24 * debbie_chu@mvista.com << 25 * << 26 * This file is subject to the terms and condi << 27 * License. See the file "COPYING" in the main << 28 * for more details. << 29 */ 9 */ 30 10 31 #include <linux/init.h> 11 #include <linux/init.h> 32 #include <linux/linkage.h> !! 12 #include <asm/asm-offsets.h> 33 #include <asm/thread_info.h> !! 13 #include <asm/pal.h> 34 #include <asm/page.h> !! 14 #include <asm/setup.h> 35 #include <linux/of_fdt.h> /* for !! 15 36 !! 16 __HEAD 37 #include <asm/setup.h> /* COMMAND_LINE_SIZE */ !! 17 .globl _stext 38 #include <asm/mmu.h> !! 18 .set noreorder 39 #include <asm/processor.h> !! 19 .globl __start 40 !! 20 .ent __start 41 .section .data !! 21 _stext: 42 .global empty_zero_page !! 22 __start: 43 .align 12 !! 23 .prologue 0 44 empty_zero_page: !! 24 br $27,1f 45 .space PAGE_SIZE !! 25 1: ldgp $29,0($27) 46 .global swapper_pg_dir !! 26 /* We need to get current_task_info loaded up... */ 47 swapper_pg_dir: !! 27 lda $8,init_thread_union 48 .space PAGE_SIZE !! 28 /* ... and find our stack ... */ 49 !! 29 lda $30,0x4000 - SIZEOF_PT_REGS($8) 50 .section .rodata !! 30 /* ... and then we can start the kernel. */ 51 .align 4 !! 31 jsr $26,start_kernel 52 endian_check: !! 32 call_pal PAL_halt 53 .word 1 !! 33 .end __start 54 !! 34 55 __HEAD !! 35 #ifdef CONFIG_SMP 56 ENTRY(_start) !! 36 .align 3 57 #if CONFIG_KERNEL_BASE_ADDR == 0 !! 37 .globl __smp_callin 58 brai TOPHYS(real_start) !! 38 .ent __smp_callin 59 .org 0x100 !! 39 /* On entry here from SRM console, the HWPCB of the per-cpu 60 real_start: !! 40 slot for this processor has been loaded. We've arranged 61 #endif !! 41 for the UNIQUE value for this process to contain the PCBB 62 !! 42 of the target idle task. */ 63 mts rmsr, r0 !! 43 __smp_callin: 64 /* Disable stack protection from bootloader */ !! 44 .prologue 1 65 mts rslr, r0 !! 45 ldgp $29,0($27) # First order of business, load the GP. 66 addi r8, r0, 0xFFFFFFFF !! 46 67 mts rshr, r8 !! 47 call_pal PAL_rduniq # Grab the target PCBB. 68 /* !! 48 mov $0,$16 # Install it. 69 * According to Xilinx, msrclr instruction beh !! 49 call_pal PAL_swpctx 70 * if the msrclr instruction is not enabled. W !! 50 71 * if the opcode is available, by issuing msrc !! 51 lda $8,0x3fff # Find "current". 72 * r8 == 0 - msr instructions are implemented !! 52 bic $30,$8,$8 73 * r8 != 0 - msr instructions are not implemen !! 53 74 */ !! 54 jsr $26,smp_callin 75 mfs r1, rmsr !! 55 call_pal PAL_halt 76 msrclr r8, 0 /* clear nothing - just !! 56 .end __smp_callin 77 cmpu r8, r8, r1 /* r1 must contain !! 57 #endif /* CONFIG_SMP */ 78 !! 58 79 /* r7 may point to an FDT, or there may be one !! 59 # 80 if it's in r7, we've got to save it away AS !! 60 # The following two functions are needed for supporting SRM PALcode 81 We ensure r7 points to a valid FDT, just in !! 61 # on the PC164 (at least), since that PALcode manages the interrupt 82 is broken or non-existent */ !! 62 # masking, and we cannot duplicate the effort without causing problems 83 beqi r7, no_fdt_arg !! 63 # 84 /* Does r7 point to a valid FDT? Load HEADER m !! 64 85 /* Run time Big/Little endian platform !! 65 .align 3 86 /* Save 1 as word and load byte - 0 - !! 66 .globl cserve_ena 87 lbui r11, r0, TOPHYS(endian_check) !! 67 .ent cserve_ena 88 beqid r11, big_endian /* DO NOT brea !! 68 cserve_ena: 89 lw r11, r0, r7 /* Big endian load !! 69 .prologue 0 90 lwr r11, r0, r7 /* Little endian l !! 70 bis $16,$16,$17 91 big_endian: !! 71 lda $16,52($31) 92 rsubi r11, r11, OF_DT_HEADER /* Che !! 72 call_pal PAL_cserve 93 beqi r11, _prepare_copy_fdt !! 73 ret ($26) 94 or r7, r0, r0 /* cle !! 74 .end cserve_ena 95 bnei r11, no_fdt_arg !! 75 96 _prepare_copy_fdt: !! 76 .align 3 97 or r11, r0, r0 /* incremment */ !! 77 .globl cserve_dis 98 ori r4, r0, TOPHYS(_fdt_start) !! 78 .ent cserve_dis 99 ori r3, r0, (0x10000 - 4) !! 79 cserve_dis: 100 _copy_fdt: !! 80 .prologue 0 101 lw r12, r7, r11 /* r12 = r7 + r11 !! 81 bis $16,$16,$17 102 sw r12, r4, r11 /* addr[r4 + r11] !! 82 lda $16,53($31) 103 addik r11, r11, 4 /* increment count !! 83 call_pal PAL_cserve 104 bgtid r3, _copy_fdt /* loop for all !! 84 ret ($26) 105 addik r3, r3, -4 /* descrement loop !! 85 .end cserve_dis 106 no_fdt_arg: !! 86 107 !! 87 # 108 #ifndef CONFIG_CMDLINE_BOOL !! 88 # It is handy, on occasion, to make halt actually just loop. 109 /* !! 89 # Putting it here means we dont have to recompile the whole 110 * handling command line !! 90 # kernel. 111 * copy command line directly to cmd_line plac !! 91 # 112 */ !! 92 113 beqid r5, skip /* Skip if NUL !! 93 .align 3 114 or r11, r0, r0 /* inc !! 94 .globl halt 115 ori r4, r0, cmd_line /* loa !! 95 .ent halt 116 tophys(r4,r4) /* con !! 96 halt: 117 ori r3, r0, COMMAND_LINE_SIZE - 1 !! 97 .prologue 0 118 _copy_command_line: !! 98 call_pal PAL_halt 119 /* r2=r5+r11 - r5 contain pointer to c !! 99 .end halt 120 lbu r2, r5, r11 << 121 beqid r2, skip /* Ski << 122 sb r2, r4, r11 /* add << 123 addik r11, r11, 1 /* inc << 124 bgtid r3, _copy_command_line /* loo << 125 addik r3, r3, -1 /* dec << 126 addik r5, r4, 0 /* add << 127 tovirt(r5,r5) << 128 skip: << 129 #endif /* CONFIG_CMDLINE_BOOL */ << 130 << 131 #ifdef NOT_COMPILE << 132 /* save bram context */ << 133 or r11, r0, r0 << 134 ori r4, r0, TOPHYS(_bram_load_star << 135 ori r3, r0, (LMB_SIZE - 4) << 136 _copy_bram: << 137 lw r7, r0, r11 /* r7 << 138 sw r7, r4, r11 /* add << 139 addik r11, r11, 4 /* inc << 140 bgtid r3, _copy_bram /* loo << 141 addik r3, r3, -4 /* des << 142 #endif << 143 /* We have to turn on the MMU right aw << 144 << 145 /* << 146 * Set up the initial MMU state so we << 147 * kernel initialization. This maps t << 148 * virtual to physical. << 149 */ << 150 nop << 151 addik r3, r0, MICROBLAZE_TLB_SIZE -1 << 152 _invalidate: << 153 mts rtlbx, r3 << 154 mts rtlbhi, r0 << 155 mts rtlblo, r0 << 156 bgtid r3, _invalidate /* loo << 157 addik r3, r3, -1 << 158 /* sync */ << 159 << 160 /* Setup the kernel PID */ << 161 mts rpid,r0 /* Loa << 162 nop << 163 bri 4 << 164 << 165 /* << 166 * We should still be executing code a << 167 * RAM_BASEADDR at this point. However << 168 * a virtual address. So, set up a TLB << 169 * translation is enabled. << 170 */ << 171 << 172 addik r3,r0, CONFIG_KERNEL_START /* << 173 tophys(r4,r3) /* Loa << 174 << 175 /* start to do TLB calculation */ << 176 addik r12, r0, _end << 177 rsub r12, r3, r12 << 178 addik r12, r12, CONFIG_LOWMEM_SIZE > << 179 << 180 or r9, r0, r0 /* TLB0 = 0 */ << 181 or r10, r0, r0 /* TLB1 = 0 */ << 182 << 183 addik r11, r12, -0x1000000 << 184 bgei r11, GT16 /* size is greater t << 185 addik r11, r12, -0x0800000 << 186 bgei r11, GT8 /* size is greater th << 187 addik r11, r12, -0x0400000 << 188 bgei r11, GT4 /* size is greater th << 189 /* size is less than 4MB */ << 190 addik r11, r12, -0x0200000 << 191 bgei r11, GT2 /* size is greater th << 192 addik r9, r0, 0x0100000 /* TLB0 must << 193 addik r11, r12, -0x0100000 << 194 bgei r11, GT1 /* size is greater th << 195 /* TLB1 is 0 which is setup above */ << 196 bri tlb_end << 197 GT4: /* r11 contains the rest - will be either << 198 ori r9, r0, 0x400000 /* TLB0 is 4MB */ << 199 bri TLB1 << 200 GT16: /* TLB0 is 16MB */ << 201 addik r9, r0, 0x1000000 /* means TLB << 202 TLB1: << 203 /* must be used r2 because of subtract << 204 addik r2, r11, -0x0400000 << 205 bgei r2, GT20 /* size is greater th << 206 /* size is >16MB and <20MB */ << 207 addik r11, r11, -0x0100000 << 208 bgei r11, GT17 /* size is greater t << 209 /* kernel is >16MB and < 17MB */ << 210 GT1: << 211 addik r10, r0, 0x0100000 /* means TL << 212 bri tlb_end << 213 GT2: /* TLB0 is 0 and TLB1 will be 4MB */ << 214 GT17: /* TLB1 is 4MB - kernel size <20MB */ << 215 addik r10, r0, 0x0400000 /* means TL << 216 bri tlb_end << 217 GT8: /* TLB0 is still zero that's why I can us << 218 GT20: /* TLB1 is 16MB - kernel size >20MB */ << 219 addik r10, r0, 0x1000000 /* means TL << 220 tlb_end: << 221 << 222 /* << 223 * Configure and load two entries into << 224 * In case we are pinning TLBs, these << 225 * other TLB functions. If not reserv << 226 * matter where they are loaded. << 227 */ << 228 andi r4,r4,0xfffffc00 /* Mas << 229 ori r4,r4,(TLB_WR | TLB_EX) /* Set << 230 << 231 /* << 232 * TLB0 is always used - check if is n << 233 * if is use TLB1 value and clear it ( << 234 */ << 235 bnei r9, tlb0_not_zero << 236 add r9, r10, r0 << 237 add r10, r0, r0 << 238 tlb0_not_zero: << 239 << 240 /* look at the code below */ << 241 ori r30, r0, 0x200 << 242 andi r29, r9, 0x100000 << 243 bneid r29, 1f << 244 addik r30, r30, 0x80 << 245 andi r29, r9, 0x400000 << 246 bneid r29, 1f << 247 addik r30, r30, 0x80 << 248 andi r29, r9, 0x1000000 << 249 bneid r29, 1f << 250 addik r30, r30, 0x80 << 251 1: << 252 andi r3,r3,0xfffffc00 /* Mas << 253 ori r3,r3,(TLB_VALID) << 254 or r3, r3, r30 << 255 << 256 /* Load tlb_skip size value which is i << 257 lwi r11, r0, TOPHYS(tlb_skip) << 258 mts rtlbx,r11 /* TLB << 259 << 260 mts rtlblo,r4 /* Loa << 261 mts rtlbhi,r3 /* Loa << 262 << 263 /* Increase tlb_skip size */ << 264 addik r11, r11, 1 << 265 swi r11, r0, TOPHYS(tlb_skip) << 266 << 267 /* TLB1 can be zeroes that's why we no << 268 beqi r10, jump_over2 << 269 << 270 /* look at the code below */ << 271 ori r30, r0, 0x200 << 272 andi r29, r10, 0x100000 << 273 bneid r29, 1f << 274 addik r30, r30, 0x80 << 275 andi r29, r10, 0x400000 << 276 bneid r29, 1f << 277 addik r30, r30, 0x80 << 278 andi r29, r10, 0x1000000 << 279 bneid r29, 1f << 280 addik r30, r30, 0x80 << 281 1: << 282 addk r4, r4, r9 /* previous ad << 283 addk r3, r3, r9 << 284 << 285 andi r3,r3,0xfffffc00 /* Mas << 286 ori r3,r3,(TLB_VALID) << 287 or r3, r3, r30 << 288 << 289 lwi r11, r0, TOPHYS(tlb_skip) << 290 mts rtlbx, r11 /* r11 << 291 << 292 mts rtlblo,r4 /* Loa << 293 mts rtlbhi,r3 /* Loa << 294 << 295 /* Increase tlb_skip size */ << 296 addik r11, r11, 1 << 297 swi r11, r0, TOPHYS(tlb_skip) << 298 << 299 jump_over2: << 300 /* << 301 * Load a TLB entry for LMB, since we << 302 * the exception vectors, using a 4k r << 303 */ << 304 /* Use temporary TLB_ID for LMB - clea << 305 ori r11, r0, MICROBLAZE_LMB_TLB_ID << 306 mts rtlbx,r11 << 307 << 308 ori r4,r0,(TLB_WR | TLB_EX) << 309 ori r3,r0,(TLB_VALID | TLB_PAGESZ( << 310 << 311 mts rtlblo,r4 /* Loa << 312 mts rtlbhi,r3 /* Loa << 313 << 314 /* << 315 * We now have the lower 16 Meg of RAM << 316 * caches ready to work. << 317 */ << 318 turn_on_mmu: << 319 ori r15,r0,start_here << 320 ori r4,r0,MSR_KERNEL_VMS << 321 mts rmsr,r4 << 322 nop << 323 rted r15,0 /* ena << 324 nop << 325 << 326 start_here: << 327 << 328 /* Initialize small data anchors */ << 329 addik r13, r0, _KERNEL_SDA_BASE_ << 330 addik r2, r0, _KERNEL_SDA2_BASE_ << 331 << 332 /* Initialize stack pointer */ << 333 addik r1, r0, init_thread_union + TH << 334 << 335 /* Initialize r31 with current task ad << 336 addik r31, r0, init_task << 337 << 338 addik r11, r0, machine_early_init << 339 brald r15, r11 << 340 nop << 341 << 342 /* << 343 * Initialize the MMU. << 344 */ << 345 bralid r15, mmu_init << 346 nop << 347 << 348 /* Go back to running unmapped so we c << 349 * and change to using our exception v << 350 * On the MicroBlaze, all we invalidat << 351 * the old 16M byte TLB mappings. << 352 */ << 353 ori r15,r0,TOPHYS(kernel_load_cont << 354 ori r4,r0,MSR_KERNEL << 355 mts rmsr,r4 << 356 nop << 357 bri 4 << 358 rted r15,0 << 359 nop << 360 << 361 /* Load up the kernel context */ << 362 kernel_load_context: << 363 ori r5, r0, MICROBLAZE_LMB_TLB_ID << 364 mts rtlbx,r5 << 365 nop << 366 mts rtlbhi,r0 << 367 nop << 368 addi r15, r0, machine_halt << 369 ori r17, r0, start_kernel << 370 ori r4, r0, MSR_KERNEL_VMS << 371 mts rmsr, r4 << 372 nop << 373 rted r17, 0 /* enable MMU << 374 nop <<

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TOMOYO Linux Cross Reference
Linux/arch/microblaze/kernel/head.S

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Differences between /arch/microblaze/kernel/head.S (Architecture m68k) and /arch/alpha/kernel/head.S (Architecture alpha)

TOMOYO Linux Cross Reference Linux/arch/microblaze/kernel/head.S

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Differences between /arch/microblaze/kernel/head.S (Architecture m68k) and /arch/alpha/kernel/head.S (Architecture alpha)

TOMOYO Linux Cross Reference
Linux/arch/microblaze/kernel/head.S