1 /* 1 /*
2 * Copyright (C) 2007-2009 Michal Simek <monstr <<
3 * Copyright (C) 2007-2009 PetaLogix <<
4 * Copyright (C) 2006 Atmark Techno, Inc. <<
5 * <<
6 * MMU code derived from arch/ppc/kernel/head_ <<
7 * Copyright (c) 1995-1996 Gary Thomas <gdt@ <<
8 * Initial PowerPC version. <<
9 * Copyright (c) 1996 Cort Dougan <cort@cs.n <<
10 * Rewritten for PReP <<
11 * Copyright (c) 1996 Paul Mackerras <paulus <<
12 * Low-level exception handers, MMU suppo <<
13 * Copyright (c) 1997 Dan Malek <dmalek@jlc. <<
14 * PowerPC 8xx modifications. <<
15 * Copyright (c) 1998-1999 TiVo, Inc. <<
16 * PowerPC 403GCX modifications. <<
17 * Copyright (c) 1999 Grant Erickson <grant@ <<
18 * PowerPC 403GCX/405GP modifications. <<
19 * Copyright 2000 MontaVista Software Inc. <<
20 * PPC405 modifications <<
21 * PowerPC 403GCX/405GP modifications. <<
22 * Author: MontaVista Software, Inc. <<
23 * frank_rowand@mvista.com or sou <<
24 * debbie_chu@mvista.com <<
25 * <<
26 * This file is subject to the terms and condi 2 * This file is subject to the terms and conditions of the GNU General Public
27 * License. See the file "COPYING" in the main !! 3 * License. See the file "COPYING" in the main directory of this archive
28 * for more details. 4 * for more details.
>> 5 *
>> 6 * Copyright (C) 1994, 1995 Waldorf Electronics
>> 7 * Written by Ralf Baechle and Andreas Busse
>> 8 * Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle
>> 9 * Copyright (C) 1996 Paul M. Antoine
>> 10 * Modified for DECStation and hence R3000 support by Paul M. Antoine
>> 11 * Further modifications by David S. Miller and Harald Koerfgen
>> 12 * Copyright (C) 1999 Silicon Graphics, Inc.
>> 13 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
>> 14 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
29 */ 15 */
30 <<
31 #include <linux/init.h> 16 #include <linux/init.h>
32 #include <linux/linkage.h> !! 17 #include <linux/threads.h>
33 #include <asm/thread_info.h> !! 18
34 #include <asm/page.h> !! 19 #include <asm/addrspace.h>
35 #include <linux/of_fdt.h> /* for !! 20 #include <asm/asm.h>
36 !! 21 #include <asm/asmmacro.h>
37 #include <asm/setup.h> /* COMMAND_LINE_SIZE */ !! 22 #include <asm/irqflags.h>
38 #include <asm/mmu.h> !! 23 #include <asm/regdef.h>
39 #include <asm/processor.h> !! 24 #include <asm/pgtable-bits.h>
40 !! 25 #include <asm/mipsregs.h>
41 .section .data !! 26 #include <asm/stackframe.h>
42 .global empty_zero_page !! 27
43 .align 12 !! 28 #include <kernel-entry-init.h>
44 empty_zero_page: !! 29
45 .space PAGE_SIZE !! 30 /*
46 .global swapper_pg_dir !! 31 * inputs are the text nasid in t1, data nasid in t2.
47 swapper_pg_dir: !! 32 */
48 .space PAGE_SIZE !! 33 .macro MAPPED_KERNEL_SETUP_TLB
49 !! 34 #ifdef CONFIG_MAPPED_KERNEL
50 .section .rodata !! 35 /*
51 .align 4 !! 36 * This needs to read the nasid - assume 0 for now.
52 endian_check: !! 37 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
53 .word 1 !! 38 * 0+DVG in tlblo_1.
54 !! 39 */
55 __HEAD !! 40 dli t0, 0xffffffffc0000000
56 ENTRY(_start) !! 41 dmtc0 t0, CP0_ENTRYHI
57 #if CONFIG_KERNEL_BASE_ADDR == 0 !! 42 li t0, 0x1c000 # Offset of text into node memory
58 brai TOPHYS(real_start) !! 43 dsll t1, NASID_SHFT # Shift text nasid into place
59 .org 0x100 !! 44 dsll t2, NASID_SHFT # Same for data nasid
60 real_start: !! 45 or t1, t1, t0 # Physical load address of kernel text
>> 46 or t2, t2, t0 # Physical load address of kernel data
>> 47 dsrl t1, 12 # 4K pfn
>> 48 dsrl t2, 12 # 4K pfn
>> 49 dsll t1, 6 # Get pfn into place
>> 50 dsll t2, 6 # Get pfn into place
>> 51 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6)
>> 52 or t0, t0, t1
>> 53 mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
>> 54 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6)
>> 55 or t0, t0, t2
>> 56 mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr
>> 57 li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
>> 58 mtc0 t0, CP0_PAGEMASK
>> 59 li t0, 0 # KMAP_INX
>> 60 mtc0 t0, CP0_INDEX
>> 61 li t0, 1
>> 62 mtc0 t0, CP0_WIRED
>> 63 tlbwi
>> 64 #else
>> 65 mtc0 zero, CP0_WIRED
61 #endif 66 #endif
>> 67 .endm
62 68
63 mts rmsr, r0 !! 69 /*
64 /* Disable stack protection from bootloader */ !! 70 * For the moment disable interrupts, mark the kernel mode and
65 mts rslr, r0 !! 71 * set ST0_KX so that the CPU does not spit fire when using
66 addi r8, r0, 0xFFFFFFFF !! 72 * 64-bit addresses. A full initialization of the CPU's status
67 mts rshr, r8 !! 73 * register is done later in per_cpu_trap_init().
68 /* !! 74 */
69 * According to Xilinx, msrclr instruction beh !! 75 .macro setup_c0_status set clr
70 * if the msrclr instruction is not enabled. W !! 76 .set push
71 * if the opcode is available, by issuing msrc !! 77 #ifdef CONFIG_MIPS_MT_SMTC
72 * r8 == 0 - msr instructions are implemented !! 78 /*
73 * r8 != 0 - msr instructions are not implemen !! 79 * For SMTC, we need to set privilege and disable interrupts only for
74 */ !! 80 * the current TC, using the TCStatus register.
75 mfs r1, rmsr !! 81 */
76 msrclr r8, 0 /* clear nothing - just !! 82 mfc0 t0, CP0_TCSTATUS
77 cmpu r8, r8, r1 /* r1 must contain !! 83 /* Fortunately CU 0 is in the same place in both registers */
78 !! 84 /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
79 /* r7 may point to an FDT, or there may be one !! 85 li t1, ST0_CU0 | 0x08001c00
80 if it's in r7, we've got to save it away AS !! 86 or t0, t1
81 We ensure r7 points to a valid FDT, just in !! 87 /* Clear TKSU, leave IXMT */
82 is broken or non-existent */ !! 88 xori t0, 0x00001800
83 beqi r7, no_fdt_arg !! 89 mtc0 t0, CP0_TCSTATUS
84 /* Does r7 point to a valid FDT? Load HEADER m !! 90 _ehb
85 /* Run time Big/Little endian platform !! 91 /* We need to leave the global IE bit set, but clear EXL...*/
86 /* Save 1 as word and load byte - 0 - !! 92 mfc0 t0, CP0_STATUS
87 lbui r11, r0, TOPHYS(endian_check) !! 93 or t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr
88 beqid r11, big_endian /* DO NOT brea !! 94 xor t0, ST0_EXL | ST0_ERL | \clr
89 lw r11, r0, r7 /* Big endian load !! 95 mtc0 t0, CP0_STATUS
90 lwr r11, r0, r7 /* Little endian l !! 96 #else
91 big_endian: !! 97 mfc0 t0, CP0_STATUS
92 rsubi r11, r11, OF_DT_HEADER /* Che !! 98 or t0, ST0_CU0|\set|0x1f|\clr
93 beqi r11, _prepare_copy_fdt !! 99 xor t0, 0x1f|\clr
94 or r7, r0, r0 /* cle !! 100 mtc0 t0, CP0_STATUS
95 bnei r11, no_fdt_arg !! 101 .set noreorder
96 _prepare_copy_fdt: !! 102 sll zero,3 # ehb
97 or r11, r0, r0 /* incremment */ !! 103 #endif
98 ori r4, r0, TOPHYS(_fdt_start) !! 104 .set pop
99 ori r3, r0, (0x10000 - 4) !! 105 .endm
100 _copy_fdt: <<
101 lw r12, r7, r11 /* r12 = r7 + r11 <<
102 sw r12, r4, r11 /* addr[r4 + r11] <<
103 addik r11, r11, 4 /* increment count <<
104 bgtid r3, _copy_fdt /* loop for all <<
105 addik r3, r3, -4 /* descrement loop <<
106 no_fdt_arg: <<
107 106
108 #ifndef CONFIG_CMDLINE_BOOL !! 107 .macro setup_c0_status_pri
109 /* !! 108 #ifdef CONFIG_64BIT
110 * handling command line !! 109 setup_c0_status ST0_KX 0
111 * copy command line directly to cmd_line plac !! 110 #else
112 */ !! 111 setup_c0_status 0 0
113 beqid r5, skip /* Skip if NUL <<
114 or r11, r0, r0 /* inc <<
115 ori r4, r0, cmd_line /* loa <<
116 tophys(r4,r4) /* con <<
117 ori r3, r0, COMMAND_LINE_SIZE - 1 <<
118 _copy_command_line: <<
119 /* r2=r5+r11 - r5 contain pointer to c <<
120 lbu r2, r5, r11 <<
121 beqid r2, skip /* Ski <<
122 sb r2, r4, r11 /* add <<
123 addik r11, r11, 1 /* inc <<
124 bgtid r3, _copy_command_line /* loo <<
125 addik r3, r3, -1 /* dec <<
126 addik r5, r4, 0 /* add <<
127 tovirt(r5,r5) <<
128 skip: <<
129 #endif /* CONFIG_CMDLINE_BOOL */ <<
130 <<
131 #ifdef NOT_COMPILE <<
132 /* save bram context */ <<
133 or r11, r0, r0 <<
134 ori r4, r0, TOPHYS(_bram_load_star <<
135 ori r3, r0, (LMB_SIZE - 4) <<
136 _copy_bram: <<
137 lw r7, r0, r11 /* r7 <<
138 sw r7, r4, r11 /* add <<
139 addik r11, r11, 4 /* inc <<
140 bgtid r3, _copy_bram /* loo <<
141 addik r3, r3, -4 /* des <<
142 #endif 112 #endif
143 /* We have to turn on the MMU right aw !! 113 .endm
144 114
145 /* !! 115 .macro setup_c0_status_sec
146 * Set up the initial MMU state so we !! 116 #ifdef CONFIG_64BIT
147 * kernel initialization. This maps t !! 117 setup_c0_status ST0_KX ST0_BEV
148 * virtual to physical. !! 118 #else
149 */ !! 119 setup_c0_status 0 ST0_BEV
150 nop !! 120 #endif
151 addik r3, r0, MICROBLAZE_TLB_SIZE -1 !! 121 .endm
152 _invalidate: <<
153 mts rtlbx, r3 <<
154 mts rtlbhi, r0 <<
155 mts rtlblo, r0 <<
156 bgtid r3, _invalidate /* loo <<
157 addik r3, r3, -1 <<
158 /* sync */ <<
159 <<
160 /* Setup the kernel PID */ <<
161 mts rpid,r0 /* Loa <<
162 nop <<
163 bri 4 <<
164 122
>> 123 #ifndef CONFIG_NO_EXCEPT_FILL
165 /* 124 /*
166 * We should still be executing code a !! 125 * Reserved space for exception handlers.
167 * RAM_BASEADDR at this point. However !! 126 * Necessary for machines which link their kernels at KSEG0.
168 * a virtual address. So, set up a TLB <<
169 * translation is enabled. <<
170 */ 127 */
>> 128 .fill 0x400
>> 129 #endif
171 130
172 addik r3,r0, CONFIG_KERNEL_START /* !! 131 EXPORT(_stext)
173 tophys(r4,r3) /* Loa <<
174 <<
175 /* start to do TLB calculation */ <<
176 addik r12, r0, _end <<
177 rsub r12, r3, r12 <<
178 addik r12, r12, CONFIG_LOWMEM_SIZE > <<
179 <<
180 or r9, r0, r0 /* TLB0 = 0 */ <<
181 or r10, r0, r0 /* TLB1 = 0 */ <<
182 <<
183 addik r11, r12, -0x1000000 <<
184 bgei r11, GT16 /* size is greater t <<
185 addik r11, r12, -0x0800000 <<
186 bgei r11, GT8 /* size is greater th <<
187 addik r11, r12, -0x0400000 <<
188 bgei r11, GT4 /* size is greater th <<
189 /* size is less than 4MB */ <<
190 addik r11, r12, -0x0200000 <<
191 bgei r11, GT2 /* size is greater th <<
192 addik r9, r0, 0x0100000 /* TLB0 must <<
193 addik r11, r12, -0x0100000 <<
194 bgei r11, GT1 /* size is greater th <<
195 /* TLB1 is 0 which is setup above */ <<
196 bri tlb_end <<
197 GT4: /* r11 contains the rest - will be either <<
198 ori r9, r0, 0x400000 /* TLB0 is 4MB */ <<
199 bri TLB1 <<
200 GT16: /* TLB0 is 16MB */ <<
201 addik r9, r0, 0x1000000 /* means TLB <<
202 TLB1: <<
203 /* must be used r2 because of subtract <<
204 addik r2, r11, -0x0400000 <<
205 bgei r2, GT20 /* size is greater th <<
206 /* size is >16MB and <20MB */ <<
207 addik r11, r11, -0x0100000 <<
208 bgei r11, GT17 /* size is greater t <<
209 /* kernel is >16MB and < 17MB */ <<
210 GT1: <<
211 addik r10, r0, 0x0100000 /* means TL <<
212 bri tlb_end <<
213 GT2: /* TLB0 is 0 and TLB1 will be 4MB */ <<
214 GT17: /* TLB1 is 4MB - kernel size <20MB */ <<
215 addik r10, r0, 0x0400000 /* means TL <<
216 bri tlb_end <<
217 GT8: /* TLB0 is still zero that's why I can us <<
218 GT20: /* TLB1 is 16MB - kernel size >20MB */ <<
219 addik r10, r0, 0x1000000 /* means TL <<
220 tlb_end: <<
221 132
>> 133 #ifdef CONFIG_BOOT_RAW
222 /* 134 /*
223 * Configure and load two entries into !! 135 * Give us a fighting chance of running if execution beings at the
224 * In case we are pinning TLBs, these !! 136 * kernel load address. This is needed because this platform does
225 * other TLB functions. If not reserv !! 137 * not have a ELF loader yet.
226 * matter where they are loaded. <<
227 */ 138 */
228 andi r4,r4,0xfffffc00 /* Mas !! 139 FEXPORT(__kernel_entry)
229 ori r4,r4,(TLB_WR | TLB_EX) /* Set !! 140 j kernel_entry
>> 141 #endif
230 142
231 /* !! 143 __REF
232 * TLB0 is always used - check if is n <<
233 * if is use TLB1 value and clear it ( <<
234 */ <<
235 bnei r9, tlb0_not_zero <<
236 add r9, r10, r0 <<
237 add r10, r0, r0 <<
238 tlb0_not_zero: <<
239 <<
240 /* look at the code below */ <<
241 ori r30, r0, 0x200 <<
242 andi r29, r9, 0x100000 <<
243 bneid r29, 1f <<
244 addik r30, r30, 0x80 <<
245 andi r29, r9, 0x400000 <<
246 bneid r29, 1f <<
247 addik r30, r30, 0x80 <<
248 andi r29, r9, 0x1000000 <<
249 bneid r29, 1f <<
250 addik r30, r30, 0x80 <<
251 1: <<
252 andi r3,r3,0xfffffc00 /* Mas <<
253 ori r3,r3,(TLB_VALID) <<
254 or r3, r3, r30 <<
255 <<
256 /* Load tlb_skip size value which is i <<
257 lwi r11, r0, TOPHYS(tlb_skip) <<
258 mts rtlbx,r11 /* TLB <<
259 <<
260 mts rtlblo,r4 /* Loa <<
261 mts rtlbhi,r3 /* Loa <<
262 <<
263 /* Increase tlb_skip size */ <<
264 addik r11, r11, 1 <<
265 swi r11, r0, TOPHYS(tlb_skip) <<
266 <<
267 /* TLB1 can be zeroes that's why we no <<
268 beqi r10, jump_over2 <<
269 <<
270 /* look at the code below */ <<
271 ori r30, r0, 0x200 <<
272 andi r29, r10, 0x100000 <<
273 bneid r29, 1f <<
274 addik r30, r30, 0x80 <<
275 andi r29, r10, 0x400000 <<
276 bneid r29, 1f <<
277 addik r30, r30, 0x80 <<
278 andi r29, r10, 0x1000000 <<
279 bneid r29, 1f <<
280 addik r30, r30, 0x80 <<
281 1: <<
282 addk r4, r4, r9 /* previous ad <<
283 addk r3, r3, r9 <<
284 144
285 andi r3,r3,0xfffffc00 /* Mas !! 145 NESTED(kernel_entry, 16, sp) # kernel entry point
286 ori r3,r3,(TLB_VALID) <<
287 or r3, r3, r30 <<
288 146
289 lwi r11, r0, TOPHYS(tlb_skip) !! 147 kernel_entry_setup # cpu specific setup
290 mts rtlbx, r11 /* r11 <<
291 148
292 mts rtlblo,r4 /* Loa !! 149 setup_c0_status_pri
293 mts rtlbhi,r3 /* Loa <<
294 150
295 /* Increase tlb_skip size */ !! 151 /* We might not get launched at the address the kernel is linked to,
296 addik r11, r11, 1 !! 152 so we jump there. */
297 swi r11, r0, TOPHYS(tlb_skip) !! 153 PTR_LA t0, 0f
>> 154 jr t0
>> 155 0:
298 156
299 jump_over2: !! 157 #ifdef CONFIG_MIPS_MT_SMTC
300 /* 158 /*
301 * Load a TLB entry for LMB, since we !! 159 * In SMTC kernel, "CLI" is thread-specific, in TCStatus.
302 * the exception vectors, using a 4k r !! 160 * We still need to enable interrupts globally in Status,
>> 161 * and clear EXL/ERL.
>> 162 *
>> 163 * TCContext is used to track interrupt levels under
>> 164 * service in SMTC kernel. Clear for boot TC before
>> 165 * allowing any interrupts.
303 */ 166 */
304 /* Use temporary TLB_ID for LMB - clea !! 167 mtc0 zero, CP0_TCCONTEXT
305 ori r11, r0, MICROBLAZE_LMB_TLB_ID !! 168
306 mts rtlbx,r11 !! 169 mfc0 t0, CP0_STATUS
>> 170 ori t0, t0, 0xff1f
>> 171 xori t0, t0, 0x001e
>> 172 mtc0 t0, CP0_STATUS
>> 173 #endif /* CONFIG_MIPS_MT_SMTC */
307 174
308 ori r4,r0,(TLB_WR | TLB_EX) !! 175 PTR_LA t0, __bss_start # clear .bss
309 ori r3,r0,(TLB_VALID | TLB_PAGESZ( !! 176 LONG_S zero, (t0)
>> 177 PTR_LA t1, __bss_stop - LONGSIZE
>> 178 1:
>> 179 PTR_ADDIU t0, LONGSIZE
>> 180 LONG_S zero, (t0)
>> 181 bne t0, t1, 1b
>> 182
>> 183 LONG_S a0, fw_arg0 # firmware arguments
>> 184 LONG_S a1, fw_arg1
>> 185 LONG_S a2, fw_arg2
>> 186 LONG_S a3, fw_arg3
>> 187
>> 188 MTC0 zero, CP0_CONTEXT # clear context register
>> 189 PTR_LA $28, init_thread_union
>> 190 /* Set the SP after an empty pt_regs. */
>> 191 PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE
>> 192 PTR_ADDU sp, $28
>> 193 back_to_back_c0_hazard
>> 194 set_saved_sp sp, t0, t1
>> 195 PTR_SUBU sp, 4 * SZREG # init stack pointer
310 196
311 mts rtlblo,r4 /* Loa !! 197 j start_kernel
312 mts rtlbhi,r3 /* Loa !! 198 END(kernel_entry)
313 199
314 /* !! 200 __CPUINIT
315 * We now have the lower 16 Meg of RAM <<
316 * caches ready to work. <<
317 */ <<
318 turn_on_mmu: <<
319 ori r15,r0,start_here <<
320 ori r4,r0,MSR_KERNEL_VMS <<
321 mts rmsr,r4 <<
322 nop <<
323 rted r15,0 /* ena <<
324 nop <<
325 <<
326 start_here: <<
327 <<
328 /* Initialize small data anchors */ <<
329 addik r13, r0, _KERNEL_SDA_BASE_ <<
330 addik r2, r0, _KERNEL_SDA2_BASE_ <<
331 <<
332 /* Initialize stack pointer */ <<
333 addik r1, r0, init_thread_union + TH <<
334 <<
335 /* Initialize r31 with current task ad <<
336 addik r31, r0, init_task <<
337 <<
338 addik r11, r0, machine_early_init <<
339 brald r15, r11 <<
340 nop <<
341 201
>> 202 #ifdef CONFIG_SMP
>> 203 /*
>> 204 * SMP slave cpus entry point. Board specific code for bootstrap calls this
>> 205 * function after setting up the stack and gp registers.
>> 206 */
>> 207 NESTED(smp_bootstrap, 16, sp)
>> 208 #ifdef CONFIG_MIPS_MT_SMTC
342 /* 209 /*
343 * Initialize the MMU. !! 210 * Read-modify-writes of Status must be atomic, and this
344 */ !! 211 * is one case where CLI is invoked without EXL being
345 bralid r15, mmu_init !! 212 * necessarily set. The CLI and setup_c0_status will
346 nop !! 213 * in fact be redundant for all but the first TC of
>> 214 * each VPE being booted.
>> 215 */
>> 216 DMT 10 # dmt t2 /* t0, t1 are used by CLI and setup_c0_status() */
>> 217 jal mips_ihb
>> 218 #endif /* CONFIG_MIPS_MT_SMTC */
>> 219 setup_c0_status_sec
>> 220 smp_slave_setup
>> 221 #ifdef CONFIG_MIPS_MT_SMTC
>> 222 andi t2, t2, VPECONTROL_TE
>> 223 beqz t2, 2f
>> 224 EMT # emt
>> 225 2:
>> 226 #endif /* CONFIG_MIPS_MT_SMTC */
>> 227 j start_secondary
>> 228 END(smp_bootstrap)
>> 229 #endif /* CONFIG_SMP */
347 230
348 /* Go back to running unmapped so we c !! 231 __FINIT
349 * and change to using our exception v <<
350 * On the MicroBlaze, all we invalidat <<
351 * the old 16M byte TLB mappings. <<
352 */ <<
353 ori r15,r0,TOPHYS(kernel_load_cont <<
354 ori r4,r0,MSR_KERNEL <<
355 mts rmsr,r4 <<
356 nop <<
357 bri 4 <<
358 rted r15,0 <<
359 nop <<
360 <<
361 /* Load up the kernel context */ <<
362 kernel_load_context: <<
363 ori r5, r0, MICROBLAZE_LMB_TLB_ID <<
364 mts rtlbx,r5 <<
365 nop <<
366 mts rtlbhi,r0 <<
367 nop <<
368 addi r15, r0, machine_halt <<
369 ori r17, r0, start_kernel <<
370 ori r4, r0, MSR_KERNEL_VMS <<
371 mts rmsr, r4 <<
372 nop <<
373 rted r17, 0 /* enable MMU <<
374 nop <<
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