Linux/arch/microblaze/kernel/head.S

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

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1 /* 1 /* 2 * Copyright (C) 2007-2009 Michal Simek <monstr << 3 * Copyright (C) 2007-2009 PetaLogix << 4 * Copyright (C) 2006 Atmark Techno, Inc. << 5 * << 6 * MMU code derived from arch/ppc/kernel/head_ << 7 * Copyright (c) 1995-1996 Gary Thomas <gdt@ << 8 * Initial PowerPC version. << 9 * Copyright (c) 1996 Cort Dougan <cort@cs.n << 10 * Rewritten for PReP << 11 * Copyright (c) 1996 Paul Mackerras <paulus << 12 * Low-level exception handers, MMU suppo << 13 * Copyright (c) 1997 Dan Malek <dmalek@jlc. << 14 * PowerPC 8xx modifications. << 15 * Copyright (c) 1998-1999 TiVo, Inc. << 16 * PowerPC 403GCX modifications. << 17 * Copyright (c) 1999 Grant Erickson <grant@ << 18 * PowerPC 403GCX/405GP modifications. << 19 * Copyright 2000 MontaVista Software Inc. << 20 * PPC405 modifications << 21 * PowerPC 403GCX/405GP modifications. << 22 * Author: MontaVista Software, Inc. << 23 * frank_rowand@mvista.com or sou << 24 * debbie_chu@mvista.com << 25 * << 26 * This file is subject to the terms and condi 2 * This file is subject to the terms and conditions of the GNU General Public 27 * License. See the file "COPYING" in the main !! 3 * License. See the file "COPYING" in the main directory of this archive 28 * for more details. 4 * for more details. >> 5 * >> 6 * Copyright (C) 1994, 1995 Waldorf Electronics >> 7 * Written by Ralf Baechle and Andreas Busse >> 8 * Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle >> 9 * Copyright (C) 1996 Paul M. Antoine >> 10 * Modified for DECStation and hence R3000 support by Paul M. Antoine >> 11 * Further modifications by David S. Miller and Harald Koerfgen >> 12 * Copyright (C) 1999 Silicon Graphics, Inc. >> 13 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com >> 14 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 29 */ 15 */ 30 << 31 #include <linux/init.h> 16 #include <linux/init.h> 32 #include <linux/linkage.h> !! 17 #include <linux/threads.h> 33 #include <asm/thread_info.h> << 34 #include <asm/page.h> << 35 #include <linux/of_fdt.h> /* for << 36 << 37 #include <asm/setup.h> /* COMMAND_LINE_SIZE */ << 38 #include <asm/mmu.h> << 39 #include <asm/processor.h> << 40 << 41 .section .data << 42 .global empty_zero_page << 43 .align 12 << 44 empty_zero_page: << 45 .space PAGE_SIZE << 46 .global swapper_pg_dir << 47 swapper_pg_dir: << 48 .space PAGE_SIZE << 49 << 50 .section .rodata << 51 .align 4 << 52 endian_check: << 53 .word 1 << 54 << 55 __HEAD << 56 ENTRY(_start) << 57 #if CONFIG_KERNEL_BASE_ADDR == 0 << 58 brai TOPHYS(real_start) << 59 .org 0x100 << 60 real_start: << 61 #endif << 62 18 63 mts rmsr, r0 !! 19 #include <asm/addrspace.h> 64 /* Disable stack protection from bootloader */ !! 20 #include <asm/asm.h> 65 mts rslr, r0 !! 21 #include <asm/asmmacro.h> 66 addi r8, r0, 0xFFFFFFFF !! 22 #include <asm/irqflags.h> 67 mts rshr, r8 !! 23 #include <asm/regdef.h> 68 /* !! 24 #include <asm/mipsregs.h> 69 * According to Xilinx, msrclr instruction beh !! 25 #include <asm/stackframe.h> 70 * if the msrclr instruction is not enabled. W !! 26 71 * if the opcode is available, by issuing msrc !! 27 #include <kernel-entry-init.h> 72 * r8 == 0 - msr instructions are implemented !! 28 73 * r8 != 0 - msr instructions are not implemen !! 29 /* 74 */ !! 30 * For the moment disable interrupts, mark the kernel mode and 75 mfs r1, rmsr !! 31 * set ST0_KX so that the CPU does not spit fire when using 76 msrclr r8, 0 /* clear nothing - just !! 32 * 64-bit addresses. A full initialization of the CPU's status 77 cmpu r8, r8, r1 /* r1 must contain !! 33 * register is done later in per_cpu_trap_init(). 78 !! 34 */ 79 /* r7 may point to an FDT, or there may be one !! 35 .macro setup_c0_status set clr 80 if it's in r7, we've got to save it away AS !! 36 .set push 81 We ensure r7 points to a valid FDT, just in !! 37 mfc0 t0, CP0_STATUS 82 is broken or non-existent */ !! 38 or t0, ST0_CU0|\set|0x1f|\clr 83 beqi r7, no_fdt_arg !! 39 xor t0, 0x1f|\clr 84 /* Does r7 point to a valid FDT? Load HEADER m !! 40 mtc0 t0, CP0_STATUS 85 /* Run time Big/Little endian platform !! 41 .set noreorder 86 /* Save 1 as word and load byte - 0 - !! 42 sll zero,3 # ehb 87 lbui r11, r0, TOPHYS(endian_check) !! 43 .set pop 88 beqid r11, big_endian /* DO NOT brea !! 44 .endm 89 lw r11, r0, r7 /* Big endian load !! 45 90 lwr r11, r0, r7 /* Little endian l !! 46 .macro setup_c0_status_pri 91 big_endian: !! 47 #ifdef CONFIG_64BIT 92 rsubi r11, r11, OF_DT_HEADER /* Che !! 48 setup_c0_status ST0_KX 0 93 beqi r11, _prepare_copy_fdt !! 49 #else 94 or r7, r0, r0 /* cle !! 50 setup_c0_status 0 0 95 bnei r11, no_fdt_arg << 96 _prepare_copy_fdt: << 97 or r11, r0, r0 /* incremment */ << 98 ori r4, r0, TOPHYS(_fdt_start) << 99 ori r3, r0, (0x10000 - 4) << 100 _copy_fdt: << 101 lw r12, r7, r11 /* r12 = r7 + r11 << 102 sw r12, r4, r11 /* addr[r4 + r11] << 103 addik r11, r11, 4 /* increment count << 104 bgtid r3, _copy_fdt /* loop for all << 105 addik r3, r3, -4 /* descrement loop << 106 no_fdt_arg: << 107 << 108 #ifndef CONFIG_CMDLINE_BOOL << 109 /* << 110 * handling command line << 111 * copy command line directly to cmd_line plac << 112 */ << 113 beqid r5, skip /* Skip if NUL << 114 or r11, r0, r0 /* inc << 115 ori r4, r0, cmd_line /* loa << 116 tophys(r4,r4) /* con << 117 ori r3, r0, COMMAND_LINE_SIZE - 1 << 118 _copy_command_line: << 119 /* r2=r5+r11 - r5 contain pointer to c << 120 lbu r2, r5, r11 << 121 beqid r2, skip /* Ski << 122 sb r2, r4, r11 /* add << 123 addik r11, r11, 1 /* inc << 124 bgtid r3, _copy_command_line /* loo << 125 addik r3, r3, -1 /* dec << 126 addik r5, r4, 0 /* add << 127 tovirt(r5,r5) << 128 skip: << 129 #endif /* CONFIG_CMDLINE_BOOL */ << 130 << 131 #ifdef NOT_COMPILE << 132 /* save bram context */ << 133 or r11, r0, r0 << 134 ori r4, r0, TOPHYS(_bram_load_star << 135 ori r3, r0, (LMB_SIZE - 4) << 136 _copy_bram: << 137 lw r7, r0, r11 /* r7 << 138 sw r7, r4, r11 /* add << 139 addik r11, r11, 4 /* inc << 140 bgtid r3, _copy_bram /* loo << 141 addik r3, r3, -4 /* des << 142 #endif 51 #endif 143 /* We have to turn on the MMU right aw !! 52 .endm 144 53 145 /* !! 54 .macro setup_c0_status_sec 146 * Set up the initial MMU state so we !! 55 #ifdef CONFIG_64BIT 147 * kernel initialization. This maps t !! 56 setup_c0_status ST0_KX ST0_BEV 148 * virtual to physical. !! 57 #else 149 */ !! 58 setup_c0_status 0 ST0_BEV 150 nop !! 59 #endif 151 addik r3, r0, MICROBLAZE_TLB_SIZE -1 !! 60 .endm 152 _invalidate: << 153 mts rtlbx, r3 << 154 mts rtlbhi, r0 << 155 mts rtlblo, r0 << 156 bgtid r3, _invalidate /* loo << 157 addik r3, r3, -1 << 158 /* sync */ << 159 << 160 /* Setup the kernel PID */ << 161 mts rpid,r0 /* Loa << 162 nop << 163 bri 4 << 164 61 >> 62 #ifndef CONFIG_NO_EXCEPT_FILL 165 /* 63 /* 166 * We should still be executing code a !! 64 * Reserved space for exception handlers. 167 * RAM_BASEADDR at this point. However !! 65 * Necessary for machines which link their kernels at KSEG0. 168 * a virtual address. So, set up a TLB << 169 * translation is enabled. << 170 */ 66 */ >> 67 .fill 0x400 >> 68 #endif 171 69 172 addik r3,r0, CONFIG_KERNEL_START /* !! 70 EXPORT(_stext) 173 tophys(r4,r3) /* Loa << 174 << 175 /* start to do TLB calculation */ << 176 addik r12, r0, _end << 177 rsub r12, r3, r12 << 178 addik r12, r12, CONFIG_LOWMEM_SIZE > << 179 << 180 or r9, r0, r0 /* TLB0 = 0 */ << 181 or r10, r0, r0 /* TLB1 = 0 */ << 182 << 183 addik r11, r12, -0x1000000 << 184 bgei r11, GT16 /* size is greater t << 185 addik r11, r12, -0x0800000 << 186 bgei r11, GT8 /* size is greater th << 187 addik r11, r12, -0x0400000 << 188 bgei r11, GT4 /* size is greater th << 189 /* size is less than 4MB */ << 190 addik r11, r12, -0x0200000 << 191 bgei r11, GT2 /* size is greater th << 192 addik r9, r0, 0x0100000 /* TLB0 must << 193 addik r11, r12, -0x0100000 << 194 bgei r11, GT1 /* size is greater th << 195 /* TLB1 is 0 which is setup above */ << 196 bri tlb_end << 197 GT4: /* r11 contains the rest - will be either << 198 ori r9, r0, 0x400000 /* TLB0 is 4MB */ << 199 bri TLB1 << 200 GT16: /* TLB0 is 16MB */ << 201 addik r9, r0, 0x1000000 /* means TLB << 202 TLB1: << 203 /* must be used r2 because of subtract << 204 addik r2, r11, -0x0400000 << 205 bgei r2, GT20 /* size is greater th << 206 /* size is >16MB and <20MB */ << 207 addik r11, r11, -0x0100000 << 208 bgei r11, GT17 /* size is greater t << 209 /* kernel is >16MB and < 17MB */ << 210 GT1: << 211 addik r10, r0, 0x0100000 /* means TL << 212 bri tlb_end << 213 GT2: /* TLB0 is 0 and TLB1 will be 4MB */ << 214 GT17: /* TLB1 is 4MB - kernel size <20MB */ << 215 addik r10, r0, 0x0400000 /* means TL << 216 bri tlb_end << 217 GT8: /* TLB0 is still zero that's why I can us << 218 GT20: /* TLB1 is 16MB - kernel size >20MB */ << 219 addik r10, r0, 0x1000000 /* means TL << 220 tlb_end: << 221 71 >> 72 #ifdef CONFIG_BOOT_RAW 222 /* 73 /* 223 * Configure and load two entries into !! 74 * Give us a fighting chance of running if execution beings at the 224 * In case we are pinning TLBs, these !! 75 * kernel load address. This is needed because this platform does 225 * other TLB functions. If not reserv !! 76 * not have a ELF loader yet. 226 * matter where they are loaded. << 227 */ 77 */ 228 andi r4,r4,0xfffffc00 /* Mas !! 78 FEXPORT(__kernel_entry) 229 ori r4,r4,(TLB_WR | TLB_EX) /* Set !! 79 j kernel_entry >> 80 #endif 230 81 231 /* !! 82 __REF 232 * TLB0 is always used - check if is n << 233 * if is use TLB1 value and clear it ( << 234 */ << 235 bnei r9, tlb0_not_zero << 236 add r9, r10, r0 << 237 add r10, r0, r0 << 238 tlb0_not_zero: << 239 << 240 /* look at the code below */ << 241 ori r30, r0, 0x200 << 242 andi r29, r9, 0x100000 << 243 bneid r29, 1f << 244 addik r30, r30, 0x80 << 245 andi r29, r9, 0x400000 << 246 bneid r29, 1f << 247 addik r30, r30, 0x80 << 248 andi r29, r9, 0x1000000 << 249 bneid r29, 1f << 250 addik r30, r30, 0x80 << 251 1: << 252 andi r3,r3,0xfffffc00 /* Mas << 253 ori r3,r3,(TLB_VALID) << 254 or r3, r3, r30 << 255 << 256 /* Load tlb_skip size value which is i << 257 lwi r11, r0, TOPHYS(tlb_skip) << 258 mts rtlbx,r11 /* TLB << 259 << 260 mts rtlblo,r4 /* Loa << 261 mts rtlbhi,r3 /* Loa << 262 << 263 /* Increase tlb_skip size */ << 264 addik r11, r11, 1 << 265 swi r11, r0, TOPHYS(tlb_skip) << 266 << 267 /* TLB1 can be zeroes that's why we no << 268 beqi r10, jump_over2 << 269 << 270 /* look at the code below */ << 271 ori r30, r0, 0x200 << 272 andi r29, r10, 0x100000 << 273 bneid r29, 1f << 274 addik r30, r30, 0x80 << 275 andi r29, r10, 0x400000 << 276 bneid r29, 1f << 277 addik r30, r30, 0x80 << 278 andi r29, r10, 0x1000000 << 279 bneid r29, 1f << 280 addik r30, r30, 0x80 << 281 1: << 282 addk r4, r4, r9 /* previous ad << 283 addk r3, r3, r9 << 284 83 285 andi r3,r3,0xfffffc00 /* Mas !! 84 NESTED(kernel_entry, 16, sp) # kernel entry point 286 ori r3,r3,(TLB_VALID) << 287 or r3, r3, r30 << 288 85 289 lwi r11, r0, TOPHYS(tlb_skip) !! 86 kernel_entry_setup # cpu specific setup 290 mts rtlbx, r11 /* r11 << 291 87 292 mts rtlblo,r4 /* Loa !! 88 setup_c0_status_pri 293 mts rtlbhi,r3 /* Loa << 294 89 295 /* Increase tlb_skip size */ !! 90 /* We might not get launched at the address the kernel is linked to, 296 addik r11, r11, 1 !! 91 so we jump there. */ 297 swi r11, r0, TOPHYS(tlb_skip) !! 92 PTR_LA t0, 0f >> 93 jr t0 >> 94 0: 298 95 299 jump_over2: !! 96 #ifdef CONFIG_USE_OF 300 /* !! 97 #ifdef CONFIG_MIPS_RAW_APPENDED_DTB 301 * Load a TLB entry for LMB, since we !! 98 PTR_LA t2, __appended_dtb 302 * the exception vectors, using a 4k r << 303 */ << 304 /* Use temporary TLB_ID for LMB - clea << 305 ori r11, r0, MICROBLAZE_LMB_TLB_ID << 306 mts rtlbx,r11 << 307 99 308 ori r4,r0,(TLB_WR | TLB_EX) !! 100 #ifdef CONFIG_CPU_BIG_ENDIAN 309 ori r3,r0,(TLB_VALID | TLB_PAGESZ( !! 101 li t1, 0xd00dfeed >> 102 #else >> 103 li t1, 0xedfe0dd0 >> 104 #endif >> 105 lw t0, (t2) >> 106 beq t0, t1, dtb_found >> 107 #endif >> 108 li t1, -2 >> 109 move t2, a1 >> 110 beq a0, t1, dtb_found 310 111 311 mts rtlblo,r4 /* Loa !! 112 li t2, 0 312 mts rtlbhi,r3 /* Loa !! 113 dtb_found: >> 114 #endif >> 115 PTR_LA t0, __bss_start # clear .bss >> 116 LONG_S zero, (t0) >> 117 PTR_LA t1, __bss_stop - LONGSIZE >> 118 1: >> 119 PTR_ADDIU t0, LONGSIZE >> 120 LONG_S zero, (t0) >> 121 bne t0, t1, 1b >> 122 >> 123 LONG_S a0, fw_arg0 # firmware arguments >> 124 LONG_S a1, fw_arg1 >> 125 LONG_S a2, fw_arg2 >> 126 LONG_S a3, fw_arg3 313 127 314 /* !! 128 #ifdef CONFIG_USE_OF 315 * We now have the lower 16 Meg of RAM !! 129 LONG_S t2, fw_passed_dtb 316 * caches ready to work. !! 130 #endif 317 */ << 318 turn_on_mmu: << 319 ori r15,r0,start_here << 320 ori r4,r0,MSR_KERNEL_VMS << 321 mts rmsr,r4 << 322 nop << 323 rted r15,0 /* ena << 324 nop << 325 << 326 start_here: << 327 << 328 /* Initialize small data anchors */ << 329 addik r13, r0, _KERNEL_SDA_BASE_ << 330 addik r2, r0, _KERNEL_SDA2_BASE_ << 331 << 332 /* Initialize stack pointer */ << 333 addik r1, r0, init_thread_union + TH << 334 << 335 /* Initialize r31 with current task ad << 336 addik r31, r0, init_task << 337 << 338 addik r11, r0, machine_early_init << 339 brald r15, r11 << 340 nop << 341 131 342 /* !! 132 MTC0 zero, CP0_CONTEXT # clear context register 343 * Initialize the MMU. !! 133 PTR_LA $28, init_thread_union 344 */ !! 134 /* Set the SP after an empty pt_regs. */ 345 bralid r15, mmu_init !! 135 PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE 346 nop !! 136 PTR_ADDU sp, $28 >> 137 back_to_back_c0_hazard >> 138 set_saved_sp sp, t0, t1 >> 139 PTR_SUBU sp, 4 * SZREG # init stack pointer >> 140 >> 141 #ifdef CONFIG_RELOCATABLE >> 142 /* Copy kernel and apply the relocations */ >> 143 jal relocate_kernel >> 144 >> 145 /* Repoint the sp into the new kernel image */ >> 146 PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE >> 147 PTR_ADDU sp, $28 >> 148 set_saved_sp sp, t0, t1 >> 149 PTR_SUBU sp, 4 * SZREG # init stack pointer >> 150 >> 151 /* >> 152 * relocate_kernel returns the entry point either >> 153 * in the relocated kernel or the original if for >> 154 * some reason relocation failed - jump there now >> 155 * with instruction hazard barrier because of the >> 156 * newly sync'd icache. >> 157 */ >> 158 jr.hb v0 >> 159 #else >> 160 j start_kernel >> 161 #endif >> 162 END(kernel_entry) 347 163 348 /* Go back to running unmapped so we c !! 164 #ifdef CONFIG_SMP 349 * and change to using our exception v !! 165 /* 350 * On the MicroBlaze, all we invalidat !! 166 * SMP slave cpus entry point. Board specific code for bootstrap calls this 351 * the old 16M byte TLB mappings. !! 167 * function after setting up the stack and gp registers. 352 */ !! 168 */ 353 ori r15,r0,TOPHYS(kernel_load_cont !! 169 NESTED(smp_bootstrap, 16, sp) 354 ori r4,r0,MSR_KERNEL !! 170 smp_slave_setup 355 mts rmsr,r4 !! 171 setup_c0_status_sec 356 nop !! 172 j start_secondary 357 bri 4 !! 173 END(smp_bootstrap) 358 rted r15,0 !! 174 #endif /* CONFIG_SMP */ 359 nop << 360 << 361 /* Load up the kernel context */ << 362 kernel_load_context: << 363 ori r5, r0, MICROBLAZE_LMB_TLB_ID << 364 mts rtlbx,r5 << 365 nop << 366 mts rtlbhi,r0 << 367 nop << 368 addi r15, r0, machine_halt << 369 ori r17, r0, start_kernel << 370 ori r4, r0, MSR_KERNEL_VMS << 371 mts rmsr, r4 << 372 nop << 373 rted r17, 0 /* enable MMU << 374 nop <<

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TOMOYO Linux Cross Reference
Linux/arch/microblaze/kernel/head.S

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Differences between /arch/microblaze/kernel/head.S (Version linux-6.12-rc7) and /arch/mips/kernel/head.S (Version linux-4.9.337)

TOMOYO Linux Cross Reference Linux/arch/microblaze/kernel/head.S

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Differences between /arch/microblaze/kernel/head.S (Version linux-6.12-rc7) and /arch/mips/kernel/head.S (Version linux-4.9.337)

TOMOYO Linux Cross Reference
Linux/arch/microblaze/kernel/head.S