1 /* !! 1 #include <asm/asm-offsets.h>
2 * Copyright (C) 2008-2009 Michal Simek <monstr !! 2 #include <asm/thread_info.h>
3 * Copyright (C) 2008-2009 PetaLogix <<
4 * Copyright (C) 2006 Atmark Techno, Inc. <<
5 * <<
6 * This file is subject to the terms and condi <<
7 * License. See the file "COPYING" in the main <<
8 * for more details. <<
9 */ <<
10 3
11 OUTPUT_ARCH(microblaze) !! 4 #define PAGE_SIZE _PAGE_SIZE
12 ENTRY(microblaze_start) <<
13 5
14 #define RO_EXCEPTION_TABLE_ALIGN 16 !! 6 /*
>> 7 * Put .bss..swapper_pg_dir as the first thing in .bss. This will
>> 8 * ensure that it has .bss alignment (64K).
>> 9 */
>> 10 #define BSS_FIRST_SECTIONS *(.bss..swapper_pg_dir)
15 11
16 #include <asm/cache.h> <<
17 #include <asm/page.h> <<
18 #include <asm-generic/vmlinux.lds.h> 12 #include <asm-generic/vmlinux.lds.h>
19 #include <asm/thread_info.h> <<
20 13
21 #ifdef __MICROBLAZEEL__ !! 14 #undef mips
22 jiffies = jiffies_64; !! 15 #define mips mips
>> 16 OUTPUT_ARCH(mips)
>> 17 ENTRY(kernel_entry)
>> 18 PHDRS {
>> 19 text PT_LOAD FLAGS(7); /* RWX */
>> 20 #ifndef CONFIG_CAVIUM_OCTEON_SOC
>> 21 note PT_NOTE FLAGS(4); /* R__ */
>> 22 #endif /* CAVIUM_OCTEON_SOC */
>> 23 }
>> 24
>> 25 #ifdef CONFIG_32BIT
>> 26 #ifdef CONFIG_CPU_LITTLE_ENDIAN
>> 27 jiffies = jiffies_64;
>> 28 #else
>> 29 jiffies = jiffies_64 + 4;
>> 30 #endif
23 #else 31 #else
24 jiffies = jiffies_64 + 4; !! 32 jiffies = jiffies_64;
25 #endif 33 #endif
26 34
27 SECTIONS { !! 35 SECTIONS
28 . = CONFIG_KERNEL_START; !! 36 {
29 microblaze_start = CONFIG_KERNEL_BASE_ !! 37 #ifdef CONFIG_BOOT_ELF64
30 .text : AT(ADDR(.text) - LOAD_OFFSET) !! 38 /* Read-only sections, merged into text segment: */
31 _text = . ; !! 39 /* . = 0xc000000000000000; */
32 _stext = . ; !! 40
33 HEAD_TEXT !! 41 /* This is the value for an Origin kernel, taken from an IRIX kernel. */
>> 42 /* . = 0xc00000000001c000; */
>> 43
>> 44 /* Set the vaddr for the text segment to a value
>> 45 * >= 0xa800 0000 0001 9000 if no symmon is going to configured
>> 46 * >= 0xa800 0000 0030 0000 otherwise
>> 47 */
>> 48
>> 49 /* . = 0xa800000000300000; */
>> 50 . = 0xffffffff80300000;
>> 51 #endif
>> 52 . = VMLINUX_LOAD_ADDRESS;
>> 53 /* read-only */
>> 54 _text = .; /* Text and read-only data */
>> 55 .text : {
34 TEXT_TEXT 56 TEXT_TEXT
35 *(.fixup) <<
36 EXIT_TEXT <<
37 EXIT_CALL <<
38 SCHED_TEXT 57 SCHED_TEXT
39 LOCK_TEXT 58 LOCK_TEXT
40 KPROBES_TEXT 59 KPROBES_TEXT
41 IRQENTRY_TEXT 60 IRQENTRY_TEXT
42 SOFTIRQENTRY_TEXT !! 61 *(.text.*)
43 . = ALIGN (4) ; !! 62 *(.fixup)
44 _etext = . ; !! 63 *(.gnu.warning)
45 } !! 64 } :text = 0
46 !! 65 _etext = .; /* End of text section */
47 . = ALIGN (8) ; !! 66
48 __fdt_blob : AT(ADDR(__fdt_blob) - LOA !! 67 EXCEPTION_TABLE(16)
49 _fdt_start = . ; !! 68
50 *(__fdt_blob) ; !! 69 /* Exception table for data bus errors */
51 . = _fdt_start + 0x10000; !! 70 __dbe_table : {
52 _fdt_end = . ; !! 71 __start___dbe_table = .;
53 } !! 72 *(__dbe_table)
54 !! 73 __stop___dbe_table = .;
55 . = ALIGN(16); !! 74 }
56 RO_DATA(4096) !! 75
57 !! 76 #ifdef CONFIG_CAVIUM_OCTEON_SOC
58 /* !! 77 #define NOTES_HEADER
59 * sdata2 section can go anywhere, but !! 78 #else /* CONFIG_CAVIUM_OCTEON_SOC */
60 * and SDA2_BASE must point to the mid !! 79 #define NOTES_HEADER :note
61 */ !! 80 #endif /* CONFIG_CAVIUM_OCTEON_SOC */
62 .sdata2 : AT(ADDR(.sdata2) - LOAD_OFFS !! 81 NOTES :text NOTES_HEADER
63 _ssrw = .; !! 82 .dummy : { *(.dummy) } :text
64 . = ALIGN(PAGE_SIZE); /* page !! 83
65 *(.sdata2) !! 84 _sdata = .; /* Start of data section */
66 . = ALIGN(8); !! 85 RODATA
67 _essrw = .; !! 86
68 _ssrw_size = _essrw - _ssrw; !! 87 /* writeable */
69 _KERNEL_SDA2_BASE_ = _ssrw + (_ssrw_si !! 88 .data : { /* Data */
70 } !! 89 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */
71 !! 90
72 _sdata = . ; !! 91 INIT_TASK_DATA(THREAD_SIZE)
73 RW_DATA(32, PAGE_SIZE, THREAD_SIZE) !! 92 NOSAVE_DATA
74 _edata = . ; !! 93 PAGE_ALIGNED_DATA(PAGE_SIZE)
75 !! 94 CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
76 /* Under the microblaze ABI, .sdata an !! 95 READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
77 . = ALIGN(8); !! 96 DATA_DATA
78 .sdata : AT(ADDR(.sdata) - LOAD_OFFSET !! 97 CONSTRUCTORS
79 _ssro = .; !! 98 }
>> 99 _gp = . + 0x8000;
>> 100 .lit8 : {
>> 101 *(.lit8)
>> 102 }
>> 103 .lit4 : {
>> 104 *(.lit4)
>> 105 }
>> 106 /* We want the small data sections together, so single-instruction offsets
>> 107 can access them all, and initialized data all before uninitialized, so
>> 108 we can shorten the on-disk segment size. */
>> 109 .sdata : {
80 *(.sdata) 110 *(.sdata)
81 } 111 }
>> 112 _edata = .; /* End of data section */
82 113
83 .sbss : AT(ADDR(.sbss) - LOAD_OFFSET) !! 114 /* will be freed after init */
84 _ssbss = .; !! 115 . = ALIGN(PAGE_SIZE); /* Init code and data */
85 *(.sbss) <<
86 _esbss = .; <<
87 _essro = .; <<
88 _ssro_size = _essro - _ssro ; <<
89 _KERNEL_SDA_BASE_ = _ssro + (_ <<
90 } <<
91 <<
92 PERCPU_SECTION(L1_CACHE_BYTES) <<
93 <<
94 . = ALIGN(PAGE_SIZE); <<
95 __init_begin = .; 116 __init_begin = .;
96 <<
97 INIT_TEXT_SECTION(PAGE_SIZE) 117 INIT_TEXT_SECTION(PAGE_SIZE)
98 !! 118 INIT_DATA_SECTION(16)
99 .init.data : AT(ADDR(.init.data) - LOA <<
100 INIT_DATA <<
101 } <<
102 119
103 . = ALIGN(4); 120 . = ALIGN(4);
104 .init.ivt : AT(ADDR(.init.ivt) - LOAD_ !! 121 .mips.machines.init : AT(ADDR(.mips.machines.init) - LOAD_OFFSET) {
105 __ivt_start = .; !! 122 __mips_machines_start = .;
106 *(.init.ivt) !! 123 *(.mips.machines.init)
107 __ivt_end = .; !! 124 __mips_machines_end = .;
108 } 125 }
109 126
110 .init.setup : AT(ADDR(.init.setup) - L !! 127 /* .exit.text is discarded at runtime, not link time, to deal with
111 INIT_SETUP(0) !! 128 * references from .rodata
>> 129 */
>> 130 .exit.text : {
>> 131 EXIT_TEXT
112 } 132 }
113 !! 133 .exit.data : {
114 .initcall.init : AT(ADDR(.initcall.ini !! 134 EXIT_DATA
115 INIT_CALLS <<
116 } 135 }
117 !! 136 #ifdef CONFIG_SMP
118 .con_initcall.init : AT(ADDR(.con_init !! 137 PERCPU_SECTION(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
119 CON_INITCALL !! 138 #endif
>> 139 #ifdef CONFIG_MIPS_RAW_APPENDED_DTB
>> 140 __appended_dtb = .;
>> 141 /* leave space for appended DTB */
>> 142 . += 0x100000;
>> 143 #elif defined(CONFIG_MIPS_ELF_APPENDED_DTB)
>> 144 .appended_dtb : AT(ADDR(.appended_dtb) - LOAD_OFFSET) {
>> 145 *(.appended_dtb)
>> 146 KEEP(*(.appended_dtb))
120 } 147 }
>> 148 #endif
>> 149 /*
>> 150 * Align to 64K in attempt to eliminate holes before the
>> 151 * .bss..swapper_pg_dir section at the start of .bss. This
>> 152 * also satisfies PAGE_SIZE alignment as the largest page size
>> 153 * allowed is 64K.
>> 154 */
>> 155 . = ALIGN(0x10000);
>> 156 __init_end = .;
>> 157 /* freed after init ends here */
>> 158
>> 159 /*
>> 160 * Force .bss to 64K alignment so that .bss..swapper_pg_dir
>> 161 * gets that alignment. .sbss should be empty, so there will be
>> 162 * no holes after __init_end. */
>> 163 BSS_SECTION(0, 0x10000, 8)
>> 164
>> 165 _end = . ;
121 166
122 __init_end_before_initramfs = .; !! 167 /* These mark the ABI of the kernel for debuggers. */
>> 168 .mdebug.abi32 : {
>> 169 KEEP(*(.mdebug.abi32))
>> 170 }
>> 171 .mdebug.abi64 : {
>> 172 KEEP(*(.mdebug.abi64))
>> 173 }
123 174
124 .init.ramfs : AT(ADDR(.init.ramfs) - L !! 175 /* This is the MIPS specific mdebug section. */
125 INIT_RAM_FS !! 176 .mdebug : {
>> 177 *(.mdebug)
126 } 178 }
127 179
128 __init_end = .; !! 180 STABS_DEBUG
>> 181 DWARF_DEBUG
129 182
130 .bss ALIGN (PAGE_SIZE) : AT(ADDR(.bss) !! 183 /* These must appear regardless of . */
131 /* page aligned when MMU used !! 184 .gptab.sdata : {
132 __bss_start = . ; !! 185 *(.gptab.data)
133 *(.bss*) !! 186 *(.gptab.sdata)
134 *(COMMON) !! 187 }
135 . = ALIGN (4) ; !! 188 .gptab.sbss : {
136 __bss_stop = . ; !! 189 *(.gptab.bss)
>> 190 *(.gptab.sbss)
137 } 191 }
138 . = ALIGN(PAGE_SIZE); <<
139 _end = .; <<
140 192
>> 193 /* Sections to be discarded */
141 DISCARDS 194 DISCARDS
>> 195 /DISCARD/ : {
>> 196 /* ABI crap starts here */
>> 197 *(.MIPS.abiflags)
>> 198 *(.MIPS.options)
>> 199 *(.options)
>> 200 *(.pdr)
>> 201 *(.reginfo)
>> 202 *(.eh_frame)
>> 203 }
142 } 204 }
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