1 # SPDX-License-Identifier: GPL-2.0 !! 1 # SPDX-License-Identifier: GPL-2.0-only
2 config MIPS !! 2 config 64BIT
>> 3 bool "64-bit kernel" if "$(ARCH)" = "sparc"
>> 4 default "$(ARCH)" = "sparc64"
>> 5 help
>> 6 SPARC is a family of RISC microprocessors designed and marketed by
>> 7 Sun Microsystems, incorporated. They are very widely found in Sun
>> 8 workstations and clones.
>> 9
>> 10 Say yes to build a 64-bit kernel - formerly known as sparc64
>> 11 Say no to build a 32-bit kernel - formerly known as sparc
>> 12
>> 13 config SPARC
3 bool 14 bool
4 default y 15 default y
5 select ARCH_32BIT_OFF_T if !64BIT <<
6 select ARCH_BINFMT_ELF_STATE if MIPS_F <<
7 select ARCH_HAS_CPU_CACHE_ALIASING 16 select ARCH_HAS_CPU_CACHE_ALIASING
8 select ARCH_HAS_CPU_FINALIZE_INIT !! 17 select ARCH_HAS_DMA_OPS
9 select ARCH_HAS_CURRENT_STACK_POINTER !! 18 select ARCH_MIGHT_HAVE_PC_PARPORT if SPARC64 && PCI
10 select ARCH_HAS_DEBUG_VIRTUAL if !64BI !! 19 select ARCH_MIGHT_HAVE_PC_SERIO
11 select ARCH_HAS_DMA_OPS if MACH_JAZZ !! 20 select OF
12 select ARCH_HAS_FORTIFY_SOURCE !! 21 select OF_PROMTREE
13 select ARCH_HAS_KCOV !! 22 select HAVE_ASM_MODVERSIONS
14 select ARCH_HAS_NON_OVERLAPPING_ADDRES !! 23 select HAVE_ARCH_KGDB if !SMP || SPARC64
15 select ARCH_HAS_PTE_SPECIAL if !(32BIT !! 24 select HAVE_ARCH_TRACEHOOK
16 select ARCH_HAS_STRNCPY_FROM_USER !! 25 select HAVE_ARCH_SECCOMP if SPARC64
17 select ARCH_HAS_STRNLEN_USER !! 26 select HAVE_EXIT_THREAD
18 select ARCH_HAS_TICK_BROADCAST if GENE !! 27 select HAVE_PCI
19 select ARCH_HAS_UBSAN !! 28 select SYSCTL_EXCEPTION_TRACE
20 select ARCH_HAS_GCOV_PROFILE_ALL !! 29 select RTC_CLASS
21 select ARCH_KEEP_MEMBLOCK !! 30 select RTC_DRV_M48T59
22 select ARCH_USE_BUILTIN_BSWAP !! 31 select RTC_SYSTOHC
23 select ARCH_USE_CMPXCHG_LOCKREF if 64B !! 32 select HAVE_ARCH_JUMP_LABEL if SPARC64
24 select ARCH_USE_MEMTEST <<
25 select ARCH_USE_QUEUED_RWLOCKS <<
26 select ARCH_USE_QUEUED_SPINLOCKS <<
27 select ARCH_SUPPORTS_HUGETLBFS if CPU_ <<
28 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
29 select ARCH_WANT_IPC_PARSE_VERSION <<
30 select ARCH_WANT_LD_ORPHAN_WARN <<
31 select BUILDTIME_TABLE_SORT <<
32 select CLONE_BACKWARDS <<
33 select CPU_NO_EFFICIENT_FFS if (TARGET <<
34 select CPU_PM if CPU_IDLE || SUSPEND <<
35 select GENERIC_ATOMIC64 if !64BIT <<
36 select GENERIC_CMOS_UPDATE <<
37 select GENERIC_CPU_AUTOPROBE <<
38 select GENERIC_GETTIMEOFDAY <<
39 select GENERIC_IOMAP <<
40 select GENERIC_IRQ_PROBE <<
41 select GENERIC_IRQ_SHOW 33 select GENERIC_IRQ_SHOW
42 select GENERIC_ISA_DMA if EISA !! 34 select ARCH_WANT_IPC_PARSE_VERSION
43 select GENERIC_LIB_ASHLDI3 !! 35 select GENERIC_PCI_IOMAP
44 select GENERIC_LIB_ASHRDI3 !! 36 select HAS_IOPORT
>> 37 select HAVE_HARDLOCKUP_DETECTOR_SPARC64 if SPARC64
>> 38 select HAVE_CBPF_JIT if SPARC32
>> 39 select HAVE_EBPF_JIT if SPARC64
>> 40 select HAVE_DEBUG_BUGVERBOSE
>> 41 select GENERIC_SMP_IDLE_THREAD
>> 42 select MODULES_USE_ELF_RELA
>> 43 select PCI_SYSCALL if PCI
>> 44 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
>> 45 select ODD_RT_SIGACTION
>> 46 select OLD_SIGSUSPEND
>> 47 select CPU_NO_EFFICIENT_FFS
>> 48 select LOCKDEP_SMALL if LOCKDEP
>> 49 select NEED_DMA_MAP_STATE
>> 50 select NEED_SG_DMA_LENGTH
>> 51 select TRACE_IRQFLAGS_SUPPORT
>> 52
>> 53 config SPARC32
>> 54 def_bool !64BIT
>> 55 select ARCH_32BIT_OFF_T
>> 56 select ARCH_HAS_CPU_FINALIZE_INIT if !SMP
>> 57 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 58 select CLZ_TAB
>> 59 select DMA_DIRECT_REMAP
>> 60 select GENERIC_ATOMIC64
45 select GENERIC_LIB_CMPDI2 61 select GENERIC_LIB_CMPDI2
46 select GENERIC_LIB_LSHRDI3 <<
47 select GENERIC_LIB_UCMPDI2 62 select GENERIC_LIB_UCMPDI2
48 select GENERIC_SCHED_CLOCK if !CAVIUM_ !! 63 select HAVE_UID16
49 select GENERIC_SMP_IDLE_THREAD !! 64 select HAVE_PAGE_SIZE_4KB
50 select GENERIC_IDLE_POLL_SETUP !! 65 select LOCK_MM_AND_FIND_VMA
51 select GENERIC_TIME_VSYSCALL !! 66 select OLD_SIGACTION
52 select GUP_GET_PXX_LOW_HIGH if CPU_MIP !! 67 select ZONE_DMA
53 select HAS_IOPORT if !NO_IOPORT_MAP || !! 68
54 select HAVE_ARCH_COMPILER_H !! 69 config SPARC64
55 select HAVE_ARCH_JUMP_LABEL !! 70 def_bool 64BIT
56 select HAVE_ARCH_KGDB if MIPS_FP_SUPPO !! 71 select ALTERNATE_USER_ADDRESS_SPACE
57 select HAVE_ARCH_MMAP_RND_BITS if MMU !! 72 select HAVE_FUNCTION_TRACER
58 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 73 select HAVE_FUNCTION_GRAPH_TRACER
59 select HAVE_ARCH_SECCOMP_FILTER !! 74 select HAVE_KRETPROBES
60 select HAVE_ARCH_TRACEHOOK !! 75 select HAVE_KPROBES
61 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 76 select MMU_GATHER_RCU_TABLE_FREE if SMP
62 select HAVE_ASM_MODVERSIONS !! 77 select MMU_GATHER_MERGE_VMAS
>> 78 select MMU_GATHER_NO_FLUSH_CACHE
>> 79 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
>> 80 select HAVE_DYNAMIC_FTRACE
>> 81 select HAVE_FTRACE_MCOUNT_RECORD
>> 82 select HAVE_PAGE_SIZE_8KB
>> 83 select HAVE_SYSCALL_TRACEPOINTS
63 select HAVE_CONTEXT_TRACKING_USER 84 select HAVE_CONTEXT_TRACKING_USER
64 select HAVE_TIF_NOHZ 85 select HAVE_TIF_NOHZ
65 select HAVE_C_RECORDMCOUNT <<
66 select HAVE_DEBUG_KMEMLEAK 86 select HAVE_DEBUG_KMEMLEAK
67 select HAVE_DEBUG_STACKOVERFLOW !! 87 select IOMMU_HELPER
68 select HAVE_DMA_CONTIGUOUS !! 88 select SPARSE_IRQ
69 select HAVE_DYNAMIC_FTRACE !! 89 select RTC_DRV_CMOS
70 select HAVE_EBPF_JIT if !CPU_MICROMIPS !! 90 select RTC_DRV_BQ4802
71 select HAVE_EXIT_THREAD !! 91 select RTC_DRV_SUN4V
72 select HAVE_GUP_FAST !! 92 select RTC_DRV_STARFIRE
73 select HAVE_FTRACE_MCOUNT_RECORD <<
74 select HAVE_FUNCTION_GRAPH_TRACER <<
75 select HAVE_FUNCTION_TRACER <<
76 select HAVE_GCC_PLUGINS <<
77 select HAVE_GENERIC_VDSO <<
78 select HAVE_IOREMAP_PROT <<
79 select HAVE_IRQ_EXIT_ON_IRQ_STACK <<
80 select HAVE_IRQ_TIME_ACCOUNTING <<
81 select HAVE_KPROBES <<
82 select HAVE_KRETPROBES <<
83 select HAVE_LD_DEAD_CODE_DATA_ELIMINAT <<
84 select HAVE_MOD_ARCH_SPECIFIC <<
85 select HAVE_NMI <<
86 select HAVE_PAGE_SIZE_4KB if !CPU_LOON <<
87 select HAVE_PAGE_SIZE_16KB if !CPU_R30 <<
88 select HAVE_PAGE_SIZE_64KB if !CPU_R30 <<
89 select HAVE_PERF_EVENTS 93 select HAVE_PERF_EVENTS
90 select HAVE_PERF_REGS <<
91 select HAVE_PERF_USER_STACK_DUMP <<
92 select HAVE_REGS_AND_STACK_ACCESS_API <<
93 select HAVE_RSEQ <<
94 select HAVE_SPARSE_SYSCALL_NR <<
95 select HAVE_STACKPROTECTOR <<
96 select HAVE_SYSCALL_TRACEPOINTS <<
97 select HAVE_VIRT_CPU_ACCOUNTING_GEN if <<
98 select IRQ_FORCED_THREADING <<
99 select ISA if EISA <<
100 select LOCK_MM_AND_FIND_VMA <<
101 select MODULES_USE_ELF_REL if MODULES <<
102 select MODULES_USE_ELF_RELA if MODULES <<
103 select PERF_USE_VMALLOC 94 select PERF_USE_VMALLOC
104 select PCI_MSI_ARCH_FALLBACKS if PCI_M !! 95 select ARCH_HAVE_NMI_SAFE_CMPXCHG
105 select RTC_LIB !! 96 select HAVE_C_RECORDMCOUNT
106 select SYSCTL_EXCEPTION_TRACE !! 97 select HAVE_ARCH_AUDITSYSCALL
107 select TRACE_IRQFLAGS_SUPPORT !! 98 select ARCH_SUPPORTS_ATOMIC_RMW
108 select ARCH_HAS_ELFCORE_COMPAT !! 99 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
109 select HAVE_ARCH_KCSAN if 64BIT !! 100 select HAVE_NMI
110 !! 101 select HAVE_REGS_AND_STACK_ACCESS_API
111 config MIPS_FIXUP_BIGPHYS_ADDR !! 102 select ARCH_USE_QUEUED_RWLOCKS
112 bool !! 103 select ARCH_USE_QUEUED_SPINLOCKS
113 !! 104 select GENERIC_TIME_VSYSCALL
114 config MIPS_GENERIC !! 105 select ARCH_CLOCKSOURCE_DATA
115 bool !! 106 select ARCH_HAS_PTE_SPECIAL
116 !! 107 select PCI_DOMAINS if PCI
117 config MACH_GENERIC_CORE !! 108 select ARCH_HAS_GIGANTIC_PAGE
118 bool !! 109 select HAVE_SOFTIRQ_ON_OWN_STACK
119 !! 110 select HAVE_SETUP_PER_CPU_AREA
120 config MACH_INGENIC !! 111 select NEED_PER_CPU_EMBED_FIRST_CHUNK
121 bool !! 112 select NEED_PER_CPU_PAGE_FIRST_CHUNK
122 select SYS_SUPPORTS_32BIT_KERNEL <<
123 select SYS_SUPPORTS_LITTLE_ENDIAN <<
124 select SYS_SUPPORTS_ZBOOT <<
125 select DMA_NONCOHERENT <<
126 select IRQ_MIPS_CPU <<
127 select PINCTRL <<
128 select GPIOLIB <<
129 select COMMON_CLK <<
130 select GENERIC_IRQ_CHIP <<
131 select BUILTIN_DTB if MIPS_NO_APPENDED <<
132 select USE_OF <<
133 select CPU_SUPPORTS_CPUFREQ <<
134 select MIPS_EXTERNAL_TIMER <<
135 <<
136 menu "Machine selection" <<
137 <<
138 choice <<
139 prompt "System type" <<
140 default MIPS_GENERIC_KERNEL <<
141 <<
142 config MIPS_GENERIC_KERNEL <<
143 bool "Generic board-agnostic MIPS kern <<
144 select MIPS_GENERIC <<
145 select BOOT_RAW <<
146 select BUILTIN_DTB <<
147 select CEVT_R4K <<
148 select CLKSRC_MIPS_GIC <<
149 select COMMON_CLK <<
150 select CPU_MIPSR2_IRQ_EI <<
151 select CPU_MIPSR2_IRQ_VI <<
152 select CSRC_R4K <<
153 select DMA_NONCOHERENT <<
154 select HAVE_PCI <<
155 select IRQ_MIPS_CPU <<
156 select MACH_GENERIC_CORE <<
157 select MIPS_AUTO_PFN_OFFSET <<
158 select MIPS_CPU_SCACHE <<
159 select MIPS_GIC <<
160 select MIPS_L1_CACHE_SHIFT_7 <<
161 select NO_EXCEPT_FILL <<
162 select PCI_DRIVERS_GENERIC <<
163 select SMP_UP if SMP <<
164 select SWAP_IO_SPACE <<
165 select SYS_HAS_CPU_MIPS32_R1 <<
166 select SYS_HAS_CPU_MIPS32_R2 <<
167 select SYS_HAS_CPU_MIPS32_R5 <<
168 select SYS_HAS_CPU_MIPS32_R6 <<
169 select SYS_HAS_CPU_MIPS64_R1 <<
170 select SYS_HAS_CPU_MIPS64_R2 <<
171 select SYS_HAS_CPU_MIPS64_R5 <<
172 select SYS_HAS_CPU_MIPS64_R6 <<
173 select SYS_SUPPORTS_32BIT_KERNEL <<
174 select SYS_SUPPORTS_64BIT_KERNEL <<
175 select SYS_SUPPORTS_BIG_ENDIAN <<
176 select SYS_SUPPORTS_HIGHMEM <<
177 select SYS_SUPPORTS_LITTLE_ENDIAN <<
178 select SYS_SUPPORTS_MICROMIPS <<
179 select SYS_SUPPORTS_MIPS16 <<
180 select SYS_SUPPORTS_MIPS_CPS <<
181 select SYS_SUPPORTS_MULTITHREADING <<
182 select SYS_SUPPORTS_RELOCATABLE <<
183 select SYS_SUPPORTS_SMARTMIPS <<
184 select SYS_SUPPORTS_ZBOOT <<
185 select UHI_BOOT <<
186 select USB_EHCI_BIG_ENDIAN_DESC if CPU <<
187 select USB_EHCI_BIG_ENDIAN_MMIO if CPU <<
188 select USB_OHCI_BIG_ENDIAN_DESC if CPU <<
189 select USB_OHCI_BIG_ENDIAN_MMIO if CPU <<
190 select USB_UHCI_BIG_ENDIAN_DESC if CPU <<
191 select USB_UHCI_BIG_ENDIAN_MMIO if CPU <<
192 select USE_OF <<
193 help <<
194 Select this to build a kernel which <<
195 generally using a flattened device t <<
196 using the boot protocol defined in t <<
197 Interface) specification. <<
198 <<
199 config MIPS_ALCHEMY <<
200 bool "Alchemy processor based machines <<
201 select PHYS_ADDR_T_64BIT <<
202 select CEVT_R4K <<
203 select CSRC_R4K <<
204 select IRQ_MIPS_CPU <<
205 select DMA_NONCOHERENT # Au10 <<
206 select MIPS_FIXUP_BIGPHYS_ADDR if PCI <<
207 select SYS_HAS_CPU_MIPS32_R1 <<
208 select SYS_SUPPORTS_32BIT_KERNEL <<
209 select SYS_SUPPORTS_APM_EMULATION <<
210 select GPIOLIB <<
211 select SYS_SUPPORTS_ZBOOT <<
212 select COMMON_CLK <<
213 <<
214 config ATH25 <<
215 bool "Atheros AR231x/AR531x SoC suppor <<
216 select CEVT_R4K <<
217 select CSRC_R4K <<
218 select DMA_NONCOHERENT <<
219 select IRQ_MIPS_CPU <<
220 select IRQ_DOMAIN <<
221 select SYS_HAS_CPU_MIPS32_R1 <<
222 select SYS_SUPPORTS_BIG_ENDIAN <<
223 select SYS_SUPPORTS_32BIT_KERNEL <<
224 select SYS_HAS_EARLY_PRINTK <<
225 help <<
226 Support for Atheros AR231x and Ather <<
227 <<
228 config ATH79 <<
229 bool "Atheros AR71XX/AR724X/AR913X bas <<
230 select ARCH_HAS_RESET_CONTROLLER <<
231 select BOOT_RAW <<
232 select CEVT_R4K <<
233 select CSRC_R4K <<
234 select DMA_NONCOHERENT <<
235 select GPIOLIB <<
236 select PINCTRL <<
237 select COMMON_CLK <<
238 select IRQ_MIPS_CPU <<
239 select SYS_HAS_CPU_MIPS32_R2 <<
240 select SYS_HAS_EARLY_PRINTK <<
241 select SYS_SUPPORTS_32BIT_KERNEL <<
242 select SYS_SUPPORTS_BIG_ENDIAN <<
243 select SYS_SUPPORTS_MIPS16 <<
244 select SYS_SUPPORTS_ZBOOT_UART_PROM <<
245 select USE_OF <<
246 select USB_EHCI_ROOT_HUB_TT if USB_EHC <<
247 help <<
248 Support for the Atheros AR71XX/AR724 <<
249 <<
250 config BMIPS_GENERIC <<
251 bool "Broadcom Generic BMIPS kernel" <<
252 select ARCH_HAS_RESET_CONTROLLER <<
253 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL <<
254 select BOOT_RAW <<
255 select NO_EXCEPT_FILL <<
256 select USE_OF <<
257 select CEVT_R4K <<
258 select CSRC_R4K <<
259 select SYNC_R4K <<
260 select COMMON_CLK <<
261 select BCM6345_L1_IRQ <<
262 select BCM7038_L1_IRQ <<
263 select BCM7120_L2_IRQ <<
264 select BRCMSTB_L2_IRQ <<
265 select IRQ_MIPS_CPU <<
266 select DMA_NONCOHERENT <<
267 select SYS_SUPPORTS_32BIT_KERNEL <<
268 select SYS_SUPPORTS_LITTLE_ENDIAN <<
269 select SYS_SUPPORTS_BIG_ENDIAN <<
270 select SYS_SUPPORTS_HIGHMEM <<
271 select SYS_HAS_CPU_BMIPS32_3300 <<
272 select SYS_HAS_CPU_BMIPS4350 <<
273 select SYS_HAS_CPU_BMIPS4380 <<
274 select SYS_HAS_CPU_BMIPS5000 <<
275 select SWAP_IO_SPACE <<
276 select USB_EHCI_BIG_ENDIAN_DESC if CPU <<
277 select USB_EHCI_BIG_ENDIAN_MMIO if CPU <<
278 select USB_OHCI_BIG_ENDIAN_DESC if CPU <<
279 select USB_OHCI_BIG_ENDIAN_MMIO if CPU <<
280 select HARDIRQS_SW_RESEND <<
281 select HAVE_PCI <<
282 select PCI_DRIVERS_GENERIC <<
283 select FW_CFE <<
284 help <<
285 Build a generic DT-based kernel imag <<
286 BCM33xx cable modem chips, BCM63xx D <<
287 box chips. Note that CONFIG_CPU_BIG <<
288 must be set appropriately for your b <<
289 <<
290 config BCM47XX <<
291 bool "Broadcom BCM47XX based boards" <<
292 select BOOT_RAW <<
293 select CEVT_R4K <<
294 select CSRC_R4K <<
295 select DMA_NONCOHERENT <<
296 select HAVE_PCI <<
297 select IRQ_MIPS_CPU <<
298 select SYS_HAS_CPU_MIPS32_R1 <<
299 select NO_EXCEPT_FILL <<
300 select SYS_SUPPORTS_32BIT_KERNEL <<
301 select SYS_SUPPORTS_LITTLE_ENDIAN <<
302 select SYS_SUPPORTS_MIPS16 <<
303 select SYS_SUPPORTS_ZBOOT <<
304 select SYS_HAS_EARLY_PRINTK <<
305 select USE_GENERIC_EARLY_PRINTK_8250 <<
306 select GPIOLIB <<
307 select LEDS_GPIO_REGISTER <<
308 select BCM47XX_NVRAM <<
309 select BCM47XX_SPROM <<
310 select BCM47XX_SSB if !BCM47XX_BCMA <<
311 help <<
312 Support for BCM47XX based boards <<
313 <<
314 config BCM63XX <<
315 bool "Broadcom BCM63XX based boards" <<
316 select BOOT_RAW <<
317 select CEVT_R4K <<
318 select CSRC_R4K <<
319 select SYNC_R4K <<
320 select DMA_NONCOHERENT <<
321 select IRQ_MIPS_CPU <<
322 select SYS_SUPPORTS_32BIT_KERNEL <<
323 select SYS_SUPPORTS_BIG_ENDIAN <<
324 select SYS_HAS_EARLY_PRINTK <<
325 select SYS_HAS_CPU_BMIPS32_3300 <<
326 select SYS_HAS_CPU_BMIPS4350 <<
327 select SYS_HAS_CPU_BMIPS4380 <<
328 select SWAP_IO_SPACE <<
329 select GPIOLIB <<
330 select MIPS_L1_CACHE_SHIFT_4 <<
331 select HAVE_LEGACY_CLK <<
332 help <<
333 Support for BCM63XX based boards <<
334 <<
335 config MIPS_COBALT <<
336 bool "Cobalt Server" <<
337 select CEVT_R4K <<
338 select CSRC_R4K <<
339 select CEVT_GT641XX <<
340 select DMA_NONCOHERENT <<
341 select FORCE_PCI <<
342 select I8253 <<
343 select I8259 <<
344 select IRQ_MIPS_CPU <<
345 select IRQ_GT641XX <<
346 select PCI_GT64XXX_PCI0 <<
347 select SYS_HAS_CPU_NEVADA <<
348 select SYS_HAS_EARLY_PRINTK <<
349 select SYS_SUPPORTS_32BIT_KERNEL <<
350 select SYS_SUPPORTS_64BIT_KERNEL <<
351 select SYS_SUPPORTS_LITTLE_ENDIAN <<
352 select USE_GENERIC_EARLY_PRINTK_8250 <<
353 <<
354 config MACH_DECSTATION <<
355 bool "DECstations" <<
356 select BOOT_ELF32 <<
357 select CEVT_DS1287 <<
358 select CEVT_R4K if CPU_R4X00 <<
359 select CSRC_IOASIC <<
360 select CSRC_R4K if CPU_R4X00 <<
361 select CPU_DADDI_WORKAROUNDS if 64BIT <<
362 select CPU_R4000_WORKAROUNDS if 64BIT <<
363 select CPU_R4400_WORKAROUNDS if 64BIT <<
364 select DMA_NONCOHERENT <<
365 select NO_IOPORT_MAP <<
366 select IRQ_MIPS_CPU <<
367 select SYS_HAS_CPU_R3000 <<
368 select SYS_HAS_CPU_R4X00 <<
369 select SYS_SUPPORTS_32BIT_KERNEL <<
370 select SYS_SUPPORTS_64BIT_KERNEL <<
371 select SYS_SUPPORTS_LITTLE_ENDIAN <<
372 select SYS_SUPPORTS_128HZ <<
373 select SYS_SUPPORTS_256HZ <<
374 select SYS_SUPPORTS_1024HZ <<
375 select MIPS_L1_CACHE_SHIFT_4 <<
376 help <<
377 This enables support for DEC's MIPS <<
378 see the Linux/MIPS FAQ on <http://ww <<
379 DECstation porting pages on <http:// <<
380 <<
381 If you have one of the following DEC <<
382 want to choose R4xx0 for the CPU Typ <<
383 <<
384 DECstation 5000/50 <<
385 DECstation 5000/150 <<
386 DECstation 5000/260 <<
387 DECsystem 5900/260 <<
388 <<
389 otherwise choose R3000. <<
390 <<
391 config MACH_JAZZ <<
392 bool "Jazz family of machines" <<
393 select ARC_MEMORY <<
394 select ARC_PROMLIB <<
395 select ARCH_MIGHT_HAVE_PC_PARPORT <<
396 select ARCH_MIGHT_HAVE_PC_SERIO <<
397 select FW_ARC <<
398 select FW_ARC32 <<
399 select ARCH_MAY_HAVE_PC_FDC <<
400 select CEVT_R4K <<
401 select CSRC_R4K <<
402 select DEFAULT_SGI_PARTITION if CPU_BI <<
403 select GENERIC_ISA_DMA <<
404 select HAVE_PCSPKR_PLATFORM <<
405 select IRQ_MIPS_CPU <<
406 select I8253 <<
407 select I8259 <<
408 select ISA <<
409 select SYS_HAS_CPU_R4X00 <<
410 select SYS_SUPPORTS_32BIT_KERNEL <<
411 select SYS_SUPPORTS_64BIT_KERNEL <<
412 select SYS_SUPPORTS_100HZ <<
413 select SYS_SUPPORTS_LITTLE_ENDIAN <<
414 help <<
415 This a family of machines based on t <<
416 used by several vendors to build RIS <<
417 Members include the Acer PICA, MIPS <<
418 Olivetti M700-10 workstations. <<
419 <<
420 config MACH_INGENIC_SOC <<
421 bool "Ingenic SoC based machines" <<
422 select MIPS_GENERIC <<
423 select MACH_INGENIC <<
424 select MACH_GENERIC_CORE <<
425 select SYS_SUPPORTS_ZBOOT_UART16550 <<
426 select CPU_SUPPORTS_CPUFREQ <<
427 select MIPS_EXTERNAL_TIMER <<
428 <<
429 config LANTIQ <<
430 bool "Lantiq based platforms" <<
431 select DMA_NONCOHERENT <<
432 select IRQ_MIPS_CPU <<
433 select CEVT_R4K <<
434 select CSRC_R4K <<
435 select NO_EXCEPT_FILL <<
436 select SYS_HAS_CPU_MIPS32_R1 <<
437 select SYS_HAS_CPU_MIPS32_R2 <<
438 select SYS_SUPPORTS_BIG_ENDIAN <<
439 select SYS_SUPPORTS_32BIT_KERNEL <<
440 select SYS_SUPPORTS_MIPS16 <<
441 select SYS_SUPPORTS_MULTITHREADING <<
442 select SYS_SUPPORTS_VPE_LOADER <<
443 select SYS_HAS_EARLY_PRINTK <<
444 select GPIOLIB <<
445 select SWAP_IO_SPACE <<
446 select BOOT_RAW <<
447 select HAVE_LEGACY_CLK <<
448 select USE_OF <<
449 select PINCTRL <<
450 select PINCTRL_LANTIQ <<
451 select ARCH_HAS_RESET_CONTROLLER <<
452 select RESET_CONTROLLER <<
453 <<
454 config MACH_LOONGSON32 <<
455 bool "Loongson 32-bit family of machin <<
456 select SYS_SUPPORTS_ZBOOT <<
457 help <<
458 This enables support for the Loongso <<
459 <<
460 Loongson-1 is a family of 32-bit MIP <<
461 the Institute of Computing Technolog <<
462 Sciences (CAS). <<
463 <<
464 config MACH_LOONGSON2EF <<
465 bool "Loongson-2E/F family of machines <<
466 select SYS_SUPPORTS_ZBOOT <<
467 help <<
468 This enables the support of early Lo <<
469 <<
470 config MACH_LOONGSON64 <<
471 bool "Loongson 64-bit family of machin <<
472 select ARCH_DMA_DEFAULT_COHERENT <<
473 select ARCH_SPARSEMEM_ENABLE <<
474 select ARCH_MIGHT_HAVE_PC_PARPORT <<
475 select ARCH_MIGHT_HAVE_PC_SERIO <<
476 select GENERIC_ISA_DMA_SUPPORT_BROKEN <<
477 select BOOT_ELF32 <<
478 select BOARD_SCACHE <<
479 select CSRC_R4K <<
480 select CEVT_R4K <<
481 select SYNC_R4K <<
482 select FORCE_PCI <<
483 select ISA <<
484 select I8259 <<
485 select IRQ_MIPS_CPU <<
486 select NO_EXCEPT_FILL <<
487 select NR_CPUS_DEFAULT_64 <<
488 select USE_GENERIC_EARLY_PRINTK_8250 <<
489 select PCI_DRIVERS_GENERIC <<
490 select SYS_HAS_CPU_LOONGSON64 <<
491 select SYS_HAS_EARLY_PRINTK <<
492 select SYS_SUPPORTS_SMP <<
493 select SYS_SUPPORTS_HOTPLUG_CPU <<
494 select SYS_SUPPORTS_NUMA <<
495 select SYS_SUPPORTS_64BIT_KERNEL <<
496 select SYS_SUPPORTS_HIGHMEM <<
497 select SYS_SUPPORTS_LITTLE_ENDIAN <<
498 select SYS_SUPPORTS_ZBOOT <<
499 select SYS_SUPPORTS_RELOCATABLE <<
500 select ZONE_DMA32 <<
501 select COMMON_CLK <<
502 select USE_OF <<
503 select BUILTIN_DTB <<
504 select PCI_HOST_GENERIC <<
505 help <<
506 This enables the support of Loongson <<
507 <<
508 Loongson-2 and Loongson-3 are 64-bit <<
509 GS264/GS464/GS464E/GS464V microarchi <<
510 and Loongson-2F which will be remove <<
511 of Computing Technology (ICT), Chine <<
512 <<
513 config MIPS_MALTA <<
514 bool "MIPS Malta board" <<
515 select ARCH_MAY_HAVE_PC_FDC <<
516 select ARCH_MIGHT_HAVE_PC_PARPORT <<
517 select ARCH_MIGHT_HAVE_PC_SERIO <<
518 select BOOT_ELF32 <<
519 select BOOT_RAW <<
520 select BUILTIN_DTB <<
521 select CEVT_R4K <<
522 select CLKSRC_MIPS_GIC <<
523 select COMMON_CLK <<
524 select CSRC_R4K <<
525 select DMA_NONCOHERENT <<
526 select GENERIC_ISA_DMA <<
527 select HAVE_PCSPKR_PLATFORM <<
528 select HAVE_PCI <<
529 select I8253 <<
530 select I8259 <<
531 select IRQ_MIPS_CPU <<
532 select MIPS_BONITO64 <<
533 select MIPS_CPU_SCACHE <<
534 select MIPS_GIC <<
535 select MIPS_L1_CACHE_SHIFT_6 <<
536 select MIPS_MSC <<
537 select PCI_GT64XXX_PCI0 <<
538 select SMP_UP if SMP <<
539 select SWAP_IO_SPACE <<
540 select SYS_HAS_CPU_MIPS32_R1 <<
541 select SYS_HAS_CPU_MIPS32_R2 <<
542 select SYS_HAS_CPU_MIPS32_R3_5 <<
543 select SYS_HAS_CPU_MIPS32_R5 <<
544 select SYS_HAS_CPU_MIPS32_R6 <<
545 select SYS_HAS_CPU_MIPS64_R1 <<
546 select SYS_HAS_CPU_MIPS64_R2 <<
547 select SYS_HAS_CPU_MIPS64_R6 <<
548 select SYS_HAS_CPU_NEVADA <<
549 select SYS_HAS_CPU_RM7000 <<
550 select SYS_SUPPORTS_32BIT_KERNEL <<
551 select SYS_SUPPORTS_64BIT_KERNEL <<
552 select SYS_SUPPORTS_BIG_ENDIAN <<
553 select SYS_SUPPORTS_HIGHMEM <<
554 select SYS_SUPPORTS_LITTLE_ENDIAN <<
555 select SYS_SUPPORTS_MICROMIPS <<
556 select SYS_SUPPORTS_MIPS16 <<
557 select SYS_SUPPORTS_MIPS_CPS <<
558 select SYS_SUPPORTS_MULTITHREADING <<
559 select SYS_SUPPORTS_RELOCATABLE <<
560 select SYS_SUPPORTS_SMARTMIPS <<
561 select SYS_SUPPORTS_VPE_LOADER <<
562 select SYS_SUPPORTS_ZBOOT <<
563 select USE_OF <<
564 select WAR_ICACHE_REFILLS <<
565 select ZONE_DMA32 if 64BIT <<
566 help <<
567 This enables support for the MIPS Te <<
568 board. <<
569 <<
570 config MACH_PIC32 <<
571 bool "Microchip PIC32 Family" <<
572 help <<
573 This enables support for the Microch <<
574 <<
575 Microchip PIC32 is a family of gener <<
576 microcontrollers. <<
577 <<
578 config EYEQ <<
579 bool "Mobileye EyeQ SoC" <<
580 select MACH_GENERIC_CORE <<
581 select ARM_AMBA <<
582 select PHYSICAL_START_BOOL <<
583 select ARCH_SPARSEMEM_DEFAULT if 64BIT <<
584 select BOOT_RAW <<
585 select BUILTIN_DTB <<
586 select CEVT_R4K <<
587 select CLKSRC_MIPS_GIC <<
588 select COMMON_CLK <<
589 select CPU_MIPSR2_IRQ_EI <<
590 select CPU_MIPSR2_IRQ_VI <<
591 select CSRC_R4K <<
592 select DMA_NONCOHERENT <<
593 select HAVE_PCI <<
594 select IRQ_MIPS_CPU <<
595 select MIPS_AUTO_PFN_OFFSET <<
596 select MIPS_CPU_SCACHE <<
597 select MIPS_GIC <<
598 select MIPS_L1_CACHE_SHIFT_7 <<
599 select PCI_DRIVERS_GENERIC <<
600 select SMP_UP if SMP <<
601 select SWAP_IO_SPACE <<
602 select SYS_HAS_CPU_MIPS64_R6 <<
603 select SYS_SUPPORTS_64BIT_KERNEL <<
604 select SYS_SUPPORTS_HIGHMEM <<
605 select SYS_SUPPORTS_LITTLE_ENDIAN <<
606 select SYS_SUPPORTS_MIPS_CPS <<
607 select SYS_SUPPORTS_RELOCATABLE <<
608 select SYS_SUPPORTS_ZBOOT <<
609 select UHI_BOOT <<
610 select USB_EHCI_BIG_ENDIAN_DESC if CPU <<
611 select USB_EHCI_BIG_ENDIAN_MMIO if CPU <<
612 select USB_OHCI_BIG_ENDIAN_DESC if CPU <<
613 select USB_OHCI_BIG_ENDIAN_MMIO if CPU <<
614 select USB_UHCI_BIG_ENDIAN_DESC if CPU <<
615 select USB_UHCI_BIG_ENDIAN_MMIO if CPU <<
616 select USE_OF <<
617 help <<
618 Select this to build a kernel suppor <<
619 <<
620 bool <<
621 <<
622 config MACH_NINTENDO64 <<
623 bool "Nintendo 64 console" <<
624 select CEVT_R4K <<
625 select CSRC_R4K <<
626 select SYS_HAS_CPU_R4300 <<
627 select SYS_SUPPORTS_BIG_ENDIAN <<
628 select SYS_SUPPORTS_ZBOOT <<
629 select SYS_SUPPORTS_32BIT_KERNEL <<
630 select SYS_SUPPORTS_64BIT_KERNEL <<
631 select DMA_NONCOHERENT <<
632 select IRQ_MIPS_CPU <<
633 <<
634 config RALINK <<
635 bool "Ralink based machines" <<
636 select CEVT_R4K <<
637 select COMMON_CLK <<
638 select CSRC_R4K <<
639 select BOOT_RAW <<
640 select DMA_NONCOHERENT <<
641 select IRQ_MIPS_CPU <<
642 select USE_OF <<
643 select SYS_HAS_CPU_MIPS32_R2 <<
644 select SYS_SUPPORTS_32BIT_KERNEL <<
645 select SYS_SUPPORTS_LITTLE_ENDIAN <<
646 select SYS_SUPPORTS_MIPS16 <<
647 select SYS_SUPPORTS_ZBOOT <<
648 select SYS_HAS_EARLY_PRINTK <<
649 select ARCH_HAS_RESET_CONTROLLER <<
650 select RESET_CONTROLLER <<
651 <<
652 config MACH_REALTEK_RTL <<
653 bool "Realtek RTL838x/RTL839x based ma <<
654 select MIPS_GENERIC <<
655 select MACH_GENERIC_CORE <<
656 select DMA_NONCOHERENT <<
657 select IRQ_MIPS_CPU <<
658 select CSRC_R4K <<
659 select CEVT_R4K <<
660 select SYS_HAS_CPU_MIPS32_R1 <<
661 select SYS_HAS_CPU_MIPS32_R2 <<
662 select SYS_SUPPORTS_BIG_ENDIAN <<
663 select SYS_SUPPORTS_32BIT_KERNEL <<
664 select SYS_SUPPORTS_MIPS16 <<
665 select SYS_SUPPORTS_MULTITHREADING <<
666 select SYS_SUPPORTS_VPE_LOADER <<
667 select BOOT_RAW <<
668 select PINCTRL <<
669 select USE_OF <<
670 select REALTEK_OTTO_TIMER <<
671 <<
672 config SGI_IP22 <<
673 bool "SGI IP22 (Indy/Indigo2)" <<
674 select ARC_MEMORY <<
675 select ARC_PROMLIB <<
676 select FW_ARC <<
677 select FW_ARC32 <<
678 select ARCH_MIGHT_HAVE_PC_SERIO <<
679 select BOOT_ELF32 <<
680 select CEVT_R4K <<
681 select CSRC_R4K <<
682 select DEFAULT_SGI_PARTITION <<
683 select DMA_NONCOHERENT <<
684 select HAVE_EISA <<
685 select I8253 <<
686 select I8259 <<
687 select IP22_CPU_SCACHE <<
688 select IRQ_MIPS_CPU <<
689 select GENERIC_ISA_DMA_SUPPORT_BROKEN <<
690 select SGI_HAS_I8042 <<
691 select SGI_HAS_INDYDOG <<
692 select SGI_HAS_HAL2 <<
693 select SGI_HAS_SEEQ <<
694 select SGI_HAS_WD93 <<
695 select SGI_HAS_ZILOG <<
696 select SWAP_IO_SPACE <<
697 select SYS_HAS_CPU_R4X00 <<
698 select SYS_HAS_CPU_R5000 <<
699 select SYS_HAS_EARLY_PRINTK <<
700 select SYS_SUPPORTS_32BIT_KERNEL <<
701 select SYS_SUPPORTS_64BIT_KERNEL <<
702 select SYS_SUPPORTS_BIG_ENDIAN <<
703 select WAR_R4600_V1_INDEX_ICACHEOP <<
704 select WAR_R4600_V1_HIT_CACHEOP <<
705 select WAR_R4600_V2_HIT_CACHEOP <<
706 select MIPS_L1_CACHE_SHIFT_7 <<
707 help <<
708 This are the SGI Indy, Challenge S a <<
709 OEM variants like the Tandem CMN B00 <<
710 that runs on these, say Y here. <<
711 <<
712 config SGI_IP27 <<
713 bool "SGI IP27 (Origin200/2000)" <<
714 select ARCH_HAS_PHYS_TO_DMA <<
715 select ARCH_SPARSEMEM_ENABLE <<
716 select FW_ARC <<
717 select FW_ARC64 <<
718 select ARC_CMDLINE_ONLY <<
719 select BOOT_ELF64 <<
720 select DEFAULT_SGI_PARTITION <<
721 select FORCE_PCI <<
722 select SYS_HAS_EARLY_PRINTK <<
723 select HAVE_PCI <<
724 select IRQ_MIPS_CPU <<
725 select IRQ_DOMAIN_HIERARCHY <<
726 select NR_CPUS_DEFAULT_64 <<
727 select PCI_DRIVERS_GENERIC <<
728 select PCI_XTALK_BRIDGE <<
729 select SYS_HAS_CPU_R10000 <<
730 select SYS_SUPPORTS_64BIT_KERNEL <<
731 select SYS_SUPPORTS_BIG_ENDIAN <<
732 select SYS_SUPPORTS_NUMA <<
733 select SYS_SUPPORTS_SMP <<
734 select WAR_R10000_LLSC <<
735 select MIPS_L1_CACHE_SHIFT_7 <<
736 select NUMA <<
737 help <<
738 This are the SGI Origin 200, Origin <<
739 workstations. To compile a Linux ke <<
740 here. <<
741 <<
742 config SGI_IP28 <<
743 bool "SGI IP28 (Indigo2 R10k)" <<
744 select ARC_MEMORY <<
745 select ARC_PROMLIB <<
746 select FW_ARC <<
747 select FW_ARC64 <<
748 select ARCH_MIGHT_HAVE_PC_SERIO <<
749 select BOOT_ELF64 <<
750 select CEVT_R4K <<
751 select CSRC_R4K <<
752 select DEFAULT_SGI_PARTITION <<
753 select DMA_NONCOHERENT <<
754 select GENERIC_ISA_DMA_SUPPORT_BROKEN <<
755 select IRQ_MIPS_CPU <<
756 select HAVE_EISA <<
757 select I8253 <<
758 select I8259 <<
759 select SGI_HAS_I8042 <<
760 select SGI_HAS_INDYDOG <<
761 select SGI_HAS_HAL2 <<
762 select SGI_HAS_SEEQ <<
763 select SGI_HAS_WD93 <<
764 select SGI_HAS_ZILOG <<
765 select SWAP_IO_SPACE <<
766 select SYS_HAS_CPU_R10000 <<
767 select SYS_HAS_EARLY_PRINTK <<
768 select SYS_SUPPORTS_64BIT_KERNEL <<
769 select SYS_SUPPORTS_BIG_ENDIAN <<
770 select WAR_R10000_LLSC <<
771 select MIPS_L1_CACHE_SHIFT_7 <<
772 help <<
773 This is the SGI Indigo2 with R10000 <<
774 kernel that runs on these, say Y her <<
775 <<
776 config SGI_IP30 <<
777 bool "SGI IP30 (Octane/Octane2)" <<
778 select ARCH_HAS_PHYS_TO_DMA <<
779 select FW_ARC <<
780 select FW_ARC64 <<
781 select BOOT_ELF64 <<
782 select CEVT_R4K <<
783 select CSRC_R4K <<
784 select FORCE_PCI <<
785 select SYNC_R4K if SMP <<
786 select ZONE_DMA32 <<
787 select HAVE_PCI <<
788 select IRQ_MIPS_CPU <<
789 select IRQ_DOMAIN_HIERARCHY <<
790 select PCI_DRIVERS_GENERIC <<
791 select PCI_XTALK_BRIDGE <<
792 select SYS_HAS_EARLY_PRINTK <<
793 select SYS_HAS_CPU_R10000 <<
794 select SYS_SUPPORTS_64BIT_KERNEL <<
795 select SYS_SUPPORTS_BIG_ENDIAN <<
796 select SYS_SUPPORTS_SMP <<
797 select WAR_R10000_LLSC <<
798 select MIPS_L1_CACHE_SHIFT_7 <<
799 select ARC_MEMORY <<
800 help <<
801 These are the SGI Octane and Octane2 <<
802 compile a Linux kernel that runs on <<
803 <<
804 config SGI_IP32 <<
805 bool "SGI IP32 (O2)" <<
806 select ARC_MEMORY <<
807 select ARC_PROMLIB <<
808 select ARCH_HAS_PHYS_TO_DMA <<
809 select FW_ARC <<
810 select FW_ARC32 <<
811 select BOOT_ELF32 <<
812 select CEVT_R4K <<
813 select CSRC_R4K <<
814 select DMA_NONCOHERENT <<
815 select HAVE_PCI <<
816 select IRQ_MIPS_CPU <<
817 select R5000_CPU_SCACHE <<
818 select RM7000_CPU_SCACHE <<
819 select SYS_HAS_CPU_R5000 <<
820 select SYS_HAS_CPU_R10000 if BROKEN <<
821 select SYS_HAS_CPU_RM7000 <<
822 select SYS_HAS_CPU_NEVADA <<
823 select SYS_SUPPORTS_64BIT_KERNEL <<
824 select SYS_SUPPORTS_BIG_ENDIAN <<
825 select WAR_ICACHE_REFILLS <<
826 help <<
827 If you want this kernel to run on SG <<
828 <<
829 config SIBYTE_CRHONE <<
830 bool "Sibyte BCM91125C-CRhone" <<
831 select BOOT_ELF32 <<
832 select SIBYTE_BCM1125 <<
833 select SWAP_IO_SPACE <<
834 select SYS_HAS_CPU_SB1 <<
835 select SYS_SUPPORTS_BIG_ENDIAN <<
836 select SYS_SUPPORTS_HIGHMEM <<
837 select SYS_SUPPORTS_LITTLE_ENDIAN <<
838 <<
839 config SIBYTE_RHONE <<
840 bool "Sibyte BCM91125E-Rhone" <<
841 select BOOT_ELF32 <<
842 select SIBYTE_SB1250 <<
843 select SWAP_IO_SPACE <<
844 select SYS_HAS_CPU_SB1 <<
845 select SYS_SUPPORTS_BIG_ENDIAN <<
846 select SYS_SUPPORTS_LITTLE_ENDIAN <<
847 <<
848 config SIBYTE_SWARM <<
849 bool "Sibyte BCM91250A-SWARM" <<
850 select BOOT_ELF32 <<
851 select HAVE_PATA_PLATFORM <<
852 select SIBYTE_SB1250 <<
853 select SWAP_IO_SPACE <<
854 select SYS_HAS_CPU_SB1 <<
855 select SYS_SUPPORTS_BIG_ENDIAN <<
856 select SYS_SUPPORTS_HIGHMEM <<
857 select SYS_SUPPORTS_LITTLE_ENDIAN <<
858 select ZONE_DMA32 if 64BIT <<
859 select SWIOTLB if ARCH_DMA_ADDR_T_64BI <<
860 <<
861 config SIBYTE_LITTLESUR <<
862 bool "Sibyte BCM91250C2-LittleSur" <<
863 select BOOT_ELF32 <<
864 select HAVE_PATA_PLATFORM <<
865 select SIBYTE_SB1250 <<
866 select SWAP_IO_SPACE <<
867 select SYS_HAS_CPU_SB1 <<
868 select SYS_SUPPORTS_BIG_ENDIAN <<
869 select SYS_SUPPORTS_HIGHMEM <<
870 select SYS_SUPPORTS_LITTLE_ENDIAN <<
871 select ZONE_DMA32 if 64BIT <<
872 <<
873 config SIBYTE_SENTOSA <<
874 bool "Sibyte BCM91250E-Sentosa" <<
875 select BOOT_ELF32 <<
876 select SIBYTE_SB1250 <<
877 select SWAP_IO_SPACE <<
878 select SYS_HAS_CPU_SB1 <<
879 select SYS_SUPPORTS_BIG_ENDIAN <<
880 select SYS_SUPPORTS_LITTLE_ENDIAN <<
881 select SWIOTLB if ARCH_DMA_ADDR_T_64BI <<
882 <<
883 config SIBYTE_BIGSUR <<
884 bool "Sibyte BCM91480B-BigSur" <<
885 select BOOT_ELF32 <<
886 select NR_CPUS_DEFAULT_4 <<
887 select SIBYTE_BCM1x80 <<
888 select SWAP_IO_SPACE <<
889 select SYS_HAS_CPU_SB1 <<
890 select SYS_SUPPORTS_BIG_ENDIAN <<
891 select SYS_SUPPORTS_HIGHMEM <<
892 select SYS_SUPPORTS_LITTLE_ENDIAN <<
893 select ZONE_DMA32 if 64BIT <<
894 select SWIOTLB if ARCH_DMA_ADDR_T_64BI <<
895 <<
896 config SNI_RM <<
897 bool "SNI RM200/300/400" <<
898 select ARC_MEMORY <<
899 select ARC_PROMLIB <<
900 select FW_ARC if CPU_LITTLE_ENDIAN <<
901 select FW_ARC32 if CPU_LITTLE_ENDIAN <<
902 select FW_SNIPROM if CPU_BIG_ENDIAN <<
903 select ARCH_MAY_HAVE_PC_FDC <<
904 select ARCH_MIGHT_HAVE_PC_PARPORT <<
905 select ARCH_MIGHT_HAVE_PC_SERIO <<
906 select BOOT_ELF32 <<
907 select CEVT_R4K <<
908 select CSRC_R4K <<
909 select DEFAULT_SGI_PARTITION if CPU_BI <<
910 select DMA_NONCOHERENT <<
911 select GENERIC_ISA_DMA <<
912 select HAVE_EISA <<
913 select HAVE_PCSPKR_PLATFORM <<
914 select HAVE_PCI <<
915 select IRQ_MIPS_CPU <<
916 select I8253 <<
917 select I8259 <<
918 select ISA <<
919 select MIPS_L1_CACHE_SHIFT_6 <<
920 select SWAP_IO_SPACE if CPU_BIG_ENDIAN <<
921 select SYS_HAS_CPU_R4X00 <<
922 select SYS_HAS_CPU_R5000 <<
923 select SYS_HAS_CPU_R10000 <<
924 select R5000_CPU_SCACHE <<
925 select SYS_HAS_EARLY_PRINTK <<
926 select SYS_SUPPORTS_32BIT_KERNEL <<
927 select SYS_SUPPORTS_64BIT_KERNEL <<
928 select SYS_SUPPORTS_BIG_ENDIAN <<
929 select SYS_SUPPORTS_HIGHMEM <<
930 select SYS_SUPPORTS_LITTLE_ENDIAN <<
931 select WAR_R4600_V2_HIT_CACHEOP <<
932 help <<
933 The SNI RM200/300/400 are MIPS-based <<
934 Siemens Nixdorf Informationssysteme <<
935 Technology and now in turn merged wi <<
936 support this machine type. <<
937 <<
938 config MACH_TX49XX <<
939 bool "Toshiba TX49 series based machin <<
940 select WAR_TX49XX_ICACHE_INDEX_INV <<
941 <<
942 config MIKROTIK_RB532 <<
943 bool "Mikrotik RB532 boards" <<
944 select CEVT_R4K <<
945 select CSRC_R4K <<
946 select DMA_NONCOHERENT <<
947 select HAVE_PCI <<
948 select IRQ_MIPS_CPU <<
949 select SYS_HAS_CPU_MIPS32_R1 <<
950 select SYS_SUPPORTS_32BIT_KERNEL <<
951 select SYS_SUPPORTS_LITTLE_ENDIAN <<
952 select SWAP_IO_SPACE <<
953 select BOOT_RAW <<
954 select GPIOLIB <<
955 select MIPS_L1_CACHE_SHIFT_4 <<
956 help <<
957 Support the Mikrotik(tm) RouterBoard <<
958 based on the IDT RC32434 SoC. <<
959 <<
960 config CAVIUM_OCTEON_SOC <<
961 bool "Cavium Networks Octeon SoC based <<
962 select CEVT_R4K <<
963 select ARCH_HAS_PHYS_TO_DMA <<
964 select HAVE_RAPIDIO <<
965 select PHYS_ADDR_T_64BIT <<
966 select SYS_SUPPORTS_64BIT_KERNEL <<
967 select SYS_SUPPORTS_BIG_ENDIAN <<
968 select EDAC_SUPPORT <<
969 select EDAC_ATOMIC_SCRUB <<
970 select SYS_SUPPORTS_LITTLE_ENDIAN <<
971 select SYS_SUPPORTS_HOTPLUG_CPU if CPU <<
972 select SYS_HAS_EARLY_PRINTK <<
973 select SYS_HAS_CPU_CAVIUM_OCTEON <<
974 select HAVE_PCI <<
975 select HAVE_PLAT_DELAY <<
976 select HAVE_PLAT_FW_INIT_CMDLINE <<
977 select HAVE_PLAT_MEMCPY <<
978 select ZONE_DMA32 <<
979 select GPIOLIB <<
980 select USE_OF <<
981 select ARCH_SPARSEMEM_ENABLE <<
982 select SYS_SUPPORTS_SMP <<
983 select NR_CPUS_DEFAULT_64 <<
984 select MIPS_NR_CPU_NR_MAP_1024 <<
985 select BUILTIN_DTB <<
986 select MTD <<
987 select MTD_COMPLEX_MAPPINGS <<
988 select SWIOTLB <<
989 select SYS_SUPPORTS_RELOCATABLE <<
990 help <<
991 This option supports all of the Octe <<
992 Networks. It builds a kernel that dy <<
993 CPU type and supports all known boar <<
994 Some of the supported boards are: <<
995 EBT3000 <<
996 EBH3000 <<
997 EBH3100 <<
998 Thunder <<
999 Kodama <<
1000 Hikari <<
1001 Say Y here for most Octeon referenc <<
1002 <<
1003 endchoice <<
1004 <<
1005 config FIT_IMAGE_FDT_EPM5 <<
1006 bool "Include FDT for Mobileye EyeQ5 <<
1007 depends on MACH_EYEQ5 <<
1008 default n <<
1009 help <<
1010 Enable this to include the FDT for <<
1011 from Mobileye in the FIT kernel ima <<
1012 This requires u-boot on the platfor <<
1013 <<
1014 source "arch/mips/alchemy/Kconfig" <<
1015 source "arch/mips/ath25/Kconfig" <<
1016 source "arch/mips/ath79/Kconfig" <<
1017 source "arch/mips/bcm47xx/Kconfig" <<
1018 source "arch/mips/bcm63xx/Kconfig" <<
1019 source "arch/mips/bmips/Kconfig" <<
1020 source "arch/mips/generic/Kconfig" <<
1021 source "arch/mips/ingenic/Kconfig" <<
1022 source "arch/mips/jazz/Kconfig" <<
1023 source "arch/mips/lantiq/Kconfig" <<
1024 source "arch/mips/mobileye/Kconfig" <<
1025 source "arch/mips/pic32/Kconfig" <<
1026 source "arch/mips/ralink/Kconfig" <<
1027 source "arch/mips/sgi-ip27/Kconfig" <<
1028 source "arch/mips/sibyte/Kconfig" <<
1029 source "arch/mips/txx9/Kconfig" <<
1030 source "arch/mips/cavium-octeon/Kconfig" <<
1031 source "arch/mips/loongson2ef/Kconfig" <<
1032 source "arch/mips/loongson32/Kconfig" <<
1033 source "arch/mips/loongson64/Kconfig" <<
1034 <<
1035 endmenu <<
1036 <<
1037 config GENERIC_HWEIGHT <<
1038 bool <<
1039 default y <<
1040 <<
1041 config GENERIC_CALIBRATE_DELAY <<
1042 bool <<
1043 default y <<
1044 <<
1045 config SCHED_OMIT_FRAME_POINTER <<
1046 bool <<
1047 default y <<
1048 <<
1049 # <<
1050 # Select some configuration options automatic <<
1051 # <<
1052 config FW_ARC <<
1053 bool <<
1054 <<
1055 config ARCH_MAY_HAVE_PC_FDC <<
1056 bool <<
1057 <<
1058 config BOOT_RAW <<
1059 bool <<
1060 <<
1061 config CEVT_BCM1480 <<
1062 bool <<
1063 <<
1064 config CEVT_DS1287 <<
1065 bool <<
1066 <<
1067 config CEVT_GT641XX <<
1068 bool <<
1069 <<
1070 config CEVT_R4K <<
1071 bool <<
1072 <<
1073 config CEVT_SB1250 <<
1074 bool <<
1075 <<
1076 config CEVT_TXX9 <<
1077 bool <<
1078 <<
1079 config CSRC_BCM1480 <<
1080 bool <<
1081 <<
1082 config CSRC_IOASIC <<
1083 bool <<
1084 <<
1085 config CSRC_R4K <<
1086 select CLOCKSOURCE_WATCHDOG if CPU_FR <<
1087 select HAVE_UNSTABLE_SCHED_CLOCK if S <<
1088 bool <<
1089 <<
1090 config CSRC_SB1250 <<
1091 bool <<
1092 <<
1093 config MIPS_CLOCK_VSYSCALL <<
1094 def_bool CSRC_R4K || CLKSRC_MIPS_GIC <<
1095 <<
1096 config GPIO_TXX9 <<
1097 select GPIOLIB <<
1098 bool <<
1099 <<
1100 config FW_CFE <<
1101 bool <<
1102 113
1103 config ARCH_SUPPORTS_UPROBES !! 114 config ARCH_PROC_KCORE_TEXT
1104 def_bool y 115 def_bool y
1105 116
1106 config DMA_NONCOHERENT <<
1107 bool <<
1108 # <<
1109 # MIPS allows mixing "slightly differ <<
1110 # Attribute bits. It is believed tha <<
1111 # KSEG1 and the implementation specif <<
1112 # by pgprot_writcombine can be mixed, <<
1113 # significant advantages. <<
1114 # <<
1115 select ARCH_HAS_SETUP_DMA_OPS <<
1116 select ARCH_HAS_DMA_WRITE_COMBINE <<
1117 select ARCH_HAS_DMA_PREP_COHERENT <<
1118 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
1119 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
1120 select ARCH_HAS_DMA_SET_UNCACHED <<
1121 select DMA_NONCOHERENT_MMAP <<
1122 select NEED_DMA_MAP_STATE <<
1123 <<
1124 config SYS_HAS_EARLY_PRINTK <<
1125 bool <<
1126 <<
1127 config SYS_SUPPORTS_HOTPLUG_CPU <<
1128 bool <<
1129 <<
1130 config MIPS_BONITO64 <<
1131 bool <<
1132 <<
1133 config MIPS_MSC <<
1134 bool <<
1135 <<
1136 config SYNC_R4K <<
1137 bool <<
1138 <<
1139 config NO_IOPORT_MAP <<
1140 def_bool n <<
1141 <<
1142 config GENERIC_CSUM <<
1143 def_bool CPU_NO_LOAD_STORE_LR <<
1144 <<
1145 config GENERIC_ISA_DMA <<
1146 bool <<
1147 select ZONE_DMA if GENERIC_ISA_DMA_SU <<
1148 select ISA_DMA_API <<
1149 <<
1150 config GENERIC_ISA_DMA_SUPPORT_BROKEN <<
1151 bool <<
1152 select GENERIC_ISA_DMA <<
1153 <<
1154 config HAVE_PLAT_DELAY <<
1155 bool <<
1156 <<
1157 config HAVE_PLAT_FW_INIT_CMDLINE <<
1158 bool <<
1159 <<
1160 config HAVE_PLAT_MEMCPY <<
1161 bool <<
1162 <<
1163 config ISA_DMA_API <<
1164 bool <<
1165 <<
1166 config SYS_SUPPORTS_RELOCATABLE <<
1167 bool <<
1168 help <<
1169 Selected if the platform supports r <<
1170 The platform must provide plat_get_ <<
1171 to allow access to command line and <<
1172 <<
1173 # <<
1174 # Endianness selection. Sufficiently obscure <<
1175 # answer,so we try hard to limit the availabl <<
1176 # choice statement should be more obvious to <<
1177 # <<
1178 choice <<
1179 prompt "Endianness selection" <<
1180 help <<
1181 Some MIPS machines can be configure <<
1182 byte order. These modes require dif <<
1183 Linux distribution. In general the <<
1184 particular system but some systems <<
1185 one or the other endianness. <<
1186 <<
1187 config CPU_BIG_ENDIAN 117 config CPU_BIG_ENDIAN
1188 bool "Big endian" !! 118 def_bool y
1189 depends on SYS_SUPPORTS_BIG_ENDIAN <<
1190 <<
1191 config CPU_LITTLE_ENDIAN <<
1192 bool "Little endian" <<
1193 depends on SYS_SUPPORTS_LITTLE_ENDIAN <<
1194 <<
1195 endchoice <<
1196 <<
1197 config EXPORT_UASM <<
1198 bool <<
1199 <<
1200 config SYS_SUPPORTS_APM_EMULATION <<
1201 bool <<
1202 <<
1203 config SYS_SUPPORTS_BIG_ENDIAN <<
1204 bool <<
1205 <<
1206 config SYS_SUPPORTS_LITTLE_ENDIAN <<
1207 bool <<
1208 <<
1209 config MIPS_HUGE_TLB_SUPPORT <<
1210 def_bool HUGETLB_PAGE || TRANSPARENT_ <<
1211 <<
1212 config IRQ_TXX9 <<
1213 bool <<
1214 <<
1215 config IRQ_GT641XX <<
1216 bool <<
1217 <<
1218 config PCI_GT64XXX_PCI0 <<
1219 bool <<
1220 <<
1221 config PCI_XTALK_BRIDGE <<
1222 bool <<
1223 119
1224 config NO_EXCEPT_FILL !! 120 config STACKTRACE_SUPPORT
1225 bool 121 bool
>> 122 default y if SPARC64
1226 123
1227 config MIPS_SPRAM !! 124 config LOCKDEP_SUPPORT
1228 bool 125 bool
>> 126 default y if SPARC64
1229 127
1230 config SWAP_IO_SPACE !! 128 config ARCH_HIBERNATION_POSSIBLE
1231 bool !! 129 def_bool y if SPARC64
1232 130
1233 config SGI_HAS_INDYDOG !! 131 config AUDIT_ARCH
1234 bool 132 bool
>> 133 default y
1235 134
1236 config SGI_HAS_HAL2 !! 135 config MMU
1237 bool 136 bool
>> 137 default y
1238 138
1239 config SGI_HAS_SEEQ !! 139 config HIGHMEM
1240 bool 140 bool
>> 141 default y if SPARC32
>> 142 select KMAP_LOCAL
1241 143
1242 config SGI_HAS_WD93 !! 144 config PGTABLE_LEVELS
1243 bool !! 145 default 4 if 64BIT
>> 146 default 3
1244 147
1245 config SGI_HAS_ZILOG !! 148 config ARCH_SUPPORTS_UPROBES
1246 bool !! 149 def_bool y if SPARC64
1247 150
1248 config SGI_HAS_I8042 !! 151 menu "Processor type and features"
1249 bool <<
1250 152
1251 config DEFAULT_SGI_PARTITION !! 153 config SMP
1252 bool !! 154 bool "Symmetric multi-processing support"
>> 155 help
>> 156 This enables support for systems with more than one CPU. If you have
>> 157 a system with only one CPU, say N. If you have a system with more
>> 158 than one CPU, say Y.
1253 159
1254 config FW_ARC32 !! 160 If you say N here, the kernel will run on uni- and multiprocessor
1255 bool !! 161 machines, but will use only one CPU of a multiprocessor machine. If
>> 162 you say Y here, the kernel will run on many, but not all,
>> 163 uniprocessor machines. On a uniprocessor machine, the kernel
>> 164 will run faster if you say N here.
1256 165
1257 config FW_SNIPROM !! 166 People using multiprocessor machines who say Y here should also say
1258 bool !! 167 Y to "Enhanced Real Time Clock Support", below. The "Advanced Power
>> 168 Management" code will be disabled if you say Y here.
1259 169
1260 config BOOT_ELF32 !! 170 See also <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO
1261 bool !! 171 available at <https://www.tldp.org/docs.html#howto>.
1262 172
1263 config MIPS_L1_CACHE_SHIFT_4 !! 173 If you don't know what to do here, say N.
1264 bool <<
1265 174
1266 config MIPS_L1_CACHE_SHIFT_5 !! 175 config NR_CPUS
1267 bool !! 176 int "Maximum number of CPUs"
>> 177 depends on SMP
>> 178 range 2 32 if SPARC32
>> 179 range 2 4096 if SPARC64
>> 180 default 32 if SPARC32
>> 181 default 4096 if SPARC64
1268 182
1269 config MIPS_L1_CACHE_SHIFT_6 !! 183 source "kernel/Kconfig.hz"
1270 bool <<
1271 184
1272 config MIPS_L1_CACHE_SHIFT_7 !! 185 config GENERIC_HWEIGHT
1273 bool 186 bool
>> 187 default y
1274 188
1275 config MIPS_L1_CACHE_SHIFT !! 189 config GENERIC_CALIBRATE_DELAY
1276 int <<
1277 default "7" if MIPS_L1_CACHE_SHIFT_7 <<
1278 default "6" if MIPS_L1_CACHE_SHIFT_6 <<
1279 default "5" if MIPS_L1_CACHE_SHIFT_5 <<
1280 default "4" if MIPS_L1_CACHE_SHIFT_4 <<
1281 default "5" <<
1282 <<
1283 config ARC_CMDLINE_ONLY <<
1284 bool 190 bool
>> 191 default y
1285 192
1286 config ARC_CONSOLE !! 193 config ARCH_MAY_HAVE_PC_FDC
1287 bool "ARC console support" <<
1288 depends on SGI_IP22 || SGI_IP28 || (S <<
1289 <<
1290 config ARC_MEMORY <<
1291 bool 194 bool
>> 195 default y
1292 196
1293 config ARC_PROMLIB !! 197 config EMULATED_CMPXCHG
1294 bool 198 bool
>> 199 default y if SPARC32
>> 200 help
>> 201 Sparc32 does not have a CAS instruction like sparc64. cmpxchg()
>> 202 is emulated, and therefore it is not completely atomic.
1295 203
1296 config FW_ARC64 !! 204 # Makefile helpers
>> 205 config SPARC32_SMP
1297 bool 206 bool
>> 207 default y
>> 208 depends on SPARC32 && SMP
1298 209
1299 config BOOT_ELF64 !! 210 config SPARC64_SMP
1300 bool 211 bool
1301 <<
1302 menu "CPU selection" <<
1303 <<
1304 choice <<
1305 prompt "CPU type" <<
1306 default CPU_R4X00 <<
1307 <<
1308 config CPU_LOONGSON64 <<
1309 bool "Loongson 64-bit CPU" <<
1310 depends on SYS_HAS_CPU_LOONGSON64 <<
1311 select ARCH_HAS_PHYS_TO_DMA <<
1312 select CPU_MIPSR2 <<
1313 select CPU_HAS_PREFETCH <<
1314 select CPU_SUPPORTS_64BIT_KERNEL <<
1315 select CPU_SUPPORTS_HIGHMEM <<
1316 select CPU_SUPPORTS_HUGEPAGES <<
1317 select CPU_SUPPORTS_MSA <<
1318 select CPU_SUPPORTS_VZ <<
1319 select CPU_DIEI_BROKEN if !LOONGSON3_ <<
1320 select CPU_MIPSR2_IRQ_VI <<
1321 select DMA_NONCOHERENT <<
1322 select WEAK_ORDERING <<
1323 select WEAK_REORDERING_BEYOND_LLSC <<
1324 select MIPS_ASID_BITS_VARIABLE <<
1325 select MIPS_PGD_C0_CONTEXT <<
1326 select MIPS_L1_CACHE_SHIFT_6 <<
1327 select MIPS_FP_SUPPORT <<
1328 select GPIOLIB <<
1329 select SWIOTLB <<
1330 help <<
1331 The Loongson GSx64(GS264/GS464/GS46 <<
1332 cores implements the MIPS64R2 instr <<
1333 including most 64-bit Loongson-2 (2 <<
1334 3B1000, 3B1500, 3A2000, 3A3000 and <<
1335 Loongson-2E/2F is not covered here <<
1336 <<
1337 config CPU_LOONGSON2E <<
1338 bool "Loongson 2E" <<
1339 depends on SYS_HAS_CPU_LOONGSON2E <<
1340 select CPU_LOONGSON2EF <<
1341 help <<
1342 The Loongson 2E processor implement <<
1343 with many extensions. <<
1344 <<
1345 It has an internal FPGA northbridge <<
1346 bonito64. <<
1347 <<
1348 config CPU_LOONGSON2F <<
1349 bool "Loongson 2F" <<
1350 depends on SYS_HAS_CPU_LOONGSON2F <<
1351 select CPU_LOONGSON2EF <<
1352 help <<
1353 The Loongson 2F processor implement <<
1354 with many extensions. <<
1355 <<
1356 Loongson2F have built-in DDR2 and P <<
1357 have a similar programming interfac <<
1358 Loongson2E. <<
1359 <<
1360 config CPU_LOONGSON1B <<
1361 bool "Loongson 1B" <<
1362 depends on SYS_HAS_CPU_LOONGSON1B <<
1363 select CPU_LOONGSON32 <<
1364 select LEDS_GPIO_REGISTER <<
1365 help <<
1366 The Loongson 1B is a 32-bit SoC, wh <<
1367 Release 1 instruction set and part <<
1368 instruction set. <<
1369 <<
1370 config CPU_LOONGSON1C <<
1371 bool "Loongson 1C" <<
1372 depends on SYS_HAS_CPU_LOONGSON1C <<
1373 select CPU_LOONGSON32 <<
1374 select LEDS_GPIO_REGISTER <<
1375 help <<
1376 The Loongson 1C is a 32-bit SoC, wh <<
1377 Release 1 instruction set and part <<
1378 instruction set. <<
1379 <<
1380 config CPU_MIPS32_R1 <<
1381 bool "MIPS32 Release 1" <<
1382 depends on SYS_HAS_CPU_MIPS32_R1 <<
1383 select CPU_HAS_PREFETCH <<
1384 select CPU_SUPPORTS_32BIT_KERNEL <<
1385 select CPU_SUPPORTS_HIGHMEM <<
1386 help <<
1387 Choose this option to build a kerne <<
1388 MIPS32 architecture. Most modern e <<
1389 MIPS processor are based on a MIPS3 <<
1390 specific type of processor in your <<
1391 otherwise CPU_MIPS32_R1 is a safe b <<
1392 Release 2 of the MIPS32 architectur <<
1393 years so chances are you even have <<
1394 in which case you should choose CPU <<
1395 performance. <<
1396 <<
1397 config CPU_MIPS32_R2 <<
1398 bool "MIPS32 Release 2" <<
1399 depends on SYS_HAS_CPU_MIPS32_R2 <<
1400 select CPU_HAS_PREFETCH <<
1401 select CPU_SUPPORTS_32BIT_KERNEL <<
1402 select CPU_SUPPORTS_HIGHMEM <<
1403 select CPU_SUPPORTS_MSA <<
1404 help <<
1405 Choose this option to build a kerne <<
1406 MIPS32 architecture. Most modern e <<
1407 MIPS processor are based on a MIPS3 <<
1408 specific type of processor in your <<
1409 otherwise CPU_MIPS32_R1 is a safe b <<
1410 <<
1411 config CPU_MIPS32_R5 <<
1412 bool "MIPS32 Release 5" <<
1413 depends on SYS_HAS_CPU_MIPS32_R5 <<
1414 select CPU_HAS_PREFETCH <<
1415 select CPU_SUPPORTS_32BIT_KERNEL <<
1416 select CPU_SUPPORTS_HIGHMEM <<
1417 select CPU_SUPPORTS_MSA <<
1418 select CPU_SUPPORTS_VZ <<
1419 select MIPS_O32_FP64_SUPPORT <<
1420 help <<
1421 Choose this option to build a kerne <<
1422 MIPS32 architecture. New MIPS proc <<
1423 family, are based on a MIPS32r5 pro <<
1424 processor, you probably need to sel <<
1425 <<
1426 config CPU_MIPS32_R6 <<
1427 bool "MIPS32 Release 6" <<
1428 depends on SYS_HAS_CPU_MIPS32_R6 <<
1429 select CPU_HAS_PREFETCH <<
1430 select CPU_NO_LOAD_STORE_LR <<
1431 select CPU_SUPPORTS_32BIT_KERNEL <<
1432 select CPU_SUPPORTS_HIGHMEM <<
1433 select CPU_SUPPORTS_MSA <<
1434 select CPU_SUPPORTS_VZ <<
1435 select MIPS_O32_FP64_SUPPORT <<
1436 help <<
1437 Choose this option to build a kerne <<
1438 MIPS32 architecture. New MIPS proc <<
1439 family, are based on a MIPS32r6 pro <<
1440 processor, you probably need to sel <<
1441 <<
1442 config CPU_MIPS64_R1 <<
1443 bool "MIPS64 Release 1" <<
1444 depends on SYS_HAS_CPU_MIPS64_R1 <<
1445 select CPU_HAS_PREFETCH <<
1446 select CPU_SUPPORTS_32BIT_KERNEL <<
1447 select CPU_SUPPORTS_64BIT_KERNEL <<
1448 select CPU_SUPPORTS_HIGHMEM <<
1449 select CPU_SUPPORTS_HUGEPAGES <<
1450 help <<
1451 Choose this option to build a kerne <<
1452 MIPS64 architecture. Many modern e <<
1453 MIPS processor are based on a MIPS6 <<
1454 specific type of processor in your <<
1455 otherwise CPU_MIPS64_R1 is a safe b <<
1456 Release 2 of the MIPS64 architectur <<
1457 years so chances are you even have <<
1458 in which case you should choose CPU <<
1459 performance. <<
1460 <<
1461 config CPU_MIPS64_R2 <<
1462 bool "MIPS64 Release 2" <<
1463 depends on SYS_HAS_CPU_MIPS64_R2 <<
1464 select CPU_HAS_PREFETCH <<
1465 select CPU_SUPPORTS_32BIT_KERNEL <<
1466 select CPU_SUPPORTS_64BIT_KERNEL <<
1467 select CPU_SUPPORTS_HIGHMEM <<
1468 select CPU_SUPPORTS_HUGEPAGES <<
1469 select CPU_SUPPORTS_MSA <<
1470 help <<
1471 Choose this option to build a kerne <<
1472 MIPS64 architecture. Many modern e <<
1473 MIPS processor are based on a MIPS6 <<
1474 specific type of processor in your <<
1475 otherwise CPU_MIPS64_R1 is a safe b <<
1476 <<
1477 config CPU_MIPS64_R5 <<
1478 bool "MIPS64 Release 5" <<
1479 depends on SYS_HAS_CPU_MIPS64_R5 <<
1480 select CPU_HAS_PREFETCH <<
1481 select CPU_SUPPORTS_32BIT_KERNEL <<
1482 select CPU_SUPPORTS_64BIT_KERNEL <<
1483 select CPU_SUPPORTS_HIGHMEM <<
1484 select CPU_SUPPORTS_HUGEPAGES <<
1485 select CPU_SUPPORTS_MSA <<
1486 select MIPS_O32_FP64_SUPPORT if 32BIT <<
1487 select CPU_SUPPORTS_VZ <<
1488 help <<
1489 Choose this option to build a kerne <<
1490 MIPS64 architecture. This is a int <<
1491 release partly implementing release <<
1492 any hardware known to be based on t <<
1493 <<
1494 config CPU_MIPS64_R6 <<
1495 bool "MIPS64 Release 6" <<
1496 depends on SYS_HAS_CPU_MIPS64_R6 <<
1497 select CPU_HAS_PREFETCH <<
1498 select CPU_NO_LOAD_STORE_LR <<
1499 select CPU_SUPPORTS_32BIT_KERNEL <<
1500 select CPU_SUPPORTS_64BIT_KERNEL <<
1501 select CPU_SUPPORTS_HIGHMEM <<
1502 select CPU_SUPPORTS_HUGEPAGES <<
1503 select CPU_SUPPORTS_MSA <<
1504 select MIPS_O32_FP64_SUPPORT if 32BIT <<
1505 select CPU_SUPPORTS_VZ <<
1506 help <<
1507 Choose this option to build a kerne <<
1508 MIPS64 architecture. New MIPS proc <<
1509 family, are based on a MIPS64r6 pro <<
1510 processor, you probably need to sel <<
1511 <<
1512 config CPU_P5600 <<
1513 bool "MIPS Warrior P5600" <<
1514 depends on SYS_HAS_CPU_P5600 <<
1515 select CPU_HAS_PREFETCH <<
1516 select CPU_SUPPORTS_32BIT_KERNEL <<
1517 select CPU_SUPPORTS_HIGHMEM <<
1518 select CPU_SUPPORTS_MSA <<
1519 select CPU_SUPPORTS_CPUFREQ <<
1520 select CPU_SUPPORTS_VZ <<
1521 select CPU_MIPSR2_IRQ_VI <<
1522 select CPU_MIPSR2_IRQ_EI <<
1523 select MIPS_O32_FP64_SUPPORT <<
1524 help <<
1525 Choose this option to build a kerne <<
1526 It's based on MIPS32r5 ISA with XPA <<
1527 MMU with two-levels TLB, UCA, MSA, <<
1528 level features like up to six P5600 <<
1529 cache, IOCU/IOMMU (though might be <<
1530 specific IP core configuration), GI <<
1531 eJTAG and PDtrace. <<
1532 <<
1533 config CPU_R3000 <<
1534 bool "R3000" <<
1535 depends on SYS_HAS_CPU_R3000 <<
1536 select CPU_HAS_WB <<
1537 select CPU_R3K_TLB <<
1538 select CPU_SUPPORTS_32BIT_KERNEL <<
1539 select CPU_SUPPORTS_HIGHMEM <<
1540 help <<
1541 Please make sure to pick the right <<
1542 designed to be generic, i.e. Kernel <<
1543 *not* work on R4000 machines and vi <<
1544 of the supported machines have an R <<
1545 might be a safe bet. If the result <<
1546 try to recompile with R3000. <<
1547 <<
1548 config CPU_R4300 <<
1549 bool "R4300" <<
1550 depends on SYS_HAS_CPU_R4300 <<
1551 select CPU_SUPPORTS_32BIT_KERNEL <<
1552 select CPU_SUPPORTS_64BIT_KERNEL <<
1553 help <<
1554 MIPS Technologies R4300-series proc <<
1555 <<
1556 config CPU_R4X00 <<
1557 bool "R4x00" <<
1558 depends on SYS_HAS_CPU_R4X00 <<
1559 select CPU_SUPPORTS_32BIT_KERNEL <<
1560 select CPU_SUPPORTS_64BIT_KERNEL <<
1561 select CPU_SUPPORTS_HUGEPAGES <<
1562 help <<
1563 MIPS Technologies R4000-series proc <<
1564 the R4000, R4400, R4600, and 4700. <<
1565 <<
1566 config CPU_TX49XX <<
1567 bool "R49XX" <<
1568 depends on SYS_HAS_CPU_TX49XX <<
1569 select CPU_HAS_PREFETCH <<
1570 select CPU_SUPPORTS_32BIT_KERNEL <<
1571 select CPU_SUPPORTS_64BIT_KERNEL <<
1572 select CPU_SUPPORTS_HUGEPAGES <<
1573 <<
1574 config CPU_R5000 <<
1575 bool "R5000" <<
1576 depends on SYS_HAS_CPU_R5000 <<
1577 select CPU_SUPPORTS_32BIT_KERNEL <<
1578 select CPU_SUPPORTS_64BIT_KERNEL <<
1579 select CPU_SUPPORTS_HUGEPAGES <<
1580 help <<
1581 MIPS Technologies R5000-series proc <<
1582 <<
1583 config CPU_R5500 <<
1584 bool "R5500" <<
1585 depends on SYS_HAS_CPU_R5500 <<
1586 select CPU_SUPPORTS_32BIT_KERNEL <<
1587 select CPU_SUPPORTS_64BIT_KERNEL <<
1588 select CPU_SUPPORTS_HUGEPAGES <<
1589 help <<
1590 NEC VR5500 and VR5500A series proce <<
1591 instruction set. <<
1592 <<
1593 config CPU_NEVADA <<
1594 bool "RM52xx" <<
1595 depends on SYS_HAS_CPU_NEVADA <<
1596 select CPU_SUPPORTS_32BIT_KERNEL <<
1597 select CPU_SUPPORTS_64BIT_KERNEL <<
1598 select CPU_SUPPORTS_HUGEPAGES <<
1599 help <<
1600 QED / PMC-Sierra RM52xx-series ("Ne <<
1601 <<
1602 config CPU_R10000 <<
1603 bool "R10000" <<
1604 depends on SYS_HAS_CPU_R10000 <<
1605 select CPU_HAS_PREFETCH <<
1606 select CPU_SUPPORTS_32BIT_KERNEL <<
1607 select CPU_SUPPORTS_64BIT_KERNEL <<
1608 select CPU_SUPPORTS_HIGHMEM <<
1609 select CPU_SUPPORTS_HUGEPAGES <<
1610 help <<
1611 MIPS Technologies R10000-series pro <<
1612 <<
1613 config CPU_RM7000 <<
1614 bool "RM7000" <<
1615 depends on SYS_HAS_CPU_RM7000 <<
1616 select CPU_HAS_PREFETCH <<
1617 select CPU_SUPPORTS_32BIT_KERNEL <<
1618 select CPU_SUPPORTS_64BIT_KERNEL <<
1619 select CPU_SUPPORTS_HIGHMEM <<
1620 select CPU_SUPPORTS_HUGEPAGES <<
1621 <<
1622 config CPU_SB1 <<
1623 bool "SB1" <<
1624 depends on SYS_HAS_CPU_SB1 <<
1625 select CPU_SUPPORTS_32BIT_KERNEL <<
1626 select CPU_SUPPORTS_64BIT_KERNEL <<
1627 select CPU_SUPPORTS_HIGHMEM <<
1628 select CPU_SUPPORTS_HUGEPAGES <<
1629 select WEAK_ORDERING <<
1630 <<
1631 config CPU_CAVIUM_OCTEON <<
1632 bool "Cavium Octeon processor" <<
1633 depends on SYS_HAS_CPU_CAVIUM_OCTEON <<
1634 select CPU_HAS_PREFETCH <<
1635 select CPU_SUPPORTS_64BIT_KERNEL <<
1636 select HAVE_PAGE_SIZE_8KB if !MIPS_VA <<
1637 select HAVE_PAGE_SIZE_32KB if !MIPS_V <<
1638 select WEAK_ORDERING <<
1639 select CPU_SUPPORTS_HIGHMEM <<
1640 select CPU_SUPPORTS_HUGEPAGES <<
1641 select USB_EHCI_BIG_ENDIAN_MMIO if CP <<
1642 select USB_OHCI_BIG_ENDIAN_MMIO if CP <<
1643 select MIPS_L1_CACHE_SHIFT_7 <<
1644 select CPU_SUPPORTS_VZ <<
1645 help <<
1646 The Cavium Octeon processor is a hi <<
1647 many ethernet hardware widgets for <<
1648 can have up to 16 Mips64v2 cores an <<
1649 Full details can be found at http:/ <<
1650 <<
1651 config CPU_BMIPS <<
1652 bool "Broadcom BMIPS" <<
1653 depends on SYS_HAS_CPU_BMIPS <<
1654 select CPU_MIPS32 <<
1655 select CPU_BMIPS32_3300 if SYS_HAS_CP <<
1656 select CPU_BMIPS4350 if SYS_HAS_CPU_B <<
1657 select CPU_BMIPS4380 if SYS_HAS_CPU_B <<
1658 select CPU_BMIPS5000 if SYS_HAS_CPU_B <<
1659 select CPU_SUPPORTS_32BIT_KERNEL <<
1660 select DMA_NONCOHERENT <<
1661 select IRQ_MIPS_CPU <<
1662 select SWAP_IO_SPACE <<
1663 select WEAK_ORDERING <<
1664 select CPU_SUPPORTS_HIGHMEM <<
1665 select CPU_HAS_PREFETCH <<
1666 select CPU_SUPPORTS_CPUFREQ <<
1667 select MIPS_EXTERNAL_TIMER <<
1668 select GENERIC_IRQ_MIGRATION if HOTPL <<
1669 help <<
1670 Support for BMIPS32/3300/4350/4380 <<
1671 <<
1672 endchoice <<
1673 <<
1674 config LOONGSON3_ENHANCEMENT <<
1675 bool "New Loongson-3 CPU Enhancements <<
1676 default n <<
1677 depends on CPU_LOONGSON64 <<
1678 help <<
1679 New Loongson-3 cores (since Loongso <<
1680 R1, Loongson-3B R1 and Loongson-3B <<
1681 FTLB, L1-VCache, EI/DI/Wait/Prefetc <<
1682 Local register, Read-Inhibit/Execut <<
1683 Fast TLB refill support, etc. <<
1684 <<
1685 This option enable those enhancemen <<
1686 time. If you want a generic kernel <<
1687 please say 'N' here. If you want a <<
1688 new Loongson-3 machines only, pleas <<
1689 <<
1690 config CPU_LOONGSON3_WORKAROUNDS <<
1691 bool "Loongson-3 LLSC Workarounds" <<
1692 default y if SMP <<
1693 depends on CPU_LOONGSON64 <<
1694 help <<
1695 Loongson-3 processors have the llsc <<
1696 Without workarounds the system may <<
1697 <<
1698 Say Y, unless you know what you are <<
1699 <<
1700 config CPU_LOONGSON3_CPUCFG_EMULATION <<
1701 bool "Emulate the CPUCFG instruction <<
1702 default y 212 default y
1703 depends on CPU_LOONGSON64 !! 213 depends on SPARC64 && SMP
1704 help <<
1705 Loongson-3A R4 and newer have the C <<
1706 userland to query CPU capabilities, <<
1707 option provides emulation of the in <<
1708 cores, back to Loongson-3A1000. <<
1709 <<
1710 If unsure, please say Y. <<
1711 214
1712 config CPU_MIPS32_3_5_FEATURES !! 215 config EARLYFB
1713 bool "MIPS32 Release 3.5 Features" !! 216 bool "Support for early boot text console"
1714 depends on SYS_HAS_CPU_MIPS32_R3_5 <<
1715 depends on CPU_MIPS32_R2 || CPU_MIPS3 <<
1716 CPU_P5600 <<
1717 help <<
1718 Choose this option to build a kerne <<
1719 MIPS32 architecture including featu <<
1720 support for Enhanced Virtual Addres <<
1721 <<
1722 config CPU_MIPS32_3_5_EVA <<
1723 bool "Enhanced Virtual Addressing (EV <<
1724 depends on CPU_MIPS32_3_5_FEATURES <<
1725 select EVA <<
1726 default y 217 default y
>> 218 depends on SPARC64
>> 219 select FONT_SUN8x16
>> 220 select FONT_SUPPORT
1727 help 221 help
1728 Choose this option if you want to e !! 222 Say Y here to enable a faster early framebuffer boot console.
1729 Addressing (EVA) on your MIPS32 cor <<
1730 One of its primary benefits is an i <<
1731 of lowmem (up to 3GB). If unsure, s <<
1732 223
1733 config CPU_MIPS32_R5_FEATURES !! 224 config HOTPLUG_CPU
1734 bool "MIPS32 Release 5 Features" !! 225 bool "Support for hot-pluggable CPUs"
1735 depends on SYS_HAS_CPU_MIPS32_R5 !! 226 depends on SPARC64 && SMP
1736 depends on CPU_MIPS32_R2 || CPU_MIPS3 <<
1737 help <<
1738 Choose this option to build a kerne <<
1739 MIPS32 architecture including featu <<
1740 support for Extended Physical Addre <<
1741 <<
1742 config CPU_MIPS32_R5_XPA <<
1743 bool "Extended Physical Addressing (X <<
1744 depends on CPU_MIPS32_R5_FEATURES <<
1745 depends on !EVA <<
1746 depends on !PAGE_SIZE_4KB <<
1747 depends on SYS_SUPPORTS_HIGHMEM <<
1748 select XPA <<
1749 select HIGHMEM <<
1750 select PHYS_ADDR_T_64BIT <<
1751 default n <<
1752 help 227 help
1753 Choose this option if you want to e !! 228 Say Y here to experiment with turning CPUs off and on. CPUs
1754 Addressing (XPA) on your MIPS32 cor !! 229 can be controlled through /sys/devices/system/cpu/cpu#.
1755 benefit is to increase physical add !! 230 Say N if you want to disable CPU hotplug.
1756 than 40 bits. Note that this has th <<
1757 64-bit addressing which in turn mak <<
1758 If unsure, say 'N' here. <<
1759 <<
1760 if CPU_LOONGSON2F <<
1761 config CPU_NOP_WORKAROUNDS <<
1762 bool <<
1763 231
1764 config CPU_JUMP_WORKAROUNDS !! 232 if SPARC64
1765 bool !! 233 source "drivers/cpufreq/Kconfig"
>> 234 endif
1766 235
1767 config CPU_LOONGSON2F_WORKAROUNDS !! 236 config US3_MC
1768 bool "Loongson 2F Workarounds" !! 237 tristate "UltraSPARC-III Memory Controller driver"
>> 238 depends on SPARC64
1769 default y 239 default y
1770 select CPU_NOP_WORKAROUNDS <<
1771 select CPU_JUMP_WORKAROUNDS <<
1772 help 240 help
1773 Loongson 2F01 / 2F02 processors hav !! 241 This adds a driver for the UltraSPARC-III memory controller.
1774 require workarounds. Without worka !! 242 Loading this driver allows exact mnemonic strings to be
1775 unexpectedly. For more information !! 243 printed in the event of a memory error, so that the faulty DIMM
1776 -mfix-loongson2f-nop and -mfix-loon !! 244 on the motherboard can be matched to the error.
1777 <<
1778 Loongson 2F03 and later have fixed <<
1779 are needed. The workarounds have n <<
1780 but may decrease the performance of <<
1781 be disabled unless the kernel is in <<
1782 systems. <<
1783 <<
1784 If unsure, please say Y. <<
1785 endif # CPU_LOONGSON2F <<
1786 <<
1787 config SYS_SUPPORTS_ZBOOT <<
1788 bool <<
1789 select HAVE_KERNEL_GZIP <<
1790 select HAVE_KERNEL_BZIP2 <<
1791 select HAVE_KERNEL_LZ4 <<
1792 select HAVE_KERNEL_LZMA <<
1793 select HAVE_KERNEL_LZO <<
1794 select HAVE_KERNEL_XZ <<
1795 select HAVE_KERNEL_ZSTD <<
1796 <<
1797 config SYS_SUPPORTS_ZBOOT_UART16550 <<
1798 bool <<
1799 select SYS_SUPPORTS_ZBOOT <<
1800 245
1801 config SYS_SUPPORTS_ZBOOT_UART_PROM !! 246 If in doubt, say Y, as this information can be very useful.
1802 bool <<
1803 select SYS_SUPPORTS_ZBOOT <<
1804 <<
1805 config CPU_LOONGSON2EF <<
1806 bool <<
1807 select CPU_SUPPORTS_32BIT_KERNEL <<
1808 select CPU_SUPPORTS_64BIT_KERNEL <<
1809 select CPU_SUPPORTS_HIGHMEM <<
1810 select CPU_SUPPORTS_HUGEPAGES <<
1811 247
1812 config CPU_LOONGSON32 !! 248 # Global things across all Sun machines.
>> 249 config GENERIC_LOCKBREAK
1813 bool 250 bool
1814 select CPU_MIPS32 !! 251 default y
1815 select CPU_MIPSR2 !! 252 depends on SPARC64 && SMP && PREEMPTION
1816 select CPU_HAS_PREFETCH <<
1817 select CPU_SUPPORTS_32BIT_KERNEL <<
1818 select CPU_SUPPORTS_HIGHMEM <<
1819 select CPU_SUPPORTS_CPUFREQ <<
1820 <<
1821 config CPU_BMIPS32_3300 <<
1822 select SMP_UP if SMP <<
1823 bool <<
1824 <<
1825 config CPU_BMIPS4350 <<
1826 bool <<
1827 select SYS_SUPPORTS_SMP <<
1828 select SYS_SUPPORTS_HOTPLUG_CPU <<
1829 <<
1830 config CPU_BMIPS4380 <<
1831 bool <<
1832 select MIPS_L1_CACHE_SHIFT_6 <<
1833 select SYS_SUPPORTS_SMP <<
1834 select SYS_SUPPORTS_HOTPLUG_CPU <<
1835 select CPU_HAS_RIXI <<
1836 <<
1837 config CPU_BMIPS5000 <<
1838 bool <<
1839 select MIPS_CPU_SCACHE <<
1840 select MIPS_L1_CACHE_SHIFT_7 <<
1841 select SYS_SUPPORTS_SMP <<
1842 select SYS_SUPPORTS_HOTPLUG_CPU <<
1843 select CPU_HAS_RIXI <<
1844 <<
1845 config SYS_HAS_CPU_LOONGSON64 <<
1846 bool <<
1847 select CPU_SUPPORTS_CPUFREQ <<
1848 select CPU_HAS_RIXI <<
1849 <<
1850 config SYS_HAS_CPU_LOONGSON2E <<
1851 bool <<
1852 <<
1853 config SYS_HAS_CPU_LOONGSON2F <<
1854 bool <<
1855 select CPU_SUPPORTS_CPUFREQ <<
1856 select CPU_SUPPORTS_ADDRWINCFG if 64B <<
1857 <<
1858 config SYS_HAS_CPU_LOONGSON1B <<
1859 bool <<
1860 <<
1861 config SYS_HAS_CPU_LOONGSON1C <<
1862 bool <<
1863 <<
1864 config SYS_HAS_CPU_MIPS32_R1 <<
1865 bool <<
1866 <<
1867 config SYS_HAS_CPU_MIPS32_R2 <<
1868 bool <<
1869 <<
1870 config SYS_HAS_CPU_MIPS32_R3_5 <<
1871 bool <<
1872 <<
1873 config SYS_HAS_CPU_MIPS32_R5 <<
1874 bool <<
1875 <<
1876 config SYS_HAS_CPU_MIPS32_R6 <<
1877 bool <<
1878 <<
1879 config SYS_HAS_CPU_MIPS64_R1 <<
1880 bool <<
1881 <<
1882 config SYS_HAS_CPU_MIPS64_R2 <<
1883 bool <<
1884 <<
1885 config SYS_HAS_CPU_MIPS64_R5 <<
1886 bool <<
1887 <<
1888 config SYS_HAS_CPU_MIPS64_R6 <<
1889 bool <<
1890 <<
1891 config SYS_HAS_CPU_P5600 <<
1892 bool <<
1893 <<
1894 config SYS_HAS_CPU_R3000 <<
1895 bool <<
1896 <<
1897 config SYS_HAS_CPU_R4300 <<
1898 bool <<
1899 <<
1900 config SYS_HAS_CPU_R4X00 <<
1901 bool <<
1902 <<
1903 config SYS_HAS_CPU_TX49XX <<
1904 bool <<
1905 <<
1906 config SYS_HAS_CPU_R5000 <<
1907 bool <<
1908 <<
1909 config SYS_HAS_CPU_R5500 <<
1910 bool <<
1911 <<
1912 config SYS_HAS_CPU_NEVADA <<
1913 bool <<
1914 <<
1915 config SYS_HAS_CPU_R10000 <<
1916 bool <<
1917 <<
1918 config SYS_HAS_CPU_RM7000 <<
1919 bool <<
1920 <<
1921 config SYS_HAS_CPU_SB1 <<
1922 bool <<
1923 <<
1924 config SYS_HAS_CPU_CAVIUM_OCTEON <<
1925 bool <<
1926 <<
1927 config SYS_HAS_CPU_BMIPS <<
1928 bool <<
1929 <<
1930 config SYS_HAS_CPU_BMIPS32_3300 <<
1931 bool <<
1932 select SYS_HAS_CPU_BMIPS <<
1933 <<
1934 config SYS_HAS_CPU_BMIPS4350 <<
1935 bool <<
1936 select SYS_HAS_CPU_BMIPS <<
1937 <<
1938 config SYS_HAS_CPU_BMIPS4380 <<
1939 bool <<
1940 select SYS_HAS_CPU_BMIPS <<
1941 <<
1942 config SYS_HAS_CPU_BMIPS5000 <<
1943 bool <<
1944 select SYS_HAS_CPU_BMIPS <<
1945 <<
1946 # <<
1947 # CPU may reorder R->R, R->W, W->R, W->W <<
1948 # Reordering beyond LL and SC is handled in W <<
1949 # <<
1950 config WEAK_ORDERING <<
1951 bool <<
1952 <<
1953 # <<
1954 # CPU may reorder reads and writes beyond LL/ <<
1955 # CPU may reorder R->LL, R->LL, W->LL, W->LL, <<
1956 # <<
1957 config WEAK_REORDERING_BEYOND_LLSC <<
1958 bool <<
1959 endmenu <<
1960 <<
1961 # <<
1962 # These two indicate any level of the MIPS32 <<
1963 # <<
1964 config CPU_MIPS32 <<
1965 bool <<
1966 default y if CPU_MIPS32_R1 || CPU_MIP <<
1967 CPU_MIPS32_R6 || CPU_P56 <<
1968 <<
1969 config CPU_MIPS64 <<
1970 bool <<
1971 default y if CPU_MIPS64_R1 || CPU_MIP <<
1972 CPU_MIPS64_R6 || CPU_LOO <<
1973 <<
1974 # <<
1975 # These indicate the revision of the architec <<
1976 # <<
1977 config CPU_MIPSR1 <<
1978 bool <<
1979 default y if CPU_MIPS32_R1 || CPU_MIP <<
1980 <<
1981 config CPU_MIPSR2 <<
1982 bool <<
1983 default y if CPU_MIPS32_R2 || CPU_MIP <<
1984 select CPU_HAS_RIXI <<
1985 select CPU_HAS_DIEI if !CPU_DIEI_BROK <<
1986 select MIPS_SPRAM <<
1987 <<
1988 config CPU_MIPSR5 <<
1989 bool <<
1990 default y if CPU_MIPS32_R5 || CPU_MIP <<
1991 select CPU_HAS_RIXI <<
1992 select CPU_HAS_DIEI if !CPU_DIEI_BROK <<
1993 select MIPS_SPRAM <<
1994 <<
1995 config CPU_MIPSR6 <<
1996 bool <<
1997 default y if CPU_MIPS32_R6 || CPU_MIP <<
1998 select CPU_HAS_RIXI <<
1999 select CPU_HAS_DIEI if !CPU_DIEI_BROK <<
2000 select HAVE_ARCH_BITREVERSE <<
2001 select MIPS_ASID_BITS_VARIABLE <<
2002 select MIPS_CRC_SUPPORT <<
2003 select MIPS_SPRAM <<
2004 <<
2005 config TARGET_ISA_REV <<
2006 int <<
2007 default 1 if CPU_MIPSR1 <<
2008 default 2 if CPU_MIPSR2 <<
2009 default 5 if CPU_MIPSR5 <<
2010 default 6 if CPU_MIPSR6 <<
2011 default 0 <<
2012 help <<
2013 Reflects the ISA revision being tar <<
2014 is effectively the Kconfig equivale <<
2015 <<
2016 config EVA <<
2017 bool <<
2018 <<
2019 config XPA <<
2020 bool <<
2021 <<
2022 config SYS_SUPPORTS_32BIT_KERNEL <<
2023 bool <<
2024 config SYS_SUPPORTS_64BIT_KERNEL <<
2025 bool <<
2026 config CPU_SUPPORTS_32BIT_KERNEL <<
2027 bool <<
2028 config CPU_SUPPORTS_64BIT_KERNEL <<
2029 bool <<
2030 config CPU_SUPPORTS_CPUFREQ <<
2031 bool <<
2032 config CPU_SUPPORTS_ADDRWINCFG <<
2033 bool <<
2034 config CPU_SUPPORTS_HUGEPAGES <<
2035 bool <<
2036 depends on !(32BIT && (PHYS_ADDR_T_64 <<
2037 config CPU_SUPPORTS_VZ <<
2038 bool <<
2039 config MIPS_PGD_C0_CONTEXT <<
2040 bool <<
2041 depends on 64BIT <<
2042 default y if (CPU_MIPSR2 || CPU_MIPSR <<
2043 <<
2044 # <<
2045 # Set to y for ptrace access to watch registe <<
2046 # <<
2047 config HARDWARE_WATCHPOINTS <<
2048 bool <<
2049 default y if CPU_MIPSR1 || CPU_MIPSR2 <<
2050 <<
2051 menu "Kernel type" <<
2052 <<
2053 choice <<
2054 prompt "Kernel code model" <<
2055 help <<
2056 You should only select this option <<
2057 actually benefits from 64-bit proce <<
2058 large memory. You will only be pre <<
2059 menu if your system does not suppor <<
2060 253
2061 config 32BIT !! 254 config NUMA
2062 bool "32-bit kernel" !! 255 bool "NUMA support"
2063 depends on CPU_SUPPORTS_32BIT_KERNEL !! 256 depends on SPARC64 && SMP
2064 select TRAD_SIGNALS <<
2065 help <<
2066 Select this option if you want to b <<
2067 257
2068 config 64BIT !! 258 config NODES_SHIFT
2069 bool "64-bit kernel" !! 259 int "Maximum NUMA Nodes (as a power of 2)"
2070 depends on CPU_SUPPORTS_64BIT_KERNEL !! 260 range 4 5 if SPARC64
>> 261 default "5"
>> 262 depends on NUMA
2071 help 263 help
2072 Select this option if you want to b !! 264 Specify the maximum number of NUMA Nodes available on the target
2073 !! 265 system. Increases memory reserved to accommodate various tables.
2074 endchoice <<
2075 <<
2076 config MIPS_VA_BITS_48 <<
2077 bool "48 bits virtual memory" <<
2078 depends on 64BIT <<
2079 help <<
2080 Support a maximum at least 48 bits <<
2081 memory. Default is 40 bits or less <<
2082 For page sizes 16k and above, this <<
2083 memory overhead for page tables. F <<
2084 level of page tables is added which <<
2085 overhead as well as slower TLB faul <<
2086 266
2087 If unsure, say N. !! 267 config ARCH_SPARSEMEM_ENABLE
2088 !! 268 def_bool y if SPARC64
2089 config ZBOOT_LOAD_ADDRESS !! 269 select SPARSEMEM_VMEMMAP_ENABLE
2090 hex "Compressed kernel load address" <<
2091 default 0xffffffff80400000 if BCM47XX <<
2092 default 0x0 <<
2093 depends on SYS_SUPPORTS_ZBOOT <<
2094 help <<
2095 The address to load compressed kern <<
2096 270
2097 This is only used if non-zero. !! 271 config ARCH_SPARSEMEM_DEFAULT
>> 272 def_bool y if SPARC64
2098 273
2099 config ARCH_FORCE_MAX_ORDER 274 config ARCH_FORCE_MAX_ORDER
2100 int "Maximum zone order" !! 275 int "Order of maximal physically contiguous allocations"
2101 default "13" if MIPS_HUGE_TLB_SUPPORT !! 276 default "12"
2102 default "12" if MIPS_HUGE_TLB_SUPPORT <<
2103 default "11" if MIPS_HUGE_TLB_SUPPORT <<
2104 default "10" <<
2105 help <<
2106 The kernel memory allocator divides <<
2107 blocks into "zones", where each zon <<
2108 pages. This option selects the lar <<
2109 keeps in the memory allocator. If <<
2110 blocks of physically contiguous mem <<
2111 increase this value. <<
2112 <<
2113 The page size is not necessarily 4K <<
2114 when choosing a value for this opti <<
2115 <<
2116 config BOARD_SCACHE <<
2117 bool <<
2118 <<
2119 config IP22_CPU_SCACHE <<
2120 bool <<
2121 select BOARD_SCACHE <<
2122 <<
2123 # <<
2124 # Support for a MIPS32 / MIPS64 style S-cache <<
2125 # <<
2126 config MIPS_CPU_SCACHE <<
2127 bool <<
2128 select BOARD_SCACHE <<
2129 <<
2130 config R5000_CPU_SCACHE <<
2131 bool <<
2132 select BOARD_SCACHE <<
2133 <<
2134 config RM7000_CPU_SCACHE <<
2135 bool <<
2136 select BOARD_SCACHE <<
2137 <<
2138 config SIBYTE_DMA_PAGEOPS <<
2139 bool "Use DMA to clear/copy pages" <<
2140 depends on CPU_SB1 <<
2141 help 277 help
2142 Instead of using the CPU to zero an !! 278 The kernel page allocator limits the size of maximal physically
2143 channel. These DMA channels are ot !! 279 contiguous allocations. The limit is called MAX_PAGE_ORDER and it
2144 SiByte Linux port. Seems to give a !! 280 defines the maximal power of two of number of pages that can be
>> 281 allocated as a single contiguous block. This option allows
>> 282 overriding the default setting when ability to allocate very
>> 283 large blocks of physically contiguous memory is required.
2145 284
2146 config CPU_HAS_PREFETCH !! 285 Don't change if unsure.
2147 bool <<
2148 286
2149 config CPU_GENERIC_DUMP_TLB !! 287 if SPARC64 || COMPILE_TEST
2150 bool !! 288 source "kernel/power/Kconfig"
2151 default y if !CPU_R3000 !! 289 endif
2152 290
2153 config MIPS_FP_SUPPORT !! 291 config SCHED_SMT
2154 bool "Floating Point support" if EXPE !! 292 bool "SMT (Hyperthreading) scheduler support"
>> 293 depends on SPARC64 && SMP
2155 default y 294 default y
2156 help 295 help
2157 Select y to include support for flo !! 296 SMT scheduler support improves the CPU scheduler's decision making
2158 including initialization of FPU har !! 297 when dealing with SPARC cpus at a cost of slightly increased overhead
2159 and emulation of an FPU where neces !! 298 in some places. If unsure say N here.
2160 userland program attempting to use <<
2161 receive a SIGILL. <<
2162 <<
2163 If you know that your userland will <<
2164 instructions then you can say n her <<
2165 <<
2166 If unsure, say y. <<
2167 <<
2168 config CPU_R2300_FPU <<
2169 bool <<
2170 depends on MIPS_FP_SUPPORT <<
2171 default y if CPU_R3000 <<
2172 <<
2173 config CPU_R3K_TLB <<
2174 bool <<
2175 <<
2176 config CPU_R4K_FPU <<
2177 bool <<
2178 depends on MIPS_FP_SUPPORT <<
2179 default y if !CPU_R2300_FPU <<
2180 <<
2181 config CPU_R4K_CACHE_TLB <<
2182 bool <<
2183 default y if !(CPU_R3K_TLB || CPU_SB1 <<
2184 299
2185 config MIPS_MT_SMP !! 300 config SCHED_MC
2186 bool "MIPS MT SMP support (1 TC on ea !! 301 bool "Multi-core scheduler support"
>> 302 depends on SPARC64 && SMP
2187 default y 303 default y
2188 depends on TARGET_ISA_REV > 0 && TARG <<
2189 depends on SYS_SUPPORTS_MULTITHREADIN <<
2190 select CPU_MIPSR2_IRQ_VI <<
2191 select CPU_MIPSR2_IRQ_EI <<
2192 select SYNC_R4K <<
2193 select MIPS_MT <<
2194 select SMP <<
2195 select SMP_UP <<
2196 select SYS_SUPPORTS_SMP <<
2197 select SYS_SUPPORTS_SCHED_SMT <<
2198 select MIPS_PERF_SHARED_TC_COUNTERS <<
2199 help 304 help
2200 This is a kernel model which is kno !! 305 Multi-core scheduler support improves the CPU scheduler's decision
2201 on cores with the MT ASE and uses t !! 306 making when dealing with multi-core CPU chips at a cost of slightly
2202 virtual processors which supports S <<
2203 Intel Hyperthreading feature. For f <<
2204 <http://www.imgtec.com/mips/mips-mu <<
2205 <<
2206 config MIPS_MT <<
2207 bool <<
2208 <<
2209 config SCHED_SMT <<
2210 bool "SMT (multithreading) scheduler <<
2211 depends on SYS_SUPPORTS_SCHED_SMT <<
2212 default n <<
2213 help <<
2214 SMT scheduler support improves the <<
2215 when dealing with MIPS MT enabled c <<
2216 increased overhead in some places. 307 increased overhead in some places. If unsure say N here.
2217 308
2218 config SYS_SUPPORTS_SCHED_SMT !! 309 config CMDLINE_BOOL
2219 bool !! 310 bool "Default bootloader kernel arguments"
>> 311 depends on SPARC64
2220 312
2221 config SYS_SUPPORTS_MULTITHREADING !! 313 config CMDLINE
2222 bool !! 314 string "Initial kernel command string"
2223 !! 315 depends on CMDLINE_BOOL
2224 config MIPS_MT_FPAFF !! 316 default "console=ttyS0,9600 root=/dev/sda1"
2225 bool "Dynamic FPU affinity for FP-int <<
2226 default y <<
2227 depends on MIPS_MT_SMP <<
2228 <<
2229 config MIPSR2_TO_R6_EMULATOR <<
2230 bool "MIPS R2-to-R6 emulator" <<
2231 depends on CPU_MIPSR6 <<
2232 depends on MIPS_FP_SUPPORT <<
2233 default y <<
2234 help 317 help
2235 Choose this option if you want to r !! 318 Say Y here if you want to be able to pass default arguments to
2236 Even if you say 'Y' here, the emula !! 319 the kernel. This will be overridden by the bootloader, if you
2237 default. You can enable it using th !! 320 use one (such as SILO). This is most useful if you want to boot
2238 The only reason this is a build-tim !! 321 a kernel from TFTP, and want default options to be available
2239 final kernel image. !! 322 with having them passed on the command line.
2240 323
2241 config SYS_SUPPORTS_VPE_LOADER !! 324 NOTE: This option WILL override the PROM bootargs setting!
2242 bool <<
2243 depends on SYS_SUPPORTS_MULTITHREADIN <<
2244 help <<
2245 Indicates that the platform support <<
2246 physical_memsize. <<
2247 <<
2248 config MIPS_VPE_LOADER <<
2249 bool "VPE loader support." <<
2250 depends on SYS_SUPPORTS_VPE_LOADER && <<
2251 select CPU_MIPSR2_IRQ_VI <<
2252 select CPU_MIPSR2_IRQ_EI <<
2253 select MIPS_MT <<
2254 help <<
2255 Includes a loader for loading an el <<
2256 onto another VPE and running it. <<
2257 325
2258 config MIPS_VPE_LOADER_MT !! 326 config SUN_PM
2259 bool 327 bool
2260 default "y" !! 328 default y if SPARC32
2261 depends on MIPS_VPE_LOADER <<
2262 <<
2263 config MIPS_VPE_LOADER_TOM <<
2264 bool "Load VPE program into memory hi <<
2265 depends on MIPS_VPE_LOADER <<
2266 default y <<
2267 help 329 help
2268 The loader can use memory that is p !! 330 Enable power management and CPU standby features on supported
2269 Linux using the kernel command line !! 331 SPARC platforms.
2270 you to ensure the amount you put in <<
2271 program requires is less or equal t <<
2272 <<
2273 config MIPS_VPE_APSP_API <<
2274 bool "Enable support for AP/SP API (R <<
2275 depends on MIPS_VPE_LOADER <<
2276 332
2277 config MIPS_VPE_APSP_API_MT !! 333 config SPARC_LED
2278 bool !! 334 tristate "Sun4m LED driver"
2279 default "y" !! 335 depends on SPARC32
2280 depends on MIPS_VPE_APSP_API <<
2281 <<
2282 config MIPS_CPS <<
2283 bool "MIPS Coherent Processing System <<
2284 depends on SYS_SUPPORTS_MIPS_CPS <<
2285 select MIPS_CM <<
2286 select MIPS_CPS_PM if HOTPLUG_CPU <<
2287 select SMP <<
2288 select HOTPLUG_CORE_SYNC_DEAD if HOTP <<
2289 select SYNC_R4K if (CEVT_R4K || CSRC_ <<
2290 select SYS_SUPPORTS_HOTPLUG_CPU <<
2291 select SYS_SUPPORTS_SCHED_SMT if CPU_ <<
2292 select SYS_SUPPORTS_SMP <<
2293 select WEAK_ORDERING <<
2294 select GENERIC_IRQ_MIGRATION if HOTPL <<
2295 help 336 help
2296 Select this if you wish to run an S !! 337 This driver toggles the front-panel LED on sun4m systems
2297 within a MIPS Coherent Processing S !! 338 in a user-specifiable manner. Its state can be probed
2298 enabled the kernel will probe for o !! 339 by reading /proc/led and its blinking mode can be changed
2299 no external assistance. It is safe !! 340 via writes to /proc/led
2300 support is unavailable. <<
2301 <<
2302 config MIPS_CPS_PM <<
2303 depends on MIPS_CPS <<
2304 bool <<
2305 <<
2306 config MIPS_CM <<
2307 bool <<
2308 select MIPS_CPC <<
2309 <<
2310 config MIPS_CPC <<
2311 bool <<
2312 <<
2313 config SB1_PASS_2_WORKAROUNDS <<
2314 bool <<
2315 depends on CPU_SB1 && (CPU_SB1_PASS_2 <<
2316 default y <<
2317 341
2318 config SB1_PASS_2_1_WORKAROUNDS !! 342 config SERIAL_CONSOLE
2319 bool 343 bool
2320 depends on CPU_SB1 && CPU_SB1_PASS_2 !! 344 depends on SPARC32
2321 default y 345 default y
2322 <<
2323 choice <<
2324 prompt "SmartMIPS or microMIPS ASE su <<
2325 <<
2326 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS <<
2327 bool "None" <<
2328 help 346 help
2329 Select this if you want neither mic !! 347 If you say Y here, it will be possible to use a serial port as the
>> 348 system console (the system console is the device which receives all
>> 349 kernel messages and warnings and which allows logins in single user
>> 350 mode). This could be useful if some terminal or printer is connected
>> 351 to that serial port.
2330 352
2331 config CPU_HAS_SMARTMIPS !! 353 Even if you say Y here, the currently visible virtual console
2332 depends on SYS_SUPPORTS_SMARTMIPS !! 354 (/dev/tty0) will still be used as the system console by default, but
2333 bool "SmartMIPS" !! 355 you can alter that using a kernel command line option such as
2334 help !! 356 "console=ttyS1". (Try "man bootparam" or see the documentation of
2335 SmartMIPS is a extension of the MIP !! 357 your boot loader (silo) about how to pass options to the kernel at
2336 increased security at both hardware !! 358 boot time.)
2337 smartcards. Enabling this option w <<
2338 SmartMIPS instructions by Linux app <<
2339 this option will not work on a MIPS <<
2340 you don't know you probably don't h <<
2341 here. <<
2342 359
2343 config CPU_MICROMIPS !! 360 If you don't have a graphics card installed and you say Y here, the
2344 depends on 32BIT && SYS_SUPPORTS_MICR !! 361 kernel will automatically use the first serial line, /dev/ttyS0, as
2345 bool "microMIPS" !! 362 system console.
2346 help <<
2347 When this option is enabled the ker <<
2348 microMIPS ISA <<
2349 363
2350 endchoice !! 364 If unsure, say N.
2351 365
2352 config CPU_HAS_MSA !! 366 config SPARC_LEON
2353 bool "Support for the MIPS SIMD Archi !! 367 bool "Sparc Leon processor family"
2354 depends on CPU_SUPPORTS_MSA !! 368 depends on SPARC32
2355 depends on MIPS_FP_SUPPORT !! 369 select USB_EHCI_BIG_ENDIAN_MMIO
2356 depends on 64BIT || MIPS_O32_FP64_SUP !! 370 select USB_EHCI_BIG_ENDIAN_DESC
>> 371 select USB_UHCI_BIG_ENDIAN_MMIO
>> 372 select USB_UHCI_BIG_ENDIAN_DESC
>> 373 help
>> 374 If you say Y here if you are running on a SPARC-LEON processor.
>> 375 The LEON processor is a synthesizable VHDL model of the
>> 376 SPARC-v8 standard. LEON is part of the GRLIB collection of
>> 377 IP cores that are distributed under GPL. GRLIB can be downloaded
>> 378 from www.gaisler.com. You can download a sparc-linux cross-compilation
>> 379 toolchain at www.gaisler.com.
>> 380
>> 381 if SPARC_LEON
>> 382 menu "U-Boot options"
>> 383
>> 384 config UBOOT_LOAD_ADDR
>> 385 hex "uImage Load Address"
>> 386 default 0x40004000
>> 387 help
>> 388 U-Boot kernel load address, the address in physical address space
>> 389 where u-boot will place the Linux kernel before booting it.
>> 390 This address is normally the base address of main memory + 0x4000.
>> 391
>> 392 config UBOOT_FLASH_ADDR
>> 393 hex "uImage.o Load Address"
>> 394 default 0x00080000
>> 395 help
>> 396 Optional setting only affecting the uImage.o ELF-image used to
>> 397 download the uImage file to the target using a ELF-loader other than
>> 398 U-Boot. It may for example be used to download an uImage to FLASH with
>> 399 the GRMON utility before even starting u-boot.
>> 400
>> 401 config UBOOT_ENTRY_ADDR
>> 402 hex "uImage Entry Address"
>> 403 default 0xf0004000
2357 help 404 help
2358 MIPS SIMD Architecture (MSA) introd !! 405 Do not change this unless you know what you're doing. This is
2359 and a set of SIMD instructions to o !! 406 hardcoded by the SPARC32 and LEON port.
2360 is enabled the kernel will support <<
2361 vector register contexts. If you kn <<
2362 running on CPUs which do not suppor <<
2363 not be making use of it then you ma <<
2364 the size & complexity of your kerne <<
2365 407
2366 If unsure, say Y. !! 408 This is the virtual address u-boot jumps to when booting the Linux
>> 409 Kernel.
2367 410
2368 config CPU_HAS_WB !! 411 endmenu
2369 bool !! 412 endif
2370 <<
2371 config XKS01 <<
2372 bool <<
2373 <<
2374 config CPU_HAS_DIEI <<
2375 depends on !CPU_DIEI_BROKEN <<
2376 bool <<
2377 <<
2378 config CPU_DIEI_BROKEN <<
2379 bool <<
2380 <<
2381 config CPU_HAS_RIXI <<
2382 bool <<
2383 <<
2384 config CPU_NO_LOAD_STORE_LR <<
2385 bool <<
2386 help <<
2387 CPU lacks support for unaligned loa <<
2388 LWL, LWR, SWL, SWR (Load/store word <<
2389 LDL, LDR, SDL, SDR (Load/store doub <<
2390 systems). <<
2391 <<
2392 # <<
2393 # Vectored interrupt mode is an R2 feature <<
2394 # <<
2395 config CPU_MIPSR2_IRQ_VI <<
2396 bool <<
2397 413
2398 # !! 414 endmenu
2399 # Extended interrupt mode is an R2 feature <<
2400 # <<
2401 config CPU_MIPSR2_IRQ_EI <<
2402 bool <<
2403 415
2404 config CPU_HAS_SYNC !! 416 menu "Bus options (PCI etc.)"
>> 417 config SBUS
2405 bool 418 bool
2406 depends on !CPU_R3000 <<
2407 default y 419 default y
2408 420
2409 # !! 421 config SBUSCHAR
2410 # CPU non-features <<
2411 # <<
2412 <<
2413 # Work around the "daddi" and "daddiu" CPU er <<
2414 # <<
2415 # - The `daddi' instruction fails to trap on <<
2416 # "MIPS R4000PC/SC Errata, Processor Revisi <<
2417 # erratum #23 <<
2418 # <<
2419 # - The `daddiu' instruction can produce an i <<
2420 # "MIPS R4000PC/SC Errata, Processor Revisi <<
2421 # erratum #41 <<
2422 # "MIPS R4000MC Errata, Processor Revision <<
2423 # #15 <<
2424 # "MIPS R4400PC/SC Errata, Processor Revisi <<
2425 # "MIPS R4400MC Errata, Processor Revision <<
2426 config CPU_DADDI_WORKAROUNDS <<
2427 bool <<
2428 <<
2429 # Work around certain R4000 CPU errata (as im <<
2430 # <<
2431 # - A double-word or a variable shift may giv <<
2432 # if executed immediately after starting an <<
2433 # "MIPS R4000PC/SC Errata, Processor Revisi <<
2434 # erratum #28 <<
2435 # "MIPS R4000MC Errata, Processor Revision <<
2436 # #19 <<
2437 # <<
2438 # - A double-word or a variable shift may giv <<
2439 # if executed while an integer multiplicati <<
2440 # "MIPS R4000PC/SC Errata, Processor Revisi <<
2441 # errata #16 & #28 <<
2442 # <<
2443 # - An integer division may give an incorrect <<
2444 # a delay slot of a taken branch or a jump: <<
2445 # "MIPS R4000PC/SC Errata, Processor Revisi <<
2446 # erratum #52 <<
2447 config CPU_R4000_WORKAROUNDS <<
2448 bool <<
2449 select CPU_R4400_WORKAROUNDS <<
2450 <<
2451 # Work around certain R4400 CPU errata (as im <<
2452 # <<
2453 # - A double-word or a variable shift may giv <<
2454 # if executed immediately after starting an <<
2455 # "MIPS R4400MC Errata, Processor Revision <<
2456 # "MIPS R4400MC Errata, Processor Revision <<
2457 config CPU_R4400_WORKAROUNDS <<
2458 bool <<
2459 <<
2460 config CPU_R4X00_BUGS64 <<
2461 bool <<
2462 default y if SYS_HAS_CPU_R4X00 && 64B <<
2463 <<
2464 config MIPS_ASID_SHIFT <<
2465 int <<
2466 default 6 if CPU_R3000 <<
2467 default 0 <<
2468 <<
2469 config MIPS_ASID_BITS <<
2470 int <<
2471 default 0 if MIPS_ASID_BITS_VARIABLE <<
2472 default 6 if CPU_R3000 <<
2473 default 8 <<
2474 <<
2475 config MIPS_ASID_BITS_VARIABLE <<
2476 bool <<
2477 <<
2478 config MIPS_CRC_SUPPORT <<
2479 bool <<
2480 <<
2481 # R4600 erratum. Due to the lack of errata i <<
2482 # technical details aren't known. I've exper <<
2483 # interrupts during indexed I-cache flushes s <<
2484 # with the issue. <<
2485 config WAR_R4600_V1_INDEX_ICACHEOP <<
2486 bool <<
2487 <<
2488 # Pleasures of the R4600 V1.x. Cite from the <<
2489 # <<
2490 # 18. The CACHE instructions Hit_Writeback_I <<
2491 # Hit_Invalidate_D and Create_Dirty_Excl <<
2492 # executed if there is no other dcache a <<
2493 # accessed for another instruction immed <<
2494 # cache instructions are executing, it i <<
2495 # tag match outputs used by these cache <<
2496 # incorrect. These cache instructions sh <<
2497 # four instructions that are not any kin <<
2498 # instruction. <<
2499 # <<
2500 # This is not allowed: lw <<
2501 # nop <<
2502 # nop <<
2503 # nop <<
2504 # cache Hi <<
2505 # <<
2506 # This is allowed: lw <<
2507 # nop <<
2508 # nop <<
2509 # nop <<
2510 # nop <<
2511 # cache Hi <<
2512 config WAR_R4600_V1_HIT_CACHEOP <<
2513 bool <<
2514 <<
2515 # Writeback and invalidate the primary cache <<
2516 # <<
2517 # R4600 v2.0 bug: "The CACHE instructions Hit <<
2518 # Hit_Writeback_D, Hit_Invalidate_D and Creat <<
2519 # operate correctly if the internal data cach <<
2520 # CACHE instructions should be separated from <<
2521 # by a load instruction to an uncached addres <<
2522 # (Revision 2.0 device errata from IDT availa <<
2523 # in .pdf format.) <<
2524 config WAR_R4600_V2_HIT_CACHEOP <<
2525 bool <<
2526 <<
2527 # From TX49/H2 manual: "If the instruction (i <<
2528 # the line which this instruction itself exis <<
2529 # operation is not guaranteed." <<
2530 # <<
2531 # Workaround: do two phase flushing for Index <<
2532 config WAR_TX49XX_ICACHE_INDEX_INV <<
2533 bool <<
2534 <<
2535 # The RM7000 processors and the E9000 cores h <<
2536 # opposes it being called that) where invalid <<
2537 # I-cache line worth of instructions being fe <<
2538 # exceptions. <<
2539 config WAR_ICACHE_REFILLS <<
2540 bool <<
2541 <<
2542 # On the R10000 up to version 2.6 (not sure a <<
2543 # may cause ll / sc and lld / scd sequences t <<
2544 config WAR_R10000_LLSC <<
2545 bool <<
2546 <<
2547 # 34K core erratum: "Problems Executing the T <<
2548 config WAR_MIPS34K_MISSED_ITLB <<
2549 bool <<
2550 <<
2551 # <<
2552 # - Highmem only makes sense for the 32-bit k <<
2553 # - The current highmem code will only work p <<
2554 # caches such as R3000, SB1, R7000 or those <<
2555 # indexed such as R4000/R4400 SC and MC ver <<
2556 # moment we protect the user and offer the <<
2557 # where it's known to be safe. This will n <<
2558 # such as MIPS32 and MIPS64 CPUs which may <<
2559 # indexed CPUs but we're playing safe. <<
2560 # - We use SYS_SUPPORTS_HIGHMEM to offer high <<
2561 # know they might have memory configuration <<
2562 # support. <<
2563 # <<
2564 config HIGHMEM <<
2565 bool "High Memory Support" <<
2566 depends on 32BIT && CPU_SUPPORTS_HIGH <<
2567 select KMAP_LOCAL <<
2568 <<
2569 config CPU_SUPPORTS_HIGHMEM <<
2570 bool <<
2571 <<
2572 config SYS_SUPPORTS_HIGHMEM <<
2573 bool <<
2574 <<
2575 config SYS_SUPPORTS_SMARTMIPS <<
2576 bool <<
2577 <<
2578 config SYS_SUPPORTS_MICROMIPS <<
2579 bool 422 bool
>> 423 default y
2580 424
2581 config SYS_SUPPORTS_MIPS16 !! 425 config SUN_LDOMS
2582 bool !! 426 bool "Sun Logical Domains support"
>> 427 depends on SPARC64
2583 help 428 help
2584 This option must be set if a kernel !! 429 Say Y here is you want to support virtual devices via
2585 enabled CPU even if MIPS16 is not a !! 430 Logical Domains.
2586 words, it makes the kernel MIPS16-t <<
2587 431
2588 config CPU_SUPPORTS_MSA !! 432 config PCIC_PCI
2589 bool 433 bool
>> 434 depends on PCI && SPARC32 && !SPARC_LEON
>> 435 default y
2590 436
2591 config ARCH_FLATMEM_ENABLE !! 437 config LEON_PCI
2592 def_bool y <<
2593 depends on !NUMA && !CPU_LOONGSON2EF <<
2594 <<
2595 config ARCH_SPARSEMEM_ENABLE <<
2596 bool 438 bool
2597 !! 439 depends on PCI && SPARC_LEON
2598 config NUMA <<
2599 bool "NUMA Support" <<
2600 depends on SYS_SUPPORTS_NUMA <<
2601 select SMP <<
2602 select HAVE_SETUP_PER_CPU_AREA <<
2603 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
2604 help <<
2605 Say Y to compile the kernel to supp <<
2606 Access). This option improves perf <<
2607 than two nodes; on two node systems <<
2608 leave it disabled; on single node s <<
2609 disabled. <<
2610 <<
2611 config SYS_SUPPORTS_NUMA <<
2612 bool <<
2613 <<
2614 config RELOCATABLE <<
2615 bool "Relocatable kernel" <<
2616 depends on SYS_SUPPORTS_RELOCATABLE <<
2617 depends on CPU_MIPS32_R2 || CPU_MIPS6 <<
2618 CPU_MIPS32_R5 || CPU_MIPS6 <<
2619 CPU_MIPS32_R6 || CPU_MIPS6 <<
2620 CPU_P5600 || CAVIUM_OCTEON <<
2621 CPU_LOONGSON64 <<
2622 help <<
2623 This builds a kernel image that ret <<
2624 so it can be loaded someplace besid <<
2625 The relocations make the kernel bin <<
2626 but are discarded at runtime <<
2627 <<
2628 config RELOCATION_TABLE_SIZE <<
2629 hex "Relocation table size" <<
2630 depends on RELOCATABLE <<
2631 range 0x0 0x01000000 <<
2632 default "0x00200000" if CPU_LOONGSON6 <<
2633 default "0x00100000" <<
2634 help <<
2635 A table of relocation data will be <<
2636 and parsed at boot to fix up the re <<
2637 <<
2638 This option allows the amount of sp <<
2639 adjusted, although the default of 1 <<
2640 <<
2641 The build will fail and a valid siz <<
2642 <<
2643 If unsure, leave at the default val <<
2644 <<
2645 config RANDOMIZE_BASE <<
2646 bool "Randomize the address of the ke <<
2647 depends on RELOCATABLE <<
2648 help <<
2649 Randomizes the physical and virtual <<
2650 kernel image is loaded, as a securi <<
2651 deters exploit attempts relying on <<
2652 of kernel internals. <<
2653 <<
2654 Entropy is generated using any copr <<
2655 <<
2656 The kernel will be offset by up to <<
2657 <<
2658 If unsure, say N. <<
2659 <<
2660 config RANDOMIZE_BASE_MAX_OFFSET <<
2661 hex "Maximum kASLR offset" if EXPERT <<
2662 depends on RANDOMIZE_BASE <<
2663 range 0x0 0x40000000 if EVA || 64BIT <<
2664 range 0x0 0x08000000 <<
2665 default "0x01000000" <<
2666 help <<
2667 When kASLR is active, this provides <<
2668 be applied to the kernel image. It <<
2669 amount of physical RAM available in <<
2670 PHYSICAL_START and must be a power <<
2671 <<
2672 This is limited by the size of KSEG <<
2673 EVA or 64-bit. The default is 16Mb. <<
2674 <<
2675 config NODES_SHIFT <<
2676 int <<
2677 default "6" <<
2678 depends on NUMA <<
2679 <<
2680 config HW_PERF_EVENTS <<
2681 bool "Enable hardware performance cou <<
2682 depends on PERF_EVENTS && (CPU_MIPS32 <<
2683 default y 440 default y
2684 help <<
2685 Enable hardware performance counter <<
2686 disabled, perf events will use soft <<
2687 441
2688 config DMI !! 442 config SPARC_GRPCI1
2689 bool "Enable DMI scanning" !! 443 bool "GRPCI Host Bridge Support"
2690 depends on MACH_LOONGSON64 !! 444 depends on LEON_PCI
2691 select DMI_SCAN_MACHINE_NON_EFI_FALLB <<
2692 default y 445 default y
2693 help 446 help
2694 Enabled scanning of DMI to identify !! 447 Say Y here to include the GRPCI Host Bridge Driver. The GRPCI
2695 here unless you have verified that !! 448 PCI host controller is typically found in GRLIB SPARC32/LEON
2696 affected by entries in the DMI blac !! 449 systems. The driver has one property (all_pci_errors) controlled
2697 BIOS code. !! 450 from the bootloader that makes the GRPCI to generate interrupts
2698 !! 451 on detected PCI Parity and System errors.
2699 config SMP <<
2700 bool "Multi-Processing support" <<
2701 depends on SYS_SUPPORTS_SMP <<
2702 help <<
2703 This enables support for systems wi <<
2704 a system with only one CPU, say N. <<
2705 than one CPU, say Y. <<
2706 <<
2707 If you say N here, the kernel will <<
2708 machines, but will use only one CPU <<
2709 you say Y here, the kernel will run <<
2710 uniprocessor machines. On a uniproc <<
2711 will run faster if you say N here. <<
2712 452
2713 People using multiprocessor machine !! 453 config SPARC_GRPCI2
2714 Y to "Enhanced Real Time Clock Supp !! 454 bool "GRPCI2 Host Bridge Support"
2715 !! 455 depends on LEON_PCI
2716 See also the SMP-HOWTO available at !! 456 default y
2717 <https://www.tldp.org/docs.html#how <<
2718 <<
2719 If you don't know what to do here, <<
2720 <<
2721 config HOTPLUG_CPU <<
2722 bool "Support for hot-pluggable CPUs" <<
2723 depends on SMP && SYS_SUPPORTS_HOTPLU <<
2724 help <<
2725 Say Y here to allow turning CPUs of <<
2726 controlled through /sys/devices/sys <<
2727 (Note: power management support wil <<
2728 automatically on SMP systems. ) <<
2729 Say N if you want to disable CPU ho <<
2730 <<
2731 config SMP_UP <<
2732 bool <<
2733 <<
2734 config SYS_SUPPORTS_MIPS_CPS <<
2735 bool <<
2736 <<
2737 config SYS_SUPPORTS_SMP <<
2738 bool <<
2739 <<
2740 config NR_CPUS_DEFAULT_4 <<
2741 bool <<
2742 <<
2743 config NR_CPUS_DEFAULT_8 <<
2744 bool <<
2745 <<
2746 config NR_CPUS_DEFAULT_16 <<
2747 bool <<
2748 <<
2749 config NR_CPUS_DEFAULT_32 <<
2750 bool <<
2751 <<
2752 config NR_CPUS_DEFAULT_64 <<
2753 bool <<
2754 <<
2755 config NR_CPUS <<
2756 int "Maximum number of CPUs (2-256)" <<
2757 range 2 256 <<
2758 depends on SMP <<
2759 default "4" if NR_CPUS_DEFAULT_4 <<
2760 default "8" if NR_CPUS_DEFAULT_8 <<
2761 default "16" if NR_CPUS_DEFAULT_16 <<
2762 default "32" if NR_CPUS_DEFAULT_32 <<
2763 default "64" if NR_CPUS_DEFAULT_64 <<
2764 help 457 help
2765 This allows you to specify the maxi !! 458 Say Y here to include the GRPCI2 Host Bridge Driver.
2766 kernel will support. The maximum s <<
2767 kernel and 64 for 64-bit kernels; t <<
2768 sense is 1 for Qemu (useful only fo <<
2769 and 2 for all others. <<
2770 <<
2771 This is purely to save memory - eac <<
2772 approximately eight kilobytes to th <<
2773 performance should round up your nu <<
2774 power of two. <<
2775 <<
2776 config MIPS_PERF_SHARED_TC_COUNTERS <<
2777 bool <<
2778 <<
2779 config MIPS_NR_CPU_NR_MAP_1024 <<
2780 bool <<
2781 <<
2782 config MIPS_NR_CPU_NR_MAP <<
2783 int <<
2784 depends on SMP <<
2785 default 1024 if MIPS_NR_CPU_NR_MAP_10 <<
2786 default NR_CPUS if !MIPS_NR_CPU_NR_MA <<
2787 459
2788 # !! 460 config SUN_OPENPROMFS
2789 # Timer Interrupt Frequency Configuration !! 461 tristate "Openprom tree appears in /proc/openprom"
2790 # <<
2791 <<
2792 choice <<
2793 prompt "Timer frequency" <<
2794 default HZ_250 <<
2795 help 462 help
2796 Allows the configuration of the tim !! 463 If you say Y, the OpenPROM device tree will be available as a
2797 !! 464 virtual file system, which you can mount to /proc/openprom by "mount
2798 config HZ_24 !! 465 -t openpromfs none /proc/openprom".
2799 bool "24 HZ" if SYS_SUPPORTS_ <<
2800 <<
2801 config HZ_48 <<
2802 bool "48 HZ" if SYS_SUPPORTS_ <<
2803 <<
2804 config HZ_100 <<
2805 bool "100 HZ" if SYS_SUPPORTS <<
2806 <<
2807 config HZ_128 <<
2808 bool "128 HZ" if SYS_SUPPORTS <<
2809 <<
2810 config HZ_250 <<
2811 bool "250 HZ" if SYS_SUPPORTS <<
2812 <<
2813 config HZ_256 <<
2814 bool "256 HZ" if SYS_SUPPORTS <<
2815 <<
2816 config HZ_1000 <<
2817 bool "1000 HZ" if SYS_SUPPORT <<
2818 466
2819 config HZ_1024 !! 467 To compile the /proc/openprom support as a module, choose M here: the
2820 bool "1024 HZ" if SYS_SUPPORT !! 468 module will be called openpromfs.
2821 469
2822 endchoice !! 470 Only choose N if you know in advance that you will not need to modify
>> 471 OpenPROM settings on the running system.
2823 472
2824 config SYS_SUPPORTS_24HZ !! 473 # Makefile helpers
2825 bool !! 474 config SPARC64_PCI
2826 <<
2827 config SYS_SUPPORTS_48HZ <<
2828 bool <<
2829 <<
2830 config SYS_SUPPORTS_100HZ <<
2831 bool <<
2832 <<
2833 config SYS_SUPPORTS_128HZ <<
2834 bool <<
2835 <<
2836 config SYS_SUPPORTS_250HZ <<
2837 bool <<
2838 <<
2839 config SYS_SUPPORTS_256HZ <<
2840 bool <<
2841 <<
2842 config SYS_SUPPORTS_1000HZ <<
2843 bool <<
2844 <<
2845 config SYS_SUPPORTS_1024HZ <<
2846 bool <<
2847 <<
2848 config SYS_SUPPORTS_ARBIT_HZ <<
2849 bool <<
2850 default y if !SYS_SUPPORTS_24HZ && \ <<
2851 !SYS_SUPPORTS_48HZ && \ <<
2852 !SYS_SUPPORTS_100HZ && \ <<
2853 !SYS_SUPPORTS_128HZ && \ <<
2854 !SYS_SUPPORTS_250HZ && \ <<
2855 !SYS_SUPPORTS_256HZ && \ <<
2856 !SYS_SUPPORTS_1000HZ && <<
2857 !SYS_SUPPORTS_1024HZ <<
2858 <<
2859 config HZ <<
2860 int <<
2861 default 24 if HZ_24 <<
2862 default 48 if HZ_48 <<
2863 default 100 if HZ_100 <<
2864 default 128 if HZ_128 <<
2865 default 250 if HZ_250 <<
2866 default 256 if HZ_256 <<
2867 default 1000 if HZ_1000 <<
2868 default 1024 if HZ_1024 <<
2869 <<
2870 config SCHED_HRTICK <<
2871 def_bool HIGH_RES_TIMERS <<
2872 <<
2873 config ARCH_SUPPORTS_KEXEC <<
2874 def_bool y <<
2875 <<
2876 config ARCH_SUPPORTS_CRASH_DUMP <<
2877 def_bool y <<
2878 <<
2879 config PHYSICAL_START <<
2880 hex "Physical address where the kerne <<
2881 default "0xffffffff84000000" <<
2882 depends on CRASH_DUMP <<
2883 help <<
2884 This gives the CKSEG0 or KSEG0 addr <<
2885 If you plan to use kernel for captu <<
2886 this value to start of the reserved <<
2887 specified in the "crashkernel=YM@XM <<
2888 passed to the panic-ed kernel). <<
2889 <<
2890 config MIPS_O32_FP64_SUPPORT <<
2891 bool "Support for O32 binaries using <<
2892 depends on 32BIT || MIPS32_O32 <<
2893 help <<
2894 When this is enabled, the kernel wi <<
2895 point registers with binaries using <<
2896 EF_MIPS_FP64 ELF header flag (typic <<
2897 32-bit MIPS systems this support is <<
2898 size and complexity of the compiled <<
2899 running a MIPS32 system and know th <<
2900 will require 64-bit floating point, <<
2901 of your kernel & potentially improv <<
2902 saying N here. <<
2903 <<
2904 Although binutils currently support <<
2905 concerning its effect upon the O32 <<
2906 worked on. In order to avoid userla <<
2907 behaviour before the details have b <<
2908 be considered experimental and only <<
2909 said details. <<
2910 <<
2911 If unsure, say N. <<
2912 <<
2913 config USE_OF <<
2914 bool <<
2915 select OF <<
2916 select OF_EARLY_FLATTREE <<
2917 select IRQ_DOMAIN <<
2918 <<
2919 config UHI_BOOT <<
2920 bool <<
2921 <<
2922 config BUILTIN_DTB <<
2923 bool <<
2924 <<
2925 choice <<
2926 prompt "Kernel appended dtb support" <<
2927 depends on USE_OF <<
2928 default MIPS_NO_APPENDED_DTB <<
2929 <<
2930 config MIPS_NO_APPENDED_DTB <<
2931 bool "None" <<
2932 help <<
2933 Do not enable appended dtb <<
2934 <<
2935 config MIPS_ELF_APPENDED_DTB <<
2936 bool "vmlinux" <<
2937 help <<
2938 With this option, the boot <<
2939 DTB) included in the vmlinu <<
2940 it is empty and the DTB can <<
2941 objcopy: <<
2942 <<
2943 objcopy --update-section <<
2944 <<
2945 This is meant as a backward <<
2946 systems with a bootloader t <<
2947 the documented boot protoco <<
2948 <<
2949 config MIPS_RAW_APPENDED_DTB <<
2950 bool "vmlinux.bin or vmlinuz. <<
2951 help <<
2952 With this option, the boot <<
2953 DTB) appended to raw vmlinu <<
2954 (e.g. cat vmlinux.bin <file <<
2955 <<
2956 This is meant as a backward <<
2957 systems with a bootloader t <<
2958 the documented boot protoco <<
2959 <<
2960 Beware that there is very l <<
2961 this option being confused <<
2962 look like a DTB header afte <<
2963 to vmlinux.bin. Do not lea <<
2964 if you don't intend to alwa <<
2965 endchoice <<
2966 <<
2967 choice <<
2968 prompt "Kernel command line type" <<
2969 depends on !CMDLINE_OVERRIDE <<
2970 default MIPS_CMDLINE_FROM_DTB if USE_ <<
2971 !MAC <<
2972 !CAV <<
2973 default MIPS_CMDLINE_FROM_BOOTLOADER <<
2974 <<
2975 config MIPS_CMDLINE_FROM_DTB <<
2976 depends on USE_OF <<
2977 bool "Dtb kernel arguments if <<
2978 <<
2979 config MIPS_CMDLINE_DTB_EXTEND <<
2980 depends on USE_OF <<
2981 bool "Extend dtb kernel argum <<
2982 <<
2983 config MIPS_CMDLINE_FROM_BOOTLOADER <<
2984 bool "Bootloader kernel argum <<
2985 <<
2986 config MIPS_CMDLINE_BUILTIN_EXTEND <<
2987 depends on CMDLINE_BOOL <<
2988 bool "Extend builtin kernel a <<
2989 endchoice <<
2990 <<
2991 endmenu <<
2992 <<
2993 config LOCKDEP_SUPPORT <<
2994 bool 475 bool
2995 default y 476 default y
>> 477 depends on SPARC64 && PCI
2996 478
2997 config STACKTRACE_SUPPORT !! 479 config SPARC64_PCI_MSI
2998 bool 480 bool
2999 default y 481 default y
>> 482 depends on SPARC64_PCI && PCI_MSI
3000 483
3001 config PGTABLE_LEVELS <<
3002 int <<
3003 default 4 if PAGE_SIZE_4KB && MIPS_VA <<
3004 default 3 if 64BIT && (!PAGE_SIZE_64K <<
3005 default 2 <<
3006 <<
3007 config MIPS_AUTO_PFN_OFFSET <<
3008 bool <<
3009 <<
3010 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC <<
3011 <<
3012 config PCI_DRIVERS_GENERIC <<
3013 select PCI_DOMAINS_GENERIC if PCI <<
3014 bool <<
3015 <<
3016 config PCI_DRIVERS_LEGACY <<
3017 def_bool !PCI_DRIVERS_GENERIC <<
3018 select NO_GENERIC_PCI_IOPORT_MAP <<
3019 select PCI_DOMAINS if PCI <<
3020 <<
3021 # <<
3022 # ISA support is now enabled via select. Too <<
3023 # or other ISA chip on the board that users d <<
3024 # users to choose the right thing ... <<
3025 # <<
3026 config ISA <<
3027 bool <<
3028 <<
3029 config TC <<
3030 bool "TURBOchannel support" <<
3031 depends on MACH_DECSTATION <<
3032 help <<
3033 TURBOchannel is a DEC (now Compaq ( <<
3034 processors. TURBOchannel programmi <<
3035 at: <<
3036 <ftp://ftp.hp.com/pub/alphaserver/a <<
3037 and: <<
3038 <http://www.computer-refuge.org/cla <<
3039 Linux driver support status is docu <<
3040 <http://www.linux-mips.org/wiki/DEC <<
3041 <<
3042 config MMU <<
3043 bool <<
3044 default y <<
3045 <<
3046 config ARCH_MMAP_RND_BITS_MIN <<
3047 default 12 if 64BIT <<
3048 default 8 <<
3049 <<
3050 config ARCH_MMAP_RND_BITS_MAX <<
3051 default 18 if 64BIT <<
3052 default 15 <<
3053 <<
3054 config ARCH_MMAP_RND_COMPAT_BITS_MIN <<
3055 default 8 <<
3056 <<
3057 config ARCH_MMAP_RND_COMPAT_BITS_MAX <<
3058 default 15 <<
3059 <<
3060 config I8253 <<
3061 bool <<
3062 select CLKSRC_I8253 <<
3063 select CLKEVT_I8253 <<
3064 select MIPS_EXTERNAL_TIMER <<
3065 endmenu 484 endmenu
3066 485
3067 config TRAD_SIGNALS <<
3068 bool <<
3069 <<
3070 config MIPS32_COMPAT <<
3071 bool <<
3072 <<
3073 config COMPAT 486 config COMPAT
3074 bool 487 bool
3075 !! 488 depends on SPARC64
3076 config MIPS32_O32 !! 489 default y
3077 bool "Kernel support for o32 binaries !! 490 select HAVE_UID16
3078 depends on 64BIT <<
3079 select ARCH_WANT_OLD_COMPAT_IPC 491 select ARCH_WANT_OLD_COMPAT_IPC
3080 select COMPAT !! 492 select COMPAT_OLD_SIGACTION
3081 select MIPS32_COMPAT <<
3082 help <<
3083 Select this option if you want to r <<
3084 32-bit binaries as used by the 32-b <<
3085 existing binaries are in this forma <<
3086 <<
3087 If unsure, say Y. <<
3088 <<
3089 config MIPS32_N32 <<
3090 bool "Kernel support for n32 binaries <<
3091 depends on 64BIT <<
3092 select ARCH_WANT_COMPAT_IPC_PARSE_VER <<
3093 select COMPAT <<
3094 select MIPS32_COMPAT <<
3095 help <<
3096 Select this option if you want to r <<
3097 64-bit binaries using 32-bit quanti <<
3098 data that would normally be 64-bit. <<
3099 cases. <<
3100 <<
3101 If unsure, say N. <<
3102 <<
3103 config CC_HAS_MNO_BRANCH_LIKELY <<
3104 def_bool y <<
3105 depends on $(cc-option,-mno-branch-li <<
3106 <<
3107 # https://github.com/llvm/llvm-project/issues <<
3108 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH <<
3109 def_bool y if CC_IS_CLANG <<
3110 <<
3111 menu "Power management options" <<
3112 <<
3113 config ARCH_HIBERNATION_POSSIBLE <<
3114 def_bool y <<
3115 depends on SYS_SUPPORTS_HOTPLUG_CPU | <<
3116 <<
3117 config ARCH_SUSPEND_POSSIBLE <<
3118 def_bool y <<
3119 depends on SYS_SUPPORTS_HOTPLUG_CPU | <<
3120 <<
3121 source "kernel/power/Kconfig" <<
3122 <<
3123 endmenu <<
3124 <<
3125 config MIPS_EXTERNAL_TIMER <<
3126 bool <<
3127 <<
3128 menu "CPU Power Management" <<
3129 <<
3130 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIME <<
3131 source "drivers/cpufreq/Kconfig" <<
3132 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL <<
3133 <<
3134 source "drivers/cpuidle/Kconfig" <<
3135 <<
3136 endmenu <<
3137 <<
3138 source "arch/mips/kvm/Kconfig" <<
3139 493
3140 source "arch/mips/vdso/Kconfig" !! 494 source "drivers/sbus/char/Kconfig"
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