1 /* 1
2 * BRIEF MODULE DESCRIPTION
3 * Au1xx0 Power Management routines.
4 *
5 * Copyright 2001, 2008 MontaVista Software In
6 * Author: MontaVista Software, Inc. <source@m
7 *
8 * Some of the routines are right out of init
9 * copyrights apply here.
10 *
11 * This program is free software; you can red
12 * under the terms of the GNU General Publ
13 * Free Software Foundation; either version
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' A
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * MERCHANTABILITY AND FITNESS FOR A PARTICUL
19 * NO EVENT SHALL THE AUTHOR BE LIABL
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQU
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITU
22 * USE, DATA, OR PROFITS; OR BUSINESS INTER
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTR
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISIN
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSS
26 *
27 * You should have received a copy of the GN
28 * with this program; if not, write to the F
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 */
31
32 #include <linux/pm.h>
33 #include <linux/sysctl.h>
34 #include <linux/jiffies.h>
35
36 #include <linux/uaccess.h>
37 #include <asm/mach-au1x00/au1000.h>
38
39 /*
40 * We need to save/restore a bunch of core reg
41 * either volatile or reset to some state acro
42 * If reading a register doesn't provide a pro
43 * later restore, we have to provide a functio
44 * register and save a copy.
45 *
46 * We only have to save/restore registers that
47 * done as part of a driver pm_* function.
48 */
49 static unsigned int sleep_sys_clocks[5];
50 static unsigned int sleep_sys_pinfunc;
51 static unsigned int sleep_static_memctlr[4][3]
52
53
54 static void save_core_regs(void)
55 {
56 /* Clocks and PLLs. */
57 sleep_sys_clocks[0] = alchemy_rdsys(AU
58 sleep_sys_clocks[1] = alchemy_rdsys(AU
59 sleep_sys_clocks[2] = alchemy_rdsys(AU
60 sleep_sys_clocks[3] = alchemy_rdsys(AU
61 sleep_sys_clocks[4] = alchemy_rdsys(AU
62
63 /* pin mux config */
64 sleep_sys_pinfunc = alchemy_rdsys(AU10
65
66 /* Save the static memory controller c
67 sleep_static_memctlr[0][0] = alchemy_r
68 sleep_static_memctlr[0][1] = alchemy_r
69 sleep_static_memctlr[0][2] = alchemy_r
70 sleep_static_memctlr[1][0] = alchemy_r
71 sleep_static_memctlr[1][1] = alchemy_r
72 sleep_static_memctlr[1][2] = alchemy_r
73 sleep_static_memctlr[2][0] = alchemy_r
74 sleep_static_memctlr[2][1] = alchemy_r
75 sleep_static_memctlr[2][2] = alchemy_r
76 sleep_static_memctlr[3][0] = alchemy_r
77 sleep_static_memctlr[3][1] = alchemy_r
78 sleep_static_memctlr[3][2] = alchemy_r
79 }
80
81 static void restore_core_regs(void)
82 {
83 /* restore clock configuration. Writi
84 * stall a bit and stabilize other clo
85 * one of those Au1000 with a write-on
86 * have a valid value)
87 */
88 alchemy_wrsys(sleep_sys_clocks[0], AU1
89 alchemy_wrsys(sleep_sys_clocks[1], AU1
90 alchemy_wrsys(sleep_sys_clocks[2], AU1
91 alchemy_wrsys(sleep_sys_clocks[4], AU1
92 if (!au1xxx_cpu_has_pll_wo())
93 alchemy_wrsys(sleep_sys_clocks
94
95 alchemy_wrsys(sleep_sys_pinfunc, AU100
96
97 /* Restore the static memory controlle
98 alchemy_wrsmem(sleep_static_memctlr[0]
99 alchemy_wrsmem(sleep_static_memctlr[0]
100 alchemy_wrsmem(sleep_static_memctlr[0]
101 alchemy_wrsmem(sleep_static_memctlr[1]
102 alchemy_wrsmem(sleep_static_memctlr[1]
103 alchemy_wrsmem(sleep_static_memctlr[1]
104 alchemy_wrsmem(sleep_static_memctlr[2]
105 alchemy_wrsmem(sleep_static_memctlr[2]
106 alchemy_wrsmem(sleep_static_memctlr[2]
107 alchemy_wrsmem(sleep_static_memctlr[3]
108 alchemy_wrsmem(sleep_static_memctlr[3]
109 alchemy_wrsmem(sleep_static_memctlr[3]
110 }
111
112 void au_sleep(void)
113 {
114 save_core_regs();
115
116 switch (alchemy_get_cputype()) {
117 case ALCHEMY_CPU_AU1000:
118 case ALCHEMY_CPU_AU1500:
119 case ALCHEMY_CPU_AU1100:
120 alchemy_sleep_au1000();
121 break;
122 case ALCHEMY_CPU_AU1550:
123 case ALCHEMY_CPU_AU1200:
124 alchemy_sleep_au1550();
125 break;
126 case ALCHEMY_CPU_AU1300:
127 alchemy_sleep_au1300();
128 break;
129 }
130
131 restore_core_regs();
132 }
133
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