1 // SPDX-License-Identifier: GPL-2.0
2 /* OCTEON 3XXX DTS common parts. */
3
4 /dts-v1/;
5
6 / {
7 compatible = "cavium,octeon-3860";
8 #address-cells = <2>;
9 #size-cells = <2>;
10 interrupt-parent = <&ciu>;
11
12 soc@0 {
13 compatible = "simple-bus";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 ranges; /* Direct mapping */
17
18 ciu: interrupt-controller@1070
19 compatible = "cavium,o
20 interrupt-controller;
21 /* Interrupts are spec
22 * 1) Controller regis
23 * 2) Bit within the r
24 */
25 #interrupt-cells = <2>
26 reg = <0x10700 0x00000
27 };
28
29 gpio: gpio-controller@10700000
30 #gpio-cells = <2>;
31 compatible = "cavium,o
32 reg = <0x10700 0x00000
33 gpio-controller;
34 /* Interrupts are spec
35 * 1) GPIO pin number
36 * 2) Triggering (1 -
37 * 2 -
38 * 4 -
39 * 8 -
40 */
41 interrupt-controller;
42 #interrupt-cells = <2>
43 /* The GPIO pin connec
44 interrupts = <0 16>, <
45 <0 20>, <
46 <0 24>, <
47 <0 28>, <
48 };
49
50 smi0: mdio@1180000001800 {
51 compatible = "cavium,o
52 #address-cells = <1>;
53 #size-cells = <0>;
54 reg = <0x11800 0x00001
55 };
56
57 pip: pip@11800a0000000 {
58 compatible = "cavium,o
59 #address-cells = <1>;
60 #size-cells = <0>;
61 reg = <0x11800 0xa0000
62
63 interface@0 {
64 compatible = "
65 #address-cells
66 #size-cells =
67 reg = <0>; /*
68
69 ethernet@0 {
70 compat
71 reg =
72 local-
73 };
74 ethernet@1 {
75 compat
76 reg =
77 local-
78 };
79 ethernet@2 {
80 compat
81 reg =
82 local-
83 };
84 };
85
86 interface@1 {
87 compatible = "
88 #address-cells
89 #size-cells =
90 reg = <1>; /*
91 };
92 };
93
94 twsi0: i2c@1180000001000 {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 compatible = "cavium,o
98 reg = <0x11800 0x00001
99 interrupts = <0 45>;
100 clock-frequency = <100
101 };
102
103 uart0: serial@1180000000800 {
104 compatible = "cavium,o
105 reg = <0x11800 0x00000
106 clock-frequency = <0>;
107 current-speed = <11520
108 reg-shift = <3>;
109 interrupts = <0 34>;
110 };
111
112 bootbus: bootbus@1180000000000
113 compatible = "cavium,o
114 reg = <0x11800 0x00000
115 /* The chip select num
116 #address-cells = <2>;
117 /* The size of the chi
118 #size-cells = <1>;
119 ranges = <0 0 0x0 0x1
120 <1 0 0x10000
121 <2 0 0x10000
122 <3 0 0x10000
123 <4 0 0x0 0x1
124 <5 0 0x0 0x1
125 <6 0 0x0 0x1
126 <7 0 0x10000
127
128 cavium,cs-config@0 {
129 compatible = "
130 cavium,cs-inde
131 cavium,t-adr
132 cavium,t-ce
133 cavium,t-oe
134 cavium,t-we
135 cavium,t-rd-hl
136 cavium,t-wr-hl
137 cavium,t-pause
138 cavium,t-wait
139 cavium,t-page
140 cavium,t-rd-dl
141
142 cavium,pages
143 cavium,bus-wid
144 };
145 cavium,cs-config@4 {
146 compatible = "
147 cavium,cs-inde
148 cavium,t-adr
149 cavium,t-ce
150 cavium,t-oe
151 cavium,t-we
152 cavium,t-rd-hl
153 cavium,t-wr-hl
154 cavium,t-pause
155 cavium,t-wait
156 cavium,t-page
157 cavium,t-rd-dl
158
159 cavium,pages
160 cavium,bus-wid
161 };
162 cavium,cs-config@5 {
163 compatible = "
164 cavium,cs-inde
165 cavium,t-adr
166 cavium,t-ce
167 cavium,t-oe
168 cavium,t-we
169 cavium,t-rd-hl
170 cavium,t-wr-hl
171 cavium,t-pause
172 cavium,t-wait
173 cavium,t-page
174 cavium,t-rd-dl
175
176 cavium,pages
177 cavium,bus-wid
178 };
179 cavium,cs-config@6 {
180 compatible = "
181 cavium,cs-inde
182 cavium,t-adr
183 cavium,t-ce
184 cavium,t-oe
185 cavium,t-we
186 cavium,t-rd-hl
187 cavium,t-wr-hl
188 cavium,t-pause
189 cavium,t-wait
190 cavium,t-page
191 cavium,t-rd-dl
192
193 cavium,pages
194 cavium,wait-mo
195 cavium,bus-wid
196 };
197
198 flash0: nor@0,0 {
199 compatible = "
200 reg = <0 0 0x8
201 #address-cells
202 #size-cells =
203 };
204 };
205
206 dma0: dma-engine@1180000000100
207 compatible = "cavium,o
208 reg = <0x11800 0x00000
209 interrupts = <0 63>;
210 };
211
212 dma1: dma-engine@1180000000108
213 compatible = "cavium,o
214 reg = <0x11800 0x00000
215 interrupts = <0 63>;
216 };
217
218 usbn: usbn@1180068000000 {
219 compatible = "cavium,o
220 reg = <0x11800 0x68000
221 ranges; /* Direct mapp
222 #address-cells = <2>;
223 #size-cells = <2>;
224
225 usbc@16f0010000000 {
226 compatible = "
227 reg = <0x16f00
228 interrupts = <
229 };
230 };
231 };
232 };
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