1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3 /*
4 * OCTEON 68XX device tree skeleton.
5 *
6 * This device tree is pruned and patched by e
7 * use. Because of this, it contains a super-
8 * devices and properties.
9 */
10 / {
11 compatible = "cavium,octeon-6880";
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&ciu2>;
15
16 soc@0 {
17 compatible = "simple-bus";
18 #address-cells = <2>;
19 #size-cells = <2>;
20 ranges; /* Direct mapping */
21
22 ciu2: interrupt-controller@107
23 compatible = "cavium,o
24 interrupt-controller;
25 /* Interrupts are spec
26 * 1) Controller regis
27 * 2) Bit within the r
28 */
29 #address-cells = <0>;
30 #interrupt-cells = <2>
31 reg = <0x10701 0x00000
32 };
33
34 gpio: gpio-controller@10700000
35 #gpio-cells = <2>;
36 compatible = "cavium,o
37 reg = <0x10700 0x00000
38 gpio-controller;
39 /* Interrupts are spec
40 * 1) GPIO pin number
41 * 2) Triggering (1 -
42 * 2 -
43 * 4 -
44 * 8 -
45 */
46 interrupt-controller;
47 #interrupt-cells = <2>
48 /* The GPIO pins conne
49 interrupts = <7 0>, <
50 <7 4>, <
51 <7 8>, <
52 <7 12>, <
53 };
54
55 smi0: mdio@1180000003800 {
56 compatible = "cavium,o
57 #address-cells = <1>;
58 #size-cells = <0>;
59 reg = <0x11800 0x00003
60
61 phy0: ethernet-phy@6 {
62 compatible = "
63 marvell,reg-in
64 /* Fix
65 <2 0x1
66 /* Adj
67 <3 0x1
68 /* irq
69 <3 0x1
70 reg = <6>;
71 };
72
73 phy1: ethernet-phy@1 {
74 cavium,qlm-tri
75 reg = <1>;
76 compatible = "
77 marvell,reg-in
78 <3 0x1
79 <3 0x1
80 <3 0x1
81 };
82 phy2: ethernet-phy@2 {
83 cavium,qlm-tri
84 reg = <2>;
85 compatible = "
86 marvell,reg-in
87 <3 0x1
88 <3 0x1
89 <3 0x1
90 };
91 phy3: ethernet-phy@3 {
92 cavium,qlm-tri
93 reg = <3>;
94 compatible = "
95 marvell,reg-in
96 <3 0x1
97 <3 0x1
98 <3 0x1
99 };
100 phy4: ethernet-phy@4 {
101 cavium,qlm-tri
102 reg = <4>;
103 compatible = "
104 marvell,reg-in
105 <3 0x1
106 <3 0x1
107 <3 0x1
108 };
109 };
110
111 smi1: mdio@1180000003880 {
112 compatible = "cavium,o
113 #address-cells = <1>;
114 #size-cells = <0>;
115 reg = <0x11800 0x00003
116
117 phy41: ethernet-phy@1
118 cavium,qlm-tri
119 reg = <1>;
120 compatible = "
121 marvell,reg-in
122 <3 0x1
123 <3 0x1
124 <3 0x1
125 };
126 phy42: ethernet-phy@2
127 cavium,qlm-tri
128 reg = <2>;
129 compatible = "
130 marvell,reg-in
131 <3 0x1
132 <3 0x1
133 <3 0x1
134 };
135 phy43: ethernet-phy@3
136 cavium,qlm-tri
137 reg = <3>;
138 compatible = "
139 marvell,reg-in
140 <3 0x1
141 <3 0x1
142 <3 0x1
143 };
144 phy44: ethernet-phy@4
145 cavium,qlm-tri
146 reg = <4>;
147 compatible = "
148 marvell,reg-in
149 <3 0x1
150 <3 0x1
151 <3 0x1
152 };
153 };
154
155 smi2: mdio@1180000003900 {
156 compatible = "cavium,o
157 #address-cells = <1>;
158 #size-cells = <0>;
159 reg = <0x11800 0x00003
160
161 phy21: ethernet-phy@1
162 cavium,qlm-tri
163 reg = <1>;
164 compatible = "
165 marvell,reg-in
166 <3 0x1
167 <3 0x1
168 <3 0x1
169 };
170 phy22: ethernet-phy@2
171 cavium,qlm-tri
172 reg = <2>;
173 compatible = "
174 marvell,reg-in
175 <3 0x1
176 <3 0x1
177 <3 0x1
178 };
179 phy23: ethernet-phy@3
180 cavium,qlm-tri
181 reg = <3>;
182 compatible = "
183 marvell,reg-in
184 <3 0x1
185 <3 0x1
186 <3 0x1
187 };
188 phy24: ethernet-phy@4
189 cavium,qlm-tri
190 reg = <4>;
191 compatible = "
192 marvell,reg-in
193 <3 0x1
194 <3 0x1
195 <3 0x1
196 };
197 };
198
199 smi3: mdio@1180000003980 {
200 compatible = "cavium,o
201 #address-cells = <1>;
202 #size-cells = <0>;
203 reg = <0x11800 0x00003
204
205 phy11: ethernet-phy@1
206 cavium,qlm-tri
207 reg = <1>;
208 compatible = "
209 marvell,reg-in
210 <3 0x1
211 <3 0x1
212 <3 0x1
213 };
214 phy12: ethernet-phy@2
215 cavium,qlm-tri
216 reg = <2>;
217 compatible = "
218 marvell,reg-in
219 <3 0x1
220 <3 0x1
221 <3 0x1
222 };
223 phy13: ethernet-phy@3
224 cavium,qlm-tri
225 reg = <3>;
226 compatible = "
227 marvell,reg-in
228 <3 0x1
229 <3 0x1
230 <3 0x1
231 };
232 phy14: ethernet-phy@4
233 cavium,qlm-tri
234 reg = <4>;
235 compatible = "
236 marvell,reg-in
237 <3 0x1
238 <3 0x1
239 <3 0x1
240 };
241 };
242
243 mix0: ethernet@1070000100000 {
244 compatible = "cavium,o
245 reg = <0x10700 0x00100
246 <0x11800 0xE0000
247 <0x11800 0xE0000
248 <0x11800 0xE0002
249 cell-index = <0>;
250 interrupts = <6 40>, <
251 local-mac-address = [
252 phy-handle = <&phy0>;
253 };
254
255 pip: pip@11800a0000000 {
256 compatible = "cavium,o
257 #address-cells = <1>;
258 #size-cells = <0>;
259 reg = <0x11800 0xa0000
260
261 interface@4 {
262 compatible = "
263 #address-cells
264 #size-cells =
265 reg = <0x4>; /
266
267 ethernet@0 {
268 compat
269 reg =
270 local-
271 phy-ha
272 };
273 ethernet@1 {
274 compat
275 reg =
276 local-
277 phy-ha
278 };
279 ethernet@2 {
280 compat
281 reg =
282 local-
283 phy-ha
284 };
285 ethernet@3 {
286 compat
287 reg =
288 local-
289 phy-ha
290 };
291 };
292
293 interface@3 {
294 compatible = "
295 #address-cells
296 #size-cells =
297 reg = <0x3>; /
298
299 ethernet@0 {
300 compat
301 reg =
302 local-
303 phy-ha
304 };
305 ethernet@1 {
306 compat
307 reg =
308 local-
309 phy-ha
310 };
311 ethernet@2 {
312 compat
313 reg =
314 local-
315 phy-ha
316 };
317 ethernet@3 {
318 compat
319 reg =
320 local-
321 phy-ha
322 };
323 };
324
325 interface@2 {
326 compatible = "
327 #address-cells
328 #size-cells =
329 reg = <0x2>; /
330
331 ethernet@0 {
332 compat
333 reg =
334 local-
335 phy-ha
336 };
337 ethernet@1 {
338 compat
339 reg =
340 local-
341 phy-ha
342 };
343 ethernet@2 {
344 compat
345 reg =
346 local-
347 phy-ha
348 };
349 ethernet@3 {
350 compat
351 reg =
352 local-
353 phy-ha
354 };
355 };
356
357 interface@1 {
358 compatible = "
359 #address-cells
360 #size-cells =
361 reg = <0x1>; /
362
363 ethernet@0 {
364 compat
365 reg =
366 local-
367 };
368 };
369
370 interface@0 {
371 compatible = "
372 #address-cells
373 #size-cells =
374 reg = <0x0>; /
375
376 ethernet@0 {
377 compat
378 reg =
379 local-
380 phy-ha
381 };
382 ethernet@1 {
383 compat
384 reg =
385 local-
386 phy-ha
387 };
388 ethernet@2 {
389 compat
390 reg =
391 local-
392 phy-ha
393 };
394 ethernet@3 {
395 compat
396 reg =
397 local-
398 phy-ha
399 };
400 };
401 };
402
403 twsi0: i2c@1180000001000 {
404 #address-cells = <1>;
405 #size-cells = <0>;
406 compatible = "cavium,o
407 reg = <0x11800 0x00001
408 interrupts = <3 32>;
409 clock-frequency = <100
410
411 rtc@68 {
412 compatible = "
413 reg = <0x68>;
414 };
415 tmp@4c {
416 compatible = "
417 reg = <0x4c>;
418 };
419 };
420
421 twsi1: i2c@1180000001200 {
422 #address-cells = <1>;
423 #size-cells = <0>;
424 compatible = "cavium,o
425 reg = <0x11800 0x00001
426 interrupts = <3 33>;
427 clock-frequency = <100
428 };
429
430 uart0: serial@1180000000800 {
431 compatible = "cavium,o
432 reg = <0x11800 0x00000
433 clock-frequency = <0>;
434 current-speed = <11520
435 reg-shift = <3>;
436 interrupts = <3 36>;
437 };
438
439 uart1: serial@1180000000c00 {
440 compatible = "cavium,o
441 reg = <0x11800 0x00000
442 clock-frequency = <0>;
443 current-speed = <11520
444 reg-shift = <3>;
445 interrupts = <3 37>;
446 };
447
448 bootbus: bootbus@1180000000000
449 compatible = "cavium,o
450 reg = <0x11800 0x00000
451 /* The chip select num
452 #address-cells = <2>;
453 /* The size of the chi
454 #size-cells = <1>;
455 ranges = <0 0 0
456 <1 0 0x10000
457 <2 0 0x10000
458 <3 0 0x10000
459 <4 0 0
460 <5 0 0
461 <6 0 0
462 <7 0 0x10000
463
464 cavium,cs-config@0 {
465 compatible = "
466 cavium,cs-inde
467 cavium,t-adr
468 cavium,t-ce
469 cavium,t-oe
470 cavium,t-we
471 cavium,t-rd-hl
472 cavium,t-wr-hl
473 cavium,t-pause
474 cavium,t-wait
475 cavium,t-page
476 cavium,t-rd-dl
477
478 cavium,pages
479 cavium,bus-wid
480 };
481 cavium,cs-config@4 {
482 compatible = "
483 cavium,cs-inde
484 cavium,t-adr
485 cavium,t-ce
486 cavium,t-oe
487 cavium,t-we
488 cavium,t-rd-hl
489 cavium,t-wr-hl
490 cavium,t-pause
491 cavium,t-wait
492 cavium,t-page
493 cavium,t-rd-dl
494
495 cavium,pages
496 cavium,bus-wid
497 };
498 cavium,cs-config@5 {
499 compatible = "
500 cavium,cs-inde
501 cavium,t-adr
502 cavium,t-ce
503 cavium,t-oe
504 cavium,t-we
505 cavium,t-rd-hl
506 cavium,t-wr-hl
507 cavium,t-pause
508 cavium,t-wait
509 cavium,t-page
510 cavium,t-rd-dl
511
512 cavium,pages
513 cavium,bus-wid
514 };
515 cavium,cs-config@6 {
516 compatible = "
517 cavium,cs-inde
518 cavium,t-adr
519 cavium,t-ce
520 cavium,t-oe
521 cavium,t-we
522 cavium,t-rd-hl
523 cavium,t-wr-hl
524 cavium,t-pause
525 cavium,t-wait
526 cavium,t-page
527 cavium,t-rd-dl
528
529 cavium,pages
530 cavium,wait-mo
531 cavium,bus-wid
532 };
533
534 flash0: nor@0,0 {
535 compatible = "
536 reg = <0 0 0x8
537 #address-cells
538 #size-cells =
539
540 partition@0 {
541 label
542 reg =
543 read-o
544 };
545 partition@2000
546 label
547 reg =
548 };
549 partition@4000
550 label
551 reg =
552 };
553 partition@7fe0
554 label
555 reg =
556 read-o
557 };
558 };
559
560 led0: led-display@4,0
561 compatible = "
562 reg = <4 0x20
563 };
564
565 compact-flash@5,0 {
566 compatible = "
567 reg = <5 0 0x1
568 cavium,bus-wid
569 cavium,true-id
570 cavium,dma-eng
571 };
572 };
573
574 dma0: dma-engine@1180000000100
575 compatible = "cavium,o
576 reg = <0x11800 0x00000
577 interrupts = <0 63>;
578 };
579 dma1: dma-engine@1180000000108
580 compatible = "cavium,o
581 reg = <0x11800 0x00000
582 interrupts = <0 63>;
583 };
584
585 uctl: uctl@118006f000000 {
586 compatible = "cavium,o
587 reg = <0x11800 0x6f000
588 ranges; /* Direct mapp
589 #address-cells = <2>;
590 #size-cells = <2>;
591 /* 12MHz, 24MHz and 48
592 refclk-frequency = <12
593 /* Either "crystal" or
594 refclk-type = "crystal
595
596 ehci@16f0000000000 {
597 compatible = "
598 reg = <0x16f00
599 interrupts = <
600 big-endian-reg
601 };
602 ohci@16f0000000400 {
603 compatible = "
604 reg = <0x16f00
605 interrupts = <
606 big-endian-reg
607 };
608 };
609 };
610
611 aliases {
612 mix0 = &mix0;
613 pip = &pip;
614 smi0 = &smi0;
615 smi1 = &smi1;
616 smi2 = &smi2;
617 smi3 = &smi3;
618 twsi0 = &twsi0;
619 twsi1 = &twsi1;
620 uart0 = &uart0;
621 uart1 = &uart1;
622 uctl = &uctl;
623 led0 = &led0;
624 flash0 = &flash0;
625 };
626 };
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