1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4740-cgu 2 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h> 3 #include <dt-bindings/clock/ingenic,tcu.h>
4 4
5 / { 5 / {
6 #address-cells = <1>; 6 #address-cells = <1>;
7 #size-cells = <1>; 7 #size-cells = <1>;
8 compatible = "ingenic,jz4740"; 8 compatible = "ingenic,jz4740";
9 9
10 cpus { 10 cpus {
11 #address-cells = <1>; 11 #address-cells = <1>;
12 #size-cells = <0>; 12 #size-cells = <0>;
13 13
14 cpu0: cpu@0 { 14 cpu0: cpu@0 {
15 device_type = "cpu"; 15 device_type = "cpu";
16 compatible = "ingenic, 16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>; 17 reg = <0>;
18 18
19 clocks = <&cgu JZ4740_ 19 clocks = <&cgu JZ4740_CLK_CCLK>;
20 clock-names = "cpu"; 20 clock-names = "cpu";
21 }; 21 };
22 }; 22 };
23 23
24 cpuintc: interrupt-controller { 24 cpuintc: interrupt-controller {
25 #address-cells = <0>; 25 #address-cells = <0>;
26 #interrupt-cells = <1>; 26 #interrupt-cells = <1>;
27 interrupt-controller; 27 interrupt-controller;
28 compatible = "mti,cpu-interrup 28 compatible = "mti,cpu-interrupt-controller";
29 }; 29 };
30 30
31 intc: interrupt-controller@10001000 { 31 intc: interrupt-controller@10001000 {
32 compatible = "ingenic,jz4740-i 32 compatible = "ingenic,jz4740-intc";
33 reg = <0x10001000 0x14>; 33 reg = <0x10001000 0x14>;
34 34
35 interrupt-controller; 35 interrupt-controller;
36 #interrupt-cells = <1>; 36 #interrupt-cells = <1>;
37 37
38 interrupt-parent = <&cpuintc>; 38 interrupt-parent = <&cpuintc>;
39 interrupts = <2>; 39 interrupts = <2>;
40 }; 40 };
41 41
42 ext: ext { 42 ext: ext {
43 compatible = "fixed-clock"; 43 compatible = "fixed-clock";
44 #clock-cells = <0>; 44 #clock-cells = <0>;
45 }; 45 };
46 46
47 rtc: rtc { 47 rtc: rtc {
48 compatible = "fixed-clock"; 48 compatible = "fixed-clock";
49 #clock-cells = <0>; 49 #clock-cells = <0>;
50 clock-frequency = <32768>; 50 clock-frequency = <32768>;
51 }; 51 };
52 52
53 cgu: jz4740-cgu@10000000 { 53 cgu: jz4740-cgu@10000000 {
54 compatible = "ingenic,jz4740-c 54 compatible = "ingenic,jz4740-cgu";
55 reg = <0x10000000 0x100>; 55 reg = <0x10000000 0x100>;
56 56
57 clocks = <&ext>, <&rtc>; 57 clocks = <&ext>, <&rtc>;
58 clock-names = "ext", "rtc"; 58 clock-names = "ext", "rtc";
59 59
60 #clock-cells = <1>; 60 #clock-cells = <1>;
61 }; 61 };
62 62
63 tcu: timer@10002000 { 63 tcu: timer@10002000 {
64 compatible = "ingenic,jz4740-t 64 compatible = "ingenic,jz4740-tcu", "simple-mfd";
65 reg = <0x10002000 0x1000>; 65 reg = <0x10002000 0x1000>;
66 #address-cells = <1>; 66 #address-cells = <1>;
67 #size-cells = <1>; 67 #size-cells = <1>;
68 ranges = <0x0 0x10002000 0x100 68 ranges = <0x0 0x10002000 0x1000>;
69 69
70 #clock-cells = <1>; 70 #clock-cells = <1>;
71 71
72 clocks = <&cgu JZ4740_CLK_RTC> 72 clocks = <&cgu JZ4740_CLK_RTC>,
73 <&cgu JZ4740_CLK_EXT> 73 <&cgu JZ4740_CLK_EXT>,
74 <&cgu JZ4740_CLK_PCLK 74 <&cgu JZ4740_CLK_PCLK>,
75 <&cgu JZ4740_CLK_TCU> 75 <&cgu JZ4740_CLK_TCU>;
76 clock-names = "rtc", "ext", "p 76 clock-names = "rtc", "ext", "pclk", "tcu";
77 77
78 interrupt-controller; 78 interrupt-controller;
79 #interrupt-cells = <1>; 79 #interrupt-cells = <1>;
80 80
81 interrupt-parent = <&intc>; 81 interrupt-parent = <&intc>;
82 interrupts = <23 22 21>; 82 interrupts = <23 22 21>;
83 83
84 watchdog: watchdog@0 { 84 watchdog: watchdog@0 {
85 compatible = "ingenic, 85 compatible = "ingenic,jz4740-watchdog";
86 reg = <0x0 0xc>; 86 reg = <0x0 0xc>;
87 87
88 clocks = <&tcu TCU_CLK 88 clocks = <&tcu TCU_CLK_WDT>;
89 clock-names = "wdt"; 89 clock-names = "wdt";
90 }; 90 };
91 91
92 pwm: pwm@40 { 92 pwm: pwm@40 {
93 compatible = "ingenic, 93 compatible = "ingenic,jz4740-pwm";
94 reg = <0x40 0x80>; 94 reg = <0x40 0x80>;
95 95
96 #pwm-cells = <3>; 96 #pwm-cells = <3>;
97 97
98 clocks = <&tcu TCU_CLK 98 clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
99 <&tcu TCU_CLK 99 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
100 <&tcu TCU_CLK 100 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
101 <&tcu TCU_CLK 101 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
102 clock-names = "timer0" 102 clock-names = "timer0", "timer1", "timer2", "timer3",
103 "timer4" 103 "timer4", "timer5", "timer6", "timer7";
104 }; 104 };
105 }; 105 };
106 106
107 rtc_dev: rtc@10003000 { 107 rtc_dev: rtc@10003000 {
108 compatible = "ingenic,jz4740-r 108 compatible = "ingenic,jz4740-rtc";
109 reg = <0x10003000 0x40>; 109 reg = <0x10003000 0x40>;
110 110
111 interrupt-parent = <&intc>; 111 interrupt-parent = <&intc>;
112 interrupts = <15>; 112 interrupts = <15>;
113 113
114 clocks = <&cgu JZ4740_CLK_RTC> 114 clocks = <&cgu JZ4740_CLK_RTC>;
115 clock-names = "rtc"; 115 clock-names = "rtc";
116 }; 116 };
117 117
118 pinctrl: pin-controller@10010000 { 118 pinctrl: pin-controller@10010000 {
119 compatible = "ingenic,jz4740-p 119 compatible = "ingenic,jz4740-pinctrl";
120 reg = <0x10010000 0x400>; 120 reg = <0x10010000 0x400>;
121 121
122 #address-cells = <1>; 122 #address-cells = <1>;
123 #size-cells = <0>; 123 #size-cells = <0>;
124 124
125 gpa: gpio@0 { 125 gpa: gpio@0 {
126 compatible = "ingenic, 126 compatible = "ingenic,jz4740-gpio";
127 reg = <0>; 127 reg = <0>;
128 128
129 gpio-controller; 129 gpio-controller;
130 gpio-ranges = <&pinctr 130 gpio-ranges = <&pinctrl 0 0 32>;
131 #gpio-cells = <2>; 131 #gpio-cells = <2>;
132 132
133 interrupt-controller; 133 interrupt-controller;
134 #interrupt-cells = <2> 134 #interrupt-cells = <2>;
135 135
136 interrupt-parent = <&i 136 interrupt-parent = <&intc>;
137 interrupts = <28>; 137 interrupts = <28>;
138 }; 138 };
139 139
140 gpb: gpio@1 { 140 gpb: gpio@1 {
141 compatible = "ingenic, 141 compatible = "ingenic,jz4740-gpio";
142 reg = <1>; 142 reg = <1>;
143 143
144 gpio-controller; 144 gpio-controller;
145 gpio-ranges = <&pinctr 145 gpio-ranges = <&pinctrl 0 32 32>;
146 #gpio-cells = <2>; 146 #gpio-cells = <2>;
147 147
148 interrupt-controller; 148 interrupt-controller;
149 #interrupt-cells = <2> 149 #interrupt-cells = <2>;
150 150
151 interrupt-parent = <&i 151 interrupt-parent = <&intc>;
152 interrupts = <27>; 152 interrupts = <27>;
153 }; 153 };
154 154
155 gpc: gpio@2 { 155 gpc: gpio@2 {
156 compatible = "ingenic, 156 compatible = "ingenic,jz4740-gpio";
157 reg = <2>; 157 reg = <2>;
158 158
159 gpio-controller; 159 gpio-controller;
160 gpio-ranges = <&pinctr 160 gpio-ranges = <&pinctrl 0 64 32>;
161 #gpio-cells = <2>; 161 #gpio-cells = <2>;
162 162
163 interrupt-controller; 163 interrupt-controller;
164 #interrupt-cells = <2> 164 #interrupt-cells = <2>;
165 165
166 interrupt-parent = <&i 166 interrupt-parent = <&intc>;
167 interrupts = <26>; 167 interrupts = <26>;
168 }; 168 };
169 169
170 gpd: gpio@3 { 170 gpd: gpio@3 {
171 compatible = "ingenic, 171 compatible = "ingenic,jz4740-gpio";
172 reg = <3>; 172 reg = <3>;
173 173
174 gpio-controller; 174 gpio-controller;
175 gpio-ranges = <&pinctr 175 gpio-ranges = <&pinctrl 0 96 32>;
176 #gpio-cells = <2>; 176 #gpio-cells = <2>;
177 177
178 interrupt-controller; 178 interrupt-controller;
179 #interrupt-cells = <2> 179 #interrupt-cells = <2>;
180 180
181 interrupt-parent = <&i 181 interrupt-parent = <&intc>;
182 interrupts = <25>; 182 interrupts = <25>;
183 }; 183 };
184 }; 184 };
185 185
186 aic: audio-controller@10020000 { 186 aic: audio-controller@10020000 {
187 compatible = "ingenic,jz4740-i 187 compatible = "ingenic,jz4740-i2s";
188 reg = <0x10020000 0x38>; 188 reg = <0x10020000 0x38>;
189 189
190 #sound-dai-cells = <0>; 190 #sound-dai-cells = <0>;
191 191
192 interrupt-parent = <&intc>; 192 interrupt-parent = <&intc>;
193 interrupts = <18>; 193 interrupts = <18>;
194 194
195 clocks = <&cgu JZ4740_CLK_AIC> 195 clocks = <&cgu JZ4740_CLK_AIC>, <&cgu JZ4740_CLK_I2S>;
196 clock-names = "aic", "i2s"; 196 clock-names = "aic", "i2s";
197 197
198 dmas = <&dmac 25 0xffffffff>, 198 dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
199 dma-names = "rx", "tx"; 199 dma-names = "rx", "tx";
200 }; 200 };
201 201
202 codec: audio-codec@100200a4 { 202 codec: audio-codec@100200a4 {
203 compatible = "ingenic,jz4740-c 203 compatible = "ingenic,jz4740-codec";
204 reg = <0x10020080 0x8>; 204 reg = <0x10020080 0x8>;
205 205
206 #sound-dai-cells = <0>; 206 #sound-dai-cells = <0>;
207 207
208 clocks = <&cgu JZ4740_CLK_AIC> 208 clocks = <&cgu JZ4740_CLK_AIC>;
209 clock-names = "aic"; 209 clock-names = "aic";
210 }; 210 };
211 211
212 mmc: mmc@10021000 { 212 mmc: mmc@10021000 {
213 compatible = "ingenic,jz4740-m 213 compatible = "ingenic,jz4740-mmc";
214 reg = <0x10021000 0x1000>; 214 reg = <0x10021000 0x1000>;
215 215
216 clocks = <&cgu JZ4740_CLK_MMC> 216 clocks = <&cgu JZ4740_CLK_MMC>;
217 clock-names = "mmc"; 217 clock-names = "mmc";
218 218
219 interrupt-parent = <&intc>; 219 interrupt-parent = <&intc>;
220 interrupts = <14>; 220 interrupts = <14>;
221 221
222 dmas = <&dmac 27 0xffffffff>, 222 dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
223 dma-names = "rx", "tx"; 223 dma-names = "rx", "tx";
224 224
225 cap-sd-highspeed; 225 cap-sd-highspeed;
226 cap-mmc-highspeed; 226 cap-mmc-highspeed;
227 cap-sdio-irq; 227 cap-sdio-irq;
228 }; 228 };
229 229
230 uart0: serial@10030000 { 230 uart0: serial@10030000 {
231 compatible = "ingenic,jz4740-u 231 compatible = "ingenic,jz4740-uart";
232 reg = <0x10030000 0x100>; 232 reg = <0x10030000 0x100>;
233 233
234 interrupt-parent = <&intc>; 234 interrupt-parent = <&intc>;
235 interrupts = <9>; 235 interrupts = <9>;
236 236
237 clocks = <&ext>, <&cgu JZ4740_ 237 clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
238 clock-names = "baud", "module" 238 clock-names = "baud", "module";
239 }; 239 };
240 240
241 uart1: serial@10031000 { 241 uart1: serial@10031000 {
242 compatible = "ingenic,jz4740-u 242 compatible = "ingenic,jz4740-uart";
243 reg = <0x10031000 0x100>; 243 reg = <0x10031000 0x100>;
244 244
245 interrupt-parent = <&intc>; 245 interrupt-parent = <&intc>;
246 interrupts = <8>; 246 interrupts = <8>;
247 247
248 clocks = <&ext>, <&cgu JZ4740_ 248 clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
249 clock-names = "baud", "module" 249 clock-names = "baud", "module";
250 }; 250 };
251 251
252 adc: adc@10070000 { 252 adc: adc@10070000 {
253 compatible = "ingenic,jz4740-a 253 compatible = "ingenic,jz4740-adc";
254 reg = <0x10070000 0x30>; 254 reg = <0x10070000 0x30>;
255 #io-channel-cells = <1>; 255 #io-channel-cells = <1>;
256 256
257 clocks = <&cgu JZ4740_CLK_ADC> 257 clocks = <&cgu JZ4740_CLK_ADC>;
258 clock-names = "adc"; 258 clock-names = "adc";
259 259
260 interrupt-parent = <&intc>; 260 interrupt-parent = <&intc>;
261 interrupts = <12>; 261 interrupts = <12>;
262 }; 262 };
263 263
264 nemc: memory-controller@13010000 { 264 nemc: memory-controller@13010000 {
265 compatible = "ingenic,jz4740-n 265 compatible = "ingenic,jz4740-nemc";
266 reg = <0x13010000 0x54>; 266 reg = <0x13010000 0x54>;
267 #address-cells = <2>; 267 #address-cells = <2>;
268 #size-cells = <1>; 268 #size-cells = <1>;
269 ranges = <1 0 0x18000000 0x400 269 ranges = <1 0 0x18000000 0x4000000>,
270 <2 0 0x14000000 0x400 270 <2 0 0x14000000 0x4000000>,
271 <3 0 0x0c000000 0x400 271 <3 0 0x0c000000 0x4000000>,
272 <4 0 0x08000000 0x400 272 <4 0 0x08000000 0x4000000>;
273 273
274 clocks = <&cgu JZ4740_CLK_MCLK 274 clocks = <&cgu JZ4740_CLK_MCLK>;
275 }; 275 };
276 276
277 ecc: ecc-controller@13010100 { 277 ecc: ecc-controller@13010100 {
278 compatible = "ingenic,jz4740-e 278 compatible = "ingenic,jz4740-ecc";
279 reg = <0x13010100 0x2C>; 279 reg = <0x13010100 0x2C>;
280 280
281 clocks = <&cgu JZ4740_CLK_MCLK 281 clocks = <&cgu JZ4740_CLK_MCLK>;
282 }; 282 };
283 283
284 dmac: dma-controller@13020000 { 284 dmac: dma-controller@13020000 {
285 compatible = "ingenic,jz4740-d 285 compatible = "ingenic,jz4740-dma";
286 reg = <0x13020000 0xbc>, <0x13 286 reg = <0x13020000 0xbc>, <0x13020300 0x14>;
287 #dma-cells = <2>; 287 #dma-cells = <2>;
288 288
289 interrupt-parent = <&intc>; 289 interrupt-parent = <&intc>;
290 interrupts = <20>; 290 interrupts = <20>;
291 291
292 clocks = <&cgu JZ4740_CLK_DMA> 292 clocks = <&cgu JZ4740_CLK_DMA>;
293 }; 293 };
294 294
295 uhc: usb@13030000 { 295 uhc: usb@13030000 {
296 compatible = "ingenic,jz4740-o 296 compatible = "ingenic,jz4740-ohci", "generic-ohci";
297 reg = <0x13030000 0x1000>; 297 reg = <0x13030000 0x1000>;
298 298
299 clocks = <&cgu JZ4740_CLK_UHC> 299 clocks = <&cgu JZ4740_CLK_UHC>;
300 assigned-clocks = <&cgu JZ4740 300 assigned-clocks = <&cgu JZ4740_CLK_UHC>;
301 assigned-clock-rates = <480000 301 assigned-clock-rates = <48000000>;
302 302
303 interrupt-parent = <&intc>; 303 interrupt-parent = <&intc>;
304 interrupts = <3>; 304 interrupts = <3>;
305 305
306 status = "disabled"; 306 status = "disabled";
307 }; 307 };
308 308
309 udc: usb@13040000 { 309 udc: usb@13040000 {
310 compatible = "ingenic,jz4740-m 310 compatible = "ingenic,jz4740-musb";
311 reg = <0x13040000 0x10000>; 311 reg = <0x13040000 0x10000>;
312 312
313 interrupt-parent = <&intc>; 313 interrupt-parent = <&intc>;
314 interrupts = <24>; 314 interrupts = <24>;
315 interrupt-names = "mc"; 315 interrupt-names = "mc";
316 316
317 clocks = <&cgu JZ4740_CLK_UDC> 317 clocks = <&cgu JZ4740_CLK_UDC>;
318 clock-names = "udc"; 318 clock-names = "udc";
319 }; 319 };
320 320
321 lcd: lcd-controller@13050000 { 321 lcd: lcd-controller@13050000 {
322 compatible = "ingenic,jz4740-l 322 compatible = "ingenic,jz4740-lcd";
323 reg = <0x13050000 0x60>; /* LC 323 reg = <0x13050000 0x60>; /* LCDCMD1+4 */
324 324
325 interrupt-parent = <&intc>; 325 interrupt-parent = <&intc>;
326 interrupts = <30>; 326 interrupts = <30>;
327 327
328 clocks = <&cgu JZ4740_CLK_LCD_ 328 clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
329 clock-names = "lcd_pclk", "lcd 329 clock-names = "lcd_pclk", "lcd";
330 }; 330 };
331 }; 331 };
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