1 /dts-v1/; 1 /dts-v1/;
2 2
3 / { 3 / {
4 #address-cells = <1>; 4 #address-cells = <1>;
5 #size-cells = <1>; 5 #size-cells = <1>;
6 compatible = "ni,169445"; 6 compatible = "ni,169445";
7 7
8 cpus { 8 cpus {
9 #address-cells = <1>; 9 #address-cells = <1>;
10 #size-cells = <0>; 10 #size-cells = <0>;
11 cpu@0 { 11 cpu@0 {
12 device_type = "cpu"; 12 device_type = "cpu";
13 compatible = "mti,mips 13 compatible = "mti,mips14KEc";
14 clocks = <&baseclk>; 14 clocks = <&baseclk>;
15 reg = <0>; 15 reg = <0>;
16 }; 16 };
17 }; 17 };
18 18
19 memory@0 { 19 memory@0 {
20 device_type = "memory"; 20 device_type = "memory";
21 reg = <0x0 0x10000000>; 21 reg = <0x0 0x10000000>;
22 }; 22 };
23 23
24 baseclk: baseclock { 24 baseclk: baseclock {
25 compatible = "fixed-clock"; 25 compatible = "fixed-clock";
26 #clock-cells = <0>; 26 #clock-cells = <0>;
27 clock-frequency = <50000000>; 27 clock-frequency = <50000000>;
28 }; 28 };
29 29
30 cpu_intc: interrupt-controller { 30 cpu_intc: interrupt-controller {
31 #address-cells = <0>; 31 #address-cells = <0>;
32 compatible = "mti,cpu-interrup 32 compatible = "mti,cpu-interrupt-controller";
33 interrupt-controller; 33 interrupt-controller;
34 #interrupt-cells = <1>; 34 #interrupt-cells = <1>;
35 }; 35 };
36 36
37 ahb@1f300000 { 37 ahb@1f300000 {
38 compatible = "simple-bus"; 38 compatible = "simple-bus";
39 #address-cells = <1>; 39 #address-cells = <1>;
40 #size-cells = <1>; 40 #size-cells = <1>;
41 ranges = <0x0 0x1f300000 0x80F 41 ranges = <0x0 0x1f300000 0x80FFF>;
42 42
43 gpio1: gpio@10 { 43 gpio1: gpio@10 {
44 compatible = "ni,16944 44 compatible = "ni,169445-nand-gpio";
45 reg = <0x10 0x4>; 45 reg = <0x10 0x4>;
46 reg-names = "dat"; 46 reg-names = "dat";
47 gpio-controller; 47 gpio-controller;
48 #gpio-cells = <2>; 48 #gpio-cells = <2>;
49 }; 49 };
50 50
51 gpio2: gpio@14 { 51 gpio2: gpio@14 {
52 compatible = "ni,16944 52 compatible = "ni,169445-nand-gpio";
53 reg = <0x14 0x4>; 53 reg = <0x14 0x4>;
54 reg-names = "dat"; 54 reg-names = "dat";
55 gpio-controller; 55 gpio-controller;
56 #gpio-cells = <2>; 56 #gpio-cells = <2>;
57 no-output; 57 no-output;
58 }; 58 };
59 59
60 nand@0 { 60 nand@0 {
61 compatible = "gpio-con 61 compatible = "gpio-control-nand";
62 nand-on-flash-bbt; 62 nand-on-flash-bbt;
63 nand-ecc-mode = "soft_ 63 nand-ecc-mode = "soft_bch";
64 nand-ecc-step-size = < 64 nand-ecc-step-size = <512>;
65 nand-ecc-strength = <4 65 nand-ecc-strength = <4>;
66 reg = <0x0 4>; 66 reg = <0x0 4>;
67 gpios = <&gpio2 0 0>, 67 gpios = <&gpio2 0 0>, /* rdy */
68 <&gpio1 1 0>, 68 <&gpio1 1 0>, /* nce */
69 <&gpio1 2 0>, 69 <&gpio1 2 0>, /* ale */
70 <&gpio1 3 0>, 70 <&gpio1 3 0>, /* cle */
71 <&gpio1 4 0>; 71 <&gpio1 4 0>; /* nwp */
72 }; 72 };
73 73
74 serial@80000 { 74 serial@80000 {
75 compatible = "ns16550a 75 compatible = "ns16550a";
76 reg = <0x80000 0x1000> 76 reg = <0x80000 0x1000>;
77 interrupt-parent = <&c 77 interrupt-parent = <&cpu_intc>;
78 interrupts = <6>; 78 interrupts = <6>;
79 clocks = <&baseclk>; 79 clocks = <&baseclk>;
80 reg-shift = <0>; 80 reg-shift = <0>;
81 }; 81 };
82 82
83 ethernet@40000 { 83 ethernet@40000 {
84 compatible = "snps,dwm 84 compatible = "snps,dwmac-4.10a";
85 interrupt-parent = <&c 85 interrupt-parent = <&cpu_intc>;
86 interrupts = <5>; 86 interrupts = <5>;
87 interrupt-names = "mac 87 interrupt-names = "macirq";
88 reg = <0x40000 0x2000> 88 reg = <0x40000 0x2000>;
89 clock-names = "stmmace 89 clock-names = "stmmaceth", "pclk";
90 clocks = <&baseclk>, < 90 clocks = <&baseclk>, <&baseclk>;
91 91
92 phy-mode = "rgmii"; 92 phy-mode = "rgmii";
93 93
94 fixed-link { 94 fixed-link {
95 speed = <1000> 95 speed = <1000>;
96 full-duplex; 96 full-duplex;
97 }; 97 };
98 }; 98 };
99 }; 99 };
100 }; 100 };
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