1 # SPDX-License-Identifier: GPL-2.0 2 if CPU_CAVIUM_OCTEON 3 4 config CAVIUM_CN63XXP1 5 bool "Enable CN63XXP1 errata workaroun 6 default "n" 7 help 8 The CN63XXP1 chip requires build tim 9 function reliably, select this optio 10 workarounds will cause a slight decr 11 non-CN63XXP1 hardware, so it is reco 12 unless it is known the workarounds a 13 14 config CAVIUM_OCTEON_CVMSEG_SIZE 15 int "Number of L1 cache lines reserved 16 range 0 54 17 default 0 if !CAVIUM_OCTEON_SOC 18 default 1 if CAVIUM_OCTEON_SOC 19 help 20 CVMSEG LM is a segment that accesses 21 local memory; the larger CVMSEG is, 22 This selects the size of CVMSEG LM, 23 legally range is from zero to 54 cac 24 between zero and 6192 bytes). 25 26 endif # CPU_CAVIUM_OCTEON 27 28 if CAVIUM_OCTEON_SOC 29 30 config CAVIUM_OCTEON_LOCK_L2 31 bool "Lock often used kernel code in t 32 default "y" 33 help 34 Enable locking parts of the kernel i 35 36 config CAVIUM_OCTEON_LOCK_L2_TLB 37 bool "Lock the TLB handler in L2" 38 depends on CAVIUM_OCTEON_LOCK_L2 39 default "y" 40 help 41 Lock the low level TLB fast path int 42 43 config CAVIUM_OCTEON_LOCK_L2_EXCEPTION 44 bool "Lock the exception handler in L2 45 depends on CAVIUM_OCTEON_LOCK_L2 46 default "y" 47 help 48 Lock the low level exception handler 49 50 config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRU 51 bool "Lock the interrupt handler in L2 52 depends on CAVIUM_OCTEON_LOCK_L2 53 default "y" 54 help 55 Lock the low level interrupt handler 56 57 config CAVIUM_OCTEON_LOCK_L2_INTERRUPT 58 bool "Lock the 2nd level interrupt han 59 depends on CAVIUM_OCTEON_LOCK_L2 60 default "y" 61 help 62 Lock the 2nd level interrupt handler 63 64 config CAVIUM_OCTEON_LOCK_L2_MEMCPY 65 bool "Lock memcpy() in L2" 66 depends on CAVIUM_OCTEON_LOCK_L2 67 default "y" 68 help 69 Lock the kernel's implementation of 70 71 config CAVIUM_RESERVE32 72 int "Memory to reserve for user proces 73 range 0 1536 74 default "0" 75 help 76 Reserve a shared memory region for u 77 memory buffers. This is required for 78 send and receive packets directly. A 79 memory mapping /dev/mem for the addr 80 optimal performance with HugeTLBs, k 81 megabytes. 82 83 config OCTEON_ILM 84 tristate "Module to measure interrupt 85 help 86 This driver is a module to measure i 87 the CIU Timers on Octeon. 88 89 To compile this driver as a module, 90 will be called octeon-ilm 91 92 endif # CAVIUM_OCTEON_SOC
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