1 # SPDX-License-Identifier: GPL-2.0 <<
2 if CPU_CAVIUM_OCTEON 1 if CPU_CAVIUM_OCTEON
3 2
4 config CAVIUM_CN63XXP1 3 config CAVIUM_CN63XXP1
5 bool "Enable CN63XXP1 errata workaroun 4 bool "Enable CN63XXP1 errata workarounds"
6 default "n" 5 default "n"
7 help 6 help
8 The CN63XXP1 chip requires build tim 7 The CN63XXP1 chip requires build time workarounds to
9 function reliably, select this optio 8 function reliably, select this option to enable them. These
10 workarounds will cause a slight decr 9 workarounds will cause a slight decrease in performance on
11 non-CN63XXP1 hardware, so it is reco 10 non-CN63XXP1 hardware, so it is recommended to select "n"
12 unless it is known the workarounds a 11 unless it is known the workarounds are needed.
13 12
14 config CAVIUM_OCTEON_CVMSEG_SIZE 13 config CAVIUM_OCTEON_CVMSEG_SIZE
15 int "Number of L1 cache lines reserved 14 int "Number of L1 cache lines reserved for CVMSEG memory"
16 range 0 54 15 range 0 54
17 default 0 if !CAVIUM_OCTEON_SOC !! 16 default 1
18 default 1 if CAVIUM_OCTEON_SOC <<
19 help 17 help
20 CVMSEG LM is a segment that accesses 18 CVMSEG LM is a segment that accesses portions of the dcache as a
21 local memory; the larger CVMSEG is, 19 local memory; the larger CVMSEG is, the smaller the cache is.
22 This selects the size of CVMSEG LM, 20 This selects the size of CVMSEG LM, which is in cache blocks. The
23 legally range is from zero to 54 cac 21 legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
24 between zero and 6192 bytes). 22 between zero and 6192 bytes).
25 23
26 endif # CPU_CAVIUM_OCTEON 24 endif # CPU_CAVIUM_OCTEON
27 25
28 if CAVIUM_OCTEON_SOC 26 if CAVIUM_OCTEON_SOC
29 27
>> 28 config CAVIUM_OCTEON_2ND_KERNEL
>> 29 bool "Build the kernel to be used as a 2nd kernel on the same chip"
>> 30 default "n"
>> 31 help
>> 32 This option configures this kernel to be linked at a different
>> 33 address and use the 2nd uart for output. This allows a kernel built
>> 34 with this option to be run at the same time as one built without this
>> 35 option.
>> 36
30 config CAVIUM_OCTEON_LOCK_L2 37 config CAVIUM_OCTEON_LOCK_L2
31 bool "Lock often used kernel code in t 38 bool "Lock often used kernel code in the L2"
32 default "y" 39 default "y"
33 help 40 help
34 Enable locking parts of the kernel i 41 Enable locking parts of the kernel into the L2 cache.
35 42
36 config CAVIUM_OCTEON_LOCK_L2_TLB 43 config CAVIUM_OCTEON_LOCK_L2_TLB
37 bool "Lock the TLB handler in L2" 44 bool "Lock the TLB handler in L2"
38 depends on CAVIUM_OCTEON_LOCK_L2 45 depends on CAVIUM_OCTEON_LOCK_L2
39 default "y" 46 default "y"
40 help 47 help
41 Lock the low level TLB fast path int 48 Lock the low level TLB fast path into L2.
42 49
43 config CAVIUM_OCTEON_LOCK_L2_EXCEPTION 50 config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
44 bool "Lock the exception handler in L2 51 bool "Lock the exception handler in L2"
45 depends on CAVIUM_OCTEON_LOCK_L2 52 depends on CAVIUM_OCTEON_LOCK_L2
46 default "y" 53 default "y"
47 help 54 help
48 Lock the low level exception handler 55 Lock the low level exception handler into L2.
49 56
50 config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRU 57 config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
51 bool "Lock the interrupt handler in L2 58 bool "Lock the interrupt handler in L2"
52 depends on CAVIUM_OCTEON_LOCK_L2 59 depends on CAVIUM_OCTEON_LOCK_L2
53 default "y" 60 default "y"
54 help 61 help
55 Lock the low level interrupt handler 62 Lock the low level interrupt handler into L2.
56 63
57 config CAVIUM_OCTEON_LOCK_L2_INTERRUPT 64 config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
58 bool "Lock the 2nd level interrupt han 65 bool "Lock the 2nd level interrupt handler in L2"
59 depends on CAVIUM_OCTEON_LOCK_L2 66 depends on CAVIUM_OCTEON_LOCK_L2
60 default "y" 67 default "y"
61 help 68 help
62 Lock the 2nd level interrupt handler 69 Lock the 2nd level interrupt handler in L2.
63 70
64 config CAVIUM_OCTEON_LOCK_L2_MEMCPY 71 config CAVIUM_OCTEON_LOCK_L2_MEMCPY
65 bool "Lock memcpy() in L2" 72 bool "Lock memcpy() in L2"
66 depends on CAVIUM_OCTEON_LOCK_L2 73 depends on CAVIUM_OCTEON_LOCK_L2
67 default "y" 74 default "y"
68 help 75 help
69 Lock the kernel's implementation of 76 Lock the kernel's implementation of memcpy() into L2.
70 77
71 config CAVIUM_RESERVE32 !! 78 config IOMMU_HELPER
72 int "Memory to reserve for user proces !! 79 bool
73 range 0 1536 !! 80
74 default "0" !! 81 config NEED_SG_DMA_LENGTH
75 help !! 82 bool
76 Reserve a shared memory region for u !! 83
77 memory buffers. This is required for !! 84 config SWIOTLB
78 send and receive packets directly. A !! 85 def_bool y
79 memory mapping /dev/mem for the addr !! 86 select IOMMU_HELPER
80 optimal performance with HugeTLBs, k !! 87 select NEED_SG_DMA_LENGTH
81 megabytes. <<
82 88
83 config OCTEON_ILM 89 config OCTEON_ILM
84 tristate "Module to measure interrupt 90 tristate "Module to measure interrupt latency using Octeon CIU Timer"
85 help 91 help
86 This driver is a module to measure i 92 This driver is a module to measure interrupt latency using the
87 the CIU Timers on Octeon. 93 the CIU Timers on Octeon.
88 94
89 To compile this driver as a module, 95 To compile this driver as a module, choose M here. The module
90 will be called octeon-ilm 96 will be called octeon-ilm
91 97
92 endif # CAVIUM_OCTEON_SOC 98 endif # CAVIUM_OCTEON_SOC
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