1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 if CPU_CAVIUM_OCTEON 2 if CPU_CAVIUM_OCTEON
3 3
4 config CAVIUM_CN63XXP1 4 config CAVIUM_CN63XXP1
5 bool "Enable CN63XXP1 errata workaroun 5 bool "Enable CN63XXP1 errata workarounds"
6 default "n" 6 default "n"
7 help 7 help
8 The CN63XXP1 chip requires build tim 8 The CN63XXP1 chip requires build time workarounds to
9 function reliably, select this optio 9 function reliably, select this option to enable them. These
10 workarounds will cause a slight decr 10 workarounds will cause a slight decrease in performance on
11 non-CN63XXP1 hardware, so it is reco 11 non-CN63XXP1 hardware, so it is recommended to select "n"
12 unless it is known the workarounds a 12 unless it is known the workarounds are needed.
13 13
14 config CAVIUM_OCTEON_CVMSEG_SIZE 14 config CAVIUM_OCTEON_CVMSEG_SIZE
15 int "Number of L1 cache lines reserved 15 int "Number of L1 cache lines reserved for CVMSEG memory"
16 range 0 54 16 range 0 54
17 default 0 if !CAVIUM_OCTEON_SOC !! 17 default 1
18 default 1 if CAVIUM_OCTEON_SOC <<
19 help 18 help
20 CVMSEG LM is a segment that accesses 19 CVMSEG LM is a segment that accesses portions of the dcache as a
21 local memory; the larger CVMSEG is, 20 local memory; the larger CVMSEG is, the smaller the cache is.
22 This selects the size of CVMSEG LM, 21 This selects the size of CVMSEG LM, which is in cache blocks. The
23 legally range is from zero to 54 cac 22 legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
24 between zero and 6192 bytes). 23 between zero and 6192 bytes).
25 24
26 endif # CPU_CAVIUM_OCTEON 25 endif # CPU_CAVIUM_OCTEON
27 26
28 if CAVIUM_OCTEON_SOC 27 if CAVIUM_OCTEON_SOC
29 28
30 config CAVIUM_OCTEON_LOCK_L2 29 config CAVIUM_OCTEON_LOCK_L2
31 bool "Lock often used kernel code in t 30 bool "Lock often used kernel code in the L2"
32 default "y" 31 default "y"
33 help 32 help
34 Enable locking parts of the kernel i 33 Enable locking parts of the kernel into the L2 cache.
35 34
36 config CAVIUM_OCTEON_LOCK_L2_TLB 35 config CAVIUM_OCTEON_LOCK_L2_TLB
37 bool "Lock the TLB handler in L2" 36 bool "Lock the TLB handler in L2"
38 depends on CAVIUM_OCTEON_LOCK_L2 37 depends on CAVIUM_OCTEON_LOCK_L2
39 default "y" 38 default "y"
40 help 39 help
41 Lock the low level TLB fast path int 40 Lock the low level TLB fast path into L2.
42 41
43 config CAVIUM_OCTEON_LOCK_L2_EXCEPTION 42 config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
44 bool "Lock the exception handler in L2 43 bool "Lock the exception handler in L2"
45 depends on CAVIUM_OCTEON_LOCK_L2 44 depends on CAVIUM_OCTEON_LOCK_L2
46 default "y" 45 default "y"
47 help 46 help
48 Lock the low level exception handler 47 Lock the low level exception handler into L2.
49 48
50 config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRU 49 config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
51 bool "Lock the interrupt handler in L2 50 bool "Lock the interrupt handler in L2"
52 depends on CAVIUM_OCTEON_LOCK_L2 51 depends on CAVIUM_OCTEON_LOCK_L2
53 default "y" 52 default "y"
54 help 53 help
55 Lock the low level interrupt handler 54 Lock the low level interrupt handler into L2.
56 55
57 config CAVIUM_OCTEON_LOCK_L2_INTERRUPT 56 config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
58 bool "Lock the 2nd level interrupt han 57 bool "Lock the 2nd level interrupt handler in L2"
59 depends on CAVIUM_OCTEON_LOCK_L2 58 depends on CAVIUM_OCTEON_LOCK_L2
60 default "y" 59 default "y"
61 help 60 help
62 Lock the 2nd level interrupt handler 61 Lock the 2nd level interrupt handler in L2.
63 62
64 config CAVIUM_OCTEON_LOCK_L2_MEMCPY 63 config CAVIUM_OCTEON_LOCK_L2_MEMCPY
65 bool "Lock memcpy() in L2" 64 bool "Lock memcpy() in L2"
66 depends on CAVIUM_OCTEON_LOCK_L2 65 depends on CAVIUM_OCTEON_LOCK_L2
67 default "y" 66 default "y"
68 help 67 help
69 Lock the kernel's implementation of 68 Lock the kernel's implementation of memcpy() into L2.
70 <<
71 config CAVIUM_RESERVE32 <<
72 int "Memory to reserve for user proces <<
73 range 0 1536 <<
74 default "0" <<
75 help <<
76 Reserve a shared memory region for u <<
77 memory buffers. This is required for <<
78 send and receive packets directly. A <<
79 memory mapping /dev/mem for the addr <<
80 optimal performance with HugeTLBs, k <<
81 megabytes. <<
82 69
83 config OCTEON_ILM 70 config OCTEON_ILM
84 tristate "Module to measure interrupt 71 tristate "Module to measure interrupt latency using Octeon CIU Timer"
85 help 72 help
86 This driver is a module to measure i 73 This driver is a module to measure interrupt latency using the
87 the CIU Timers on Octeon. 74 the CIU Timers on Octeon.
88 75
89 To compile this driver as a module, 76 To compile this driver as a module, choose M here. The module
90 will be called octeon-ilm 77 will be called octeon-ilm
91 78
92 endif # CAVIUM_OCTEON_SOC 79 endif # CAVIUM_OCTEON_SOC
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