1 /***********************license start********* 1
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistr
10 * it under the terms of the GNU General Publi
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that i
14 * AS-IS and WITHOUT ANY WARRANTY; without eve
15 * of MERCHANTABILITY or FITNESS FOR A PARTICU
16 * NONINFRINGEMENT. See the GNU General Publi
17 * details.
18 *
19 * You should have received a copy of the GNU
20 * along with this file; if not, write to the
21 * Foundation, Inc., 51 Franklin St, Fifth Flo
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a dif
25 * Contact Cavium Networks for more informatio
26 ***********************license end***********
27
28 /*
29 * Support library for the hardware Packet Out
30 */
31
32 #include <asm/octeon/octeon.h>
33
34 #include <asm/octeon/cvmx-config.h>
35 #include <asm/octeon/cvmx-pko.h>
36 #include <asm/octeon/cvmx-helper.h>
37
38 /*
39 * Internal state of packet output
40 */
41
42 static int __cvmx_pko_int(int interface, int i
43 {
44 switch (interface) {
45 case 0:
46 return index;
47 case 1:
48 return 4;
49 case 2:
50 return index + 0x08;
51 case 3:
52 return index + 0x0c;
53 case 4:
54 return index + 0x10;
55 case 5:
56 return 0x1c;
57 case 6:
58 return 0x1d;
59 case 7:
60 return 0x1e;
61 case 8:
62 return 0x1f;
63 default:
64 return -1;
65 }
66 }
67
68 static void __cvmx_pko_iport_config(int pko_po
69 {
70 int queue;
71 const int num_queues = 1;
72 const int base_queue = pko_port;
73 const int static_priority_end = 1;
74 const int static_priority_base = 1;
75
76 for (queue = 0; queue < num_queues; qu
77 union cvmx_pko_mem_iqueue_ptrs
78 cvmx_cmd_queue_result_t cmd_re
79 uint64_t *buf_ptr;
80
81 config.u64 = 0;
82 config.s.index = queu
83 config.s.qid = base
84 config.s.ipid = pko_
85 config.s.tail = (que
86 config.s.s_tail = (que
87 config.s.static_p = (sta
88 config.s.static_q = (que
89 config.s.qos_mask = 0xff
90
91 cmd_res = cvmx_cmd_queue_initi
92 CVMX_CMD_QUEUE
93 CVMX_PKO_MAX_Q
94 CVMX_FPA_OUTPU
95 (CVMX_FPA_OUTP
96 CVMX_PKO_COMM
97
98 WARN(cmd_res,
99 "%s: cmd_res=%d pko_port=
100 __func__, (int)cmd_res
101 num_queues, queue);
102
103 buf_ptr = (uint64_t *)cvmx_cmd
104 CVMX_CMD_QUEUE
105 config.s.buf_ptr = cvmx_ptr_to
106 CVMX_SYNCWS;
107 cvmx_write_csr(CVMX_PKO_MEM_IQ
108 }
109 }
110
111 static void __cvmx_pko_queue_alloc_o68(void)
112 {
113 int port;
114
115 for (port = 0; port < 48; port++)
116 __cvmx_pko_iport_config(port);
117 }
118
119 static void __cvmx_pko_port_map_o68(void)
120 {
121 int port;
122 int interface, index;
123 cvmx_helper_interface_mode_t mode;
124 union cvmx_pko_mem_iport_ptrs config;
125
126 /*
127 * Initialize every iport with the inv
128 */
129 config.u64 = 0;
130 config.s.eid = 31; /* Invalid */
131 for (port = 0; port < 128; port++) {
132 config.s.ipid = port;
133 cvmx_write_csr(CVMX_PKO_MEM_IP
134 }
135
136 /*
137 * Set up PKO_MEM_IPORT_PTRS
138 */
139 for (port = 0; port < 48; port++) {
140 interface = cvmx_helper_get_in
141 index = cvmx_helper_get_interf
142 mode = cvmx_helper_interface_g
143 if (mode == CVMX_HELPER_INTERF
144 continue;
145
146 config.s.ipid = port;
147 config.s.qos_mask = 0xff;
148 config.s.crc = 1;
149 config.s.min_pkt = 1;
150 config.s.intr = __cvmx_pko_int
151 config.s.eid = config.s.intr;
152 config.s.pipe = (mode == CVMX_
153 index : port;
154 cvmx_write_csr(CVMX_PKO_MEM_IP
155 }
156 }
157
158 static void __cvmx_pko_chip_init(void)
159 {
160 int i;
161
162 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
163 __cvmx_pko_port_map_o68();
164 __cvmx_pko_queue_alloc_o68();
165 return;
166 }
167
168 /*
169 * Initialize queues
170 */
171 for (i = 0; i < CVMX_PKO_MAX_OUTPUT_QU
172 const uint64_t priority = 8;
173
174 cvmx_pko_config_port(CVMX_PKO_
175 &priority
176 }
177 }
178
179 /*
180 * Call before any other calls to initialize t
181 * output system. This does chip global confi
182 * done by one core.
183 */
184
185 void cvmx_pko_initialize_global(void)
186 {
187 union cvmx_pko_reg_cmd_buf config;
188
189 /*
190 * Set the size of the PKO command buf
191 * 64bit words. This allows the normal
192 * aligned and never span a command wo
193 */
194 config.u64 = 0;
195 config.s.pool = CVMX_FPA_OUTPUT_BUFFER
196 config.s.size = CVMX_FPA_OUTPUT_BUFFER
197
198 cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, c
199
200 /*
201 * Chip-specific setup.
202 */
203 __cvmx_pko_chip_init();
204
205 /*
206 * If we aren't using all of the queue
207 * internal memory.
208 */
209 if (OCTEON_IS_MODEL(OCTEON_CN38XX) ||
210 || OCTEON_IS_MODEL(OCTEON_CN56XX)
211 || OCTEON_IS_MODEL(OCTEON_CN52XX))
212 int num_interfaces = cvmx_help
213 int last_port =
214 cvmx_helper_get_last_ipd_p
215 int max_queues =
216 cvmx_pko_get_base_queue(la
217 cvmx_pko_get_num_queues(la
218 if (OCTEON_IS_MODEL(OCTEON_CN3
219 if (max_queues <= 32)
220 cvmx_write_csr
221 else if (max_queues <=
222 cvmx_write_csr
223 } else {
224 if (max_queues <= 64)
225 cvmx_write_csr
226 else if (max_queues <=
227 cvmx_write_csr
228 }
229 }
230 }
231
232 /*
233 * Enables the packet output hardware. It must
234 * configured.
235 */
236 void cvmx_pko_enable(void)
237 {
238 union cvmx_pko_reg_flags flags;
239
240 flags.u64 = cvmx_read_csr(CVMX_PKO_REG
241 if (flags.s.ena_pko)
242 cvmx_dprintf
243 ("Warning: Enabling PKO wh
244
245 flags.s.ena_dwb = 1;
246 flags.s.ena_pko = 1;
247 /*
248 * always enable big endian for 3-word
249 * for 2-word.
250 */
251 flags.s.store_be = 1;
252 cvmx_write_csr(CVMX_PKO_REG_FLAGS, fla
253 }
254
255 /*
256 * Disables the packet output. Does not affect
257 */
258 void cvmx_pko_disable(void)
259 {
260 union cvmx_pko_reg_flags pko_reg_flags
261 pko_reg_flags.u64 = cvmx_read_csr(CVMX
262 pko_reg_flags.s.ena_pko = 0;
263 cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko
264 }
265 EXPORT_SYMBOL_GPL(cvmx_pko_disable);
266
267 /*
268 * Reset the packet output.
269 */
270 static void __cvmx_pko_reset(void)
271 {
272 union cvmx_pko_reg_flags pko_reg_flags
273 pko_reg_flags.u64 = cvmx_read_csr(CVMX
274 pko_reg_flags.s.reset = 1;
275 cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko
276 }
277
278 /*
279 * Shutdown and free resources required by pac
280 */
281 void cvmx_pko_shutdown(void)
282 {
283 union cvmx_pko_mem_queue_ptrs config;
284 int queue;
285
286 cvmx_pko_disable();
287
288 for (queue = 0; queue < CVMX_PKO_MAX_O
289 config.u64 = 0;
290 config.s.tail = 1;
291 config.s.index = 0;
292 config.s.port = CVMX_PKO_MEM_Q
293 config.s.queue = queue & 0x7f;
294 config.s.qos_mask = 0;
295 config.s.buf_ptr = 0;
296 if (!OCTEON_IS_MODEL(OCTEON_CN
297 union cvmx_pko_reg_que
298 config1.u64 = 0;
299 config1.s.qid7 = queue
300 cvmx_write_csr(CVMX_PK
301 }
302 cvmx_write_csr(CVMX_PKO_MEM_QU
303 cvmx_cmd_queue_shutdown(CVMX_C
304 }
305 __cvmx_pko_reset();
306 }
307 EXPORT_SYMBOL_GPL(cvmx_pko_shutdown);
308
309 /*
310 * Configure a output port and the associated
311 *
312 * @port: Port to configure.
313 * @base_queue: First queue number to associat
314 * @num_queues: Number of queues to associate
315 * @priority: Array of priority levels for e
316 * allowed to be 0-8. A valu
317 * of a value of 1. A value
318 * will be participated in.
319 * on the fly while the pko
320 * indicates that static pri
321 * priority is used all queu
322 * contiguous starting at th
323 * queues have higher priori
324 * There must be num_queues
325 */
326 cvmx_pko_status_t cvmx_pko_config_port(uint64_
327 uint64_
328 const u
329 {
330 cvmx_pko_status_t result_code;
331 uint64_t queue;
332 union cvmx_pko_mem_queue_ptrs config;
333 union cvmx_pko_reg_queue_ptrs1 config1
334 int static_priority_base = -1;
335 int static_priority_end = -1;
336
337 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
338 return CVMX_PKO_SUCCESS;
339
340 if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS
341 && (port != CVMX_PKO_MEM_QUEUE_PTR
342 cvmx_dprintf("ERROR: cvmx_pko_
343 (unsigned long lo
344 return CVMX_PKO_INVALID_PORT;
345 }
346
347 if (base_queue + num_queues > CVMX_PKO
348 cvmx_dprintf
349 ("ERROR: cvmx_pko_config_p
350 (unsigned long long)(base
351 return CVMX_PKO_INVALID_QUEUE;
352 }
353
354 if (port != CVMX_PKO_MEM_QUEUE_PTRS_IL
355 /*
356 * Validate the static queue p
357 * static_priority_base and st
358 * accordingly.
359 */
360 for (queue = 0; queue < num_qu
361 /* Find first queue of
362 if (static_priority_ba
363 && priority[queue]
364 CVMX_PKO_QUEUE_STA
365 static_priorit
366 /* Find last queue of
367 if (static_priority_ba
368 && static_priority
369 && priority[queue]
370 && queue)
371 static_priorit
372 else if (static_priori
373 && static_pri
374 && queue == n
375 /* all queues
376 static_priorit
377 /*
378 * Check to make sure
379 * queues are contiguo
380 * cases of static pri
381 * queue 0.
382 */
383 if (static_priority_en
384 && (int)queue > st
385 && priority[queue]
386 CVMX_PKO_QUEUE_STA
387 cvmx_dprintf("
388 "
389 "
390 "
391 (int)q
392 return CVMX_PK
393 }
394 }
395 if (static_priority_base > 0)
396 cvmx_dprintf("ERROR: c
397 "priority
398 "queue. s
399 static_priorit
400 return CVMX_PKO_INVALI
401 }
402 #if 0
403 cvmx_dprintf("Port %d: Static
404 "end: %d\n", port
405 static_priority_base,
406 #endif
407 }
408 /*
409 * At this point, static_priority_base
410 * are either both -1, or are valid st
411 * numbers.
412 */
413
414 result_code = CVMX_PKO_SUCCESS;
415
416 #ifdef PKO_DEBUG
417 cvmx_dprintf("num queues: %d (%lld,%ll
418 CVMX_PKO_QUEUES_PER_PORT_
419 CVMX_PKO_QUEUES_PER_PORT_
420 #endif
421
422 for (queue = 0; queue < num_queues; qu
423 uint64_t *buf_ptr = NULL;
424
425 config1.u64 = 0;
426 config1.s.idx3 = queue >> 3;
427 config1.s.qid7 = (base_queue +
428
429 config.u64 = 0;
430 config.s.tail = queue == (num_
431 config.s.index = queue;
432 config.s.port = port;
433 config.s.queue = base_queue +
434
435 if (!cvmx_octeon_is_pass1()) {
436 config.s.static_p = st
437 config.s.static_q = (i
438 config.s.s_tail = (int
439 }
440 /*
441 * Convert the priority into a
442 * to space the bits out evenl
443 * get grouped up
444 */
445 switch ((int)priority[queue])
446 case 0:
447 config.s.qos_mask = 0x
448 break;
449 case 1:
450 config.s.qos_mask = 0x
451 break;
452 case 2:
453 config.s.qos_mask = 0x
454 break;
455 case 3:
456 config.s.qos_mask = 0x
457 break;
458 case 4:
459 config.s.qos_mask = 0x
460 break;
461 case 5:
462 config.s.qos_mask = 0x
463 break;
464 case 6:
465 config.s.qos_mask = 0x
466 break;
467 case 7:
468 config.s.qos_mask = 0x
469 break;
470 case 8:
471 config.s.qos_mask = 0x
472 break;
473 case CVMX_PKO_QUEUE_STATIC_PRI
474 if (!cvmx_octeon_is_pa
475 config.s.qos_m
476 break;
477 }
478 fallthrough; /* to
479 default:
480 cvmx_dprintf("ERROR: c
481 "priority
482 (unsigned long
483 config.s.qos_mask = 0x
484 result_code = CVMX_PKO
485 break;
486 }
487
488 if (port != CVMX_PKO_MEM_QUEUE
489 cvmx_cmd_queue_result_
490 cvmx_cmd_queue_ini
491
492
493
494
495
496
497
498 if (cmd_res != CVMX_CM
499 switch (cmd_re
500 case CVMX_CMD_
501 cvmx_d
502
503
504
505 return
506 case CVMX_CMD_
507 cvmx_d
508 ("
509 return
510 case CVMX_CMD_
511 default:
512 cvmx_d
513 ("
514 return
515 }
516 }
517
518 buf_ptr =
519 (uint64_t *)
520 cvmx_cmd_queue_buf
521
522 config.s.buf_ptr = cvm
523 } else
524 config.s.buf_ptr = 0;
525
526 CVMX_SYNCWS;
527
528 if (!OCTEON_IS_MODEL(OCTEON_CN
529 cvmx_write_csr(CVMX_PK
530 cvmx_write_csr(CVMX_PKO_MEM_QU
531 }
532
533 return result_code;
534 }
535
536 #ifdef PKO_DEBUG
537 /*
538 * Show map of ports -> queues for different c
539 */
540 void cvmx_pko_show_queue_map()
541 {
542 int core, port;
543 int pko_output_ports = 36;
544
545 cvmx_dprintf("port");
546 for (port = 0; port < pko_output_ports
547 cvmx_dprintf("%3d ", port);
548 cvmx_dprintf("\n");
549
550 for (core = 0; core < CVMX_MAX_CORES;
551 cvmx_dprintf("\n%2d: ", core);
552 for (port = 0; port < pko_outp
553 cvmx_dprintf("%3d ",
554 cvmx_pko_
555
556 }
557 }
558 cvmx_dprintf("\n");
559 }
560 #endif
561
562 /*
563 * Rate limit a PKO port to a max packets/sec.
564 * supported on CN51XX and higher, excluding C
565 *
566 * @port: Port to rate limit
567 * @packets_s: Maximum packet/sec
568 * @burst: Maximum number of packets to bu
569 * limiting cuts in.
570 *
571 * Returns Zero on success, negative on failur
572 */
573 int cvmx_pko_rate_limit_packets(int port, int
574 {
575 union cvmx_pko_mem_port_rate0 pko_mem_
576 union cvmx_pko_mem_port_rate1 pko_mem_
577
578 pko_mem_port_rate0.u64 = 0;
579 pko_mem_port_rate0.s.pid = port;
580 pko_mem_port_rate0.s.rate_pkt =
581 cvmx_sysinfo_get()->cpu_clock_hz /
582 /* No cost per word since we are limit
583 pko_mem_port_rate0.s.rate_word = 0;
584
585 pko_mem_port_rate1.u64 = 0;
586 pko_mem_port_rate1.s.pid = port;
587 pko_mem_port_rate1.s.rate_lim =
588 ((uint64_t) pko_mem_port_rate0.s.r
589
590 cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0
591 cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1
592 return 0;
593 }
594
595 /*
596 * Rate limit a PKO port to a max bits/sec. Th
597 * supported on CN51XX and higher, excluding C
598 *
599 * @port: Port to rate limit
600 * @bits_s: PKO rate limit in bits/sec
601 * @burst: Maximum number of bits to burst be
602 * limiting cuts in.
603 *
604 * Returns Zero on success, negative on failur
605 */
606 int cvmx_pko_rate_limit_bits(int port, uint64_
607 {
608 union cvmx_pko_mem_port_rate0 pko_mem_
609 union cvmx_pko_mem_port_rate1 pko_mem_
610 uint64_t clock_rate = cvmx_sysinfo_get
611 uint64_t tokens_per_bit = clock_rate *
612
613 pko_mem_port_rate0.u64 = 0;
614 pko_mem_port_rate0.s.pid = port;
615 /*
616 * Each packet has a 12 bytes of inter
617 * preamble, and a 4 byte CRC. These a
618 * per word count. Multiply by 8 to co
619 * by 256 for limit granularity.
620 */
621 pko_mem_port_rate0.s.rate_pkt = (12 +
622 /* Each 8 byte word has 64bits */
623 pko_mem_port_rate0.s.rate_word = 64 *
624
625 pko_mem_port_rate1.u64 = 0;
626 pko_mem_port_rate1.s.pid = port;
627 pko_mem_port_rate1.s.rate_lim = tokens
628
629 cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0
630 cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1
631 return 0;
632 }
633
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