1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) 1995, 1996, 1997 Paul M. Anto
4 * Copyright (C) 2000, 2001, 2002, 2003, 2005
5 *
6 * Written by Ralf Baechle and Andreas Busse,
7 * support by Paul Antoine and Harald Koerfgen
8 *
9 * completely rewritten:
10 * Copyright (C) 1998 Harald Koerfgen
11 *
12 * Rewritten extensively for controller-driven
13 * by Maciej W. Rozycki.
14 */
15
16 #include <asm/addrspace.h>
17 #include <asm/asm.h>
18 #include <asm/mipsregs.h>
19 #include <asm/regdef.h>
20 #include <asm/stackframe.h>
21
22 #include <asm/dec/interrupts.h>
23 #include <asm/dec/ioasic_addrs.h>
24 #include <asm/dec/ioasic_ints.h>
25 #include <asm/dec/kn01.h>
26 #include <asm/dec/kn02.h>
27 #include <asm/dec/kn02xa.h>
28 #include <asm/dec/kn03.h>
29
30 #define KN02_CSR_BASE CKSEG1ADDR(KN0
31 #define KN02XA_IOASIC_BASE CKSEG1ADDR(KN0
32 #define KN03_IOASIC_BASE CKSEG1ADDR(KN0
33
34 .text
35 .set noreorder
36 /*
37 * plat_irq_dispatch: Interrupt handler for DE
38 *
39 * We follow the model in the Indy interrupt c
40 * says: a lot of complication here is taken a
41 *
42 * 1) We handle one interrupt and return, sitt
43 * and moving across all the pending IRQ bi
44 * register is _NOT_ the answer, the common
45 * pending IRQ so optimize in that directio
46 *
47 * 2) We need not check against bits in the st
48 * IRQ mask, that would make this routine s
49 *
50 * 3) Linux only thinks in terms of all IRQs o
51 * off, nothing in between like BSD spl() b
52 *
53 * Furthermore, the IRQs on the DECstations lo
54 * software IRQs which we don't use at all) li
55 *
56 * DS2100/3100's, aka kn01, aka Pmax:
57 *
58 * MIPS IRQ Source
59 * -------- ------
60 * 0 Software (ignored)
61 * 1 Software (ignored)
62 * 2 SCSI
63 * 3 Lance Ethernet
64 * 4 DZ11 serial
65 * 5 RTC
66 * 6 Memory Controller & Vi
67 * 7 FPU
68 *
69 * DS5000/200, aka kn02, aka 3max:
70 *
71 * MIPS IRQ Source
72 * -------- ------
73 * 0 Software (ignored)
74 * 1 Software (ignored)
75 * 2 TurboChannel
76 * 3 RTC
77 * 4 Reserved
78 * 5 Memory Controller
79 * 6 Reserved
80 * 7 FPU
81 *
82 * DS5000/1xx's, aka kn02ba, aka 3min:
83 *
84 * MIPS IRQ Source
85 * -------- ------
86 * 0 Software (ignored)
87 * 1 Software (ignored)
88 * 2 TurboChannel Slot 0
89 * 3 TurboChannel Slot 1
90 * 4 TurboChannel Slot 2
91 * 5 TurboChannel Slot 3 (A
92 * 6 Halt button
93 * 7 FPU/R4k timer
94 *
95 * DS5000/2x's, aka kn02ca, aka maxine:
96 *
97 * MIPS IRQ Source
98 * -------- ------
99 * 0 Software (ignored)
100 * 1 Software (ignored)
101 * 2 Periodic Interrupt (10
102 * 3 RTC
103 * 4 I/O write timeout
104 * 5 TurboChannel (ASIC)
105 * 6 Halt Keycode from Acce
106 * 7 FPU/R4k timer
107 *
108 * DS5000/2xx's, aka kn03, aka 3maxplus:
109 *
110 * MIPS IRQ Source
111 * -------- ------
112 * 0 Software (ignored)
113 * 1 Software (ignored)
114 * 2 System Board (ASIC)
115 * 3 RTC
116 * 4 Reserved
117 * 5 Memory
118 * 6 Halt Button
119 * 7 FPU/R4k timer
120 *
121 * We handle the IRQ according to _our_ priori
122 * then we just return. If multiple IRQs are
123 * just take another exception, big deal.
124 */
125 .align 5
126 NESTED(plat_irq_dispatch, PT_S
127 .set noreorder
128
129 /*
130 * Get pending Interrupts
131 */
132 mfc0 t0,CP0_CAUSE
133 mfc0 t1,CP0_STATUS
134 #if defined(CONFIG_32BIT) && defined(CONFIG_MI
135 lw t2,cpu_fpu_mask
136 #endif
137 andi t0,ST0_IM
138 and t0,t1
139
140 beqz t0,spurious
141
142 #if defined(CONFIG_32BIT) && defined(CONFIG_MI
143 and t2,t0
144 bnez t2,fpu
145 #endif
146
147 /*
148 * Find irq with highest prior
149 */
150 # open coded PTR_LA t1, cpu_ma
151 #if defined(CONFIG_32BIT) || defined(KBUILD_64
152 # open coded la t1, cpu_mask_n
153 lui t1, %hi(cpu_mask_nr_tb
154 addiu t1, %lo(cpu_mask_nr_tb
155 #else
156 #error GCC `-msym32' option required for 64-bi
157 #endif
158 1: lw t2,(t1)
159 nop
160 and t2,t0
161 beqz t2,1b
162 addu t1,2*PTRSIZE
163
164 /*
165 * Do the low-level stuff
166 */
167 lw a0,(-PTRSIZE)(t1)
168 nop
169 bgez a0,handle_it
170
171 nop
172 jr a0
173
174 lui t2,(KN03_IOASIC_BASE>>
175
176
177 /*
178 * Handle "IRQ Controller" Interrupts
179 * Masked Interrupts are still visible and hav
180 */
181 FEXPORT(kn02_io_int)
182 lui t0,(KN02_CSR_BASE>>16)
183
184 lw t0,(t0)
185 nop
186 andi t1,t0,KN02_IRQ_ALL
187 b 1f
188 srl t0,16
189
190 FEXPORT(kn02xa_io_int)
191 lui t2,(KN02XA_IOASIC_BASE
192
193
194 FEXPORT(kn03_io_int)
195 lw t0,IO_REG_SIR(t2)
196 lw t1,IO_REG_SIMR(t2)
197 nop
198
199 1: and t0,t1
200
201 beqz t0,spurious
202
203 /*
204 * Find irq with highest prior
205 */
206 # open coded PTR_LA t1,asic_ma
207 #if defined(CONFIG_32BIT) || defined(KBUILD_64
208 # open coded la t1, asic_mask_
209 lui t1, %hi(asic_mask_nr_t
210 addiu t1, %lo(asic_mask_nr_t
211 #else
212 #error GCC `-msym32' option required for 64-bi
213 #endif
214 2: lw t2,(t1)
215 nop
216 and t2,t0
217 beq zero,t2,2b
218 addu t1,2*PTRSIZE
219
220 /*
221 * Do the low-level stuff
222 */
223 lw a0,%lo(-PTRSIZE)(t1)
224 nop
225 bgez a0,handle_it
226
227 nop
228 jr a0
229 nop
230
231 /*
232 * Dispatch low-priority interrupts. We recon
233 * bits again, which looks like a lose, but it
234 * simple and O(log n), so it gets compensated
235 */
236 FEXPORT(cpu_all_int)
237 li a0,DEC_CPU_IRQ_BASE
238 srl t0,CAUSEB_IP
239 li t1,CAUSEF_IP>>CAUSEB_I
240 b 1f
241 li t2,4
242
243 FEXPORT(kn02_all_int)
244 li a0,KN02_IRQ_BASE
245 li t1,KN02_IRQ_ALL
246 b 1f
247 li t2,4
248
249 FEXPORT(asic_all_int)
250 li a0,IO_IRQ_BASE
251 li t1,IO_IRQ_ALL
252 b 1f
253 li t2,8
254
255 /*
256 * Dispatch DMA interrupts -- O(log n).
257 */
258 FEXPORT(asic_dma_int)
259 li a0,IO_IRQ_BASE+IO_INR_
260 srl t0,IO_INR_DMA
261 li t1,IO_IRQ_DMA>>IO_INR_
262 li t2,8
263
264 /*
265 * Find irq with highest prior
266 * Highest irq number takes pr
267 */
268 1: srlv t3,t1,t2
269 2: xor t1,t3
270 and t3,t0,t1
271 beqz t3,3f
272 nop
273 move t0,t3
274 addu a0,t2
275 3: srl t2,1
276 bnez t2,2b
277 srlv t3,t1,t2
278
279 handle_it:
280 j dec_irq_dispatch
281 nop
282
283 #if defined(CONFIG_32BIT) && defined(CONFIG_MI
284 fpu:
285 lw t0,fpu_kstat_irq
286 nop
287 lw t1,(t0)
288 nop
289 addu t1,1
290 j handle_fpe_int
291 sw t1,(t0)
292 #endif
293
294 spurious:
295 j spurious_interrupt
296 nop
297 END(plat_irq_dispatch)
298
299 /*
300 * Generic unimplemented interrupt routines --
301 * and asic_mask_nr_tbl are initialized to poi
302 * The tables are then filled in by machine-sp
303 * in dec_setup().
304 */
305 FEXPORT(dec_intr_unimplemented
306 move a1,t0
307 ASM_PANIC("Unimplemented cpu i
308
309 FEXPORT(asic_intr_unimplemente
310 move a1,t0
311 ASM_PANIC("Unimplemented asic
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