1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Microsemi MIPS SoC support 3 * Microsemi MIPS SoC support
4 * 4 *
5 * Copyright (c) 2017 Microsemi Corporation 5 * Copyright (c) 2017 Microsemi Corporation
6 */ 6 */
7 #include <asm/machine.h> 7 #include <asm/machine.h>
8 #include <asm/prom.h> 8 #include <asm/prom.h>
9 9
10 #define DEVCPU_GCB_CHIP_REGS_CHIP_ID 0x7107 10 #define DEVCPU_GCB_CHIP_REGS_CHIP_ID 0x71070000
11 #define CHIP_ID_PART_ID GENMAS 11 #define CHIP_ID_PART_ID GENMASK(27, 12)
12 12
13 #define OCELOT_PART_ID (0x751 13 #define OCELOT_PART_ID (0x7514 << 12)
14 14
15 #define UART_UART 0x7010 15 #define UART_UART 0x70100000
16 16
17 static __init bool ocelot_detect(void) 17 static __init bool ocelot_detect(void)
18 { 18 {
19 u32 rev; 19 u32 rev;
20 int idx; 20 int idx;
21 21
22 /* Look for the TLB entry set up by re 22 /* Look for the TLB entry set up by redboot before trying to use it */
23 write_c0_entryhi(DEVCPU_GCB_CHIP_REGS_ 23 write_c0_entryhi(DEVCPU_GCB_CHIP_REGS_CHIP_ID);
24 mtc0_tlbw_hazard(); 24 mtc0_tlbw_hazard();
25 tlb_probe(); 25 tlb_probe();
26 tlb_probe_hazard(); 26 tlb_probe_hazard();
27 idx = read_c0_index(); 27 idx = read_c0_index();
28 if (idx < 0) 28 if (idx < 0)
29 return false; 29 return false;
30 30
31 /* A TLB entry exists, lets assume its 31 /* A TLB entry exists, lets assume its usable and check the CHIP ID */
32 rev = __raw_readl((void __iomem *)DEVC 32 rev = __raw_readl((void __iomem *)DEVCPU_GCB_CHIP_REGS_CHIP_ID);
33 33
34 if ((rev & CHIP_ID_PART_ID) != OCELOT_ 34 if ((rev & CHIP_ID_PART_ID) != OCELOT_PART_ID)
35 return false; 35 return false;
36 36
37 /* Copy command line from bootloader e 37 /* Copy command line from bootloader early for Initrd detection */
38 if (fw_arg0 < 10 && (fw_arg1 & 0xFFF00 38 if (fw_arg0 < 10 && (fw_arg1 & 0xFFF00000) == 0x80000000) {
39 unsigned int prom_argc = fw_ar 39 unsigned int prom_argc = fw_arg0;
40 const char **prom_argv = (cons 40 const char **prom_argv = (const char **)fw_arg1;
41 41
42 if (prom_argc > 1 && strlen(pr 42 if (prom_argc > 1 && strlen(prom_argv[1]) > 0)
43 /* ignore all built-in 43 /* ignore all built-in args if any f/w args given */
44 strcpy(arcs_cmdline, p 44 strcpy(arcs_cmdline, prom_argv[1]);
45 } 45 }
46 46
47 return true; 47 return true;
48 } 48 }
49 49
50 static void __init ocelot_earlyprintk_init(voi 50 static void __init ocelot_earlyprintk_init(void)
51 { 51 {
52 void __iomem *uart_base; 52 void __iomem *uart_base;
53 53
54 uart_base = ioremap(UART_UART, 0x20); 54 uart_base = ioremap(UART_UART, 0x20);
55 setup_8250_early_printk_port((unsigned 55 setup_8250_early_printk_port((unsigned long)uart_base, 2, 50000);
56 } 56 }
57 57
58 static void __init ocelot_late_init(void) 58 static void __init ocelot_late_init(void)
59 { 59 {
60 ocelot_earlyprintk_init(); 60 ocelot_earlyprintk_init();
61 } 61 }
62 62
63 static __init const void *ocelot_fixup_fdt(con 63 static __init const void *ocelot_fixup_fdt(const void *fdt,
64 con 64 const void *match_data)
65 { 65 {
66 /* This has to be done so late because 66 /* This has to be done so late because ioremap needs to work */
67 late_time_init = ocelot_late_init; 67 late_time_init = ocelot_late_init;
68 68
69 return fdt; 69 return fdt;
70 } 70 }
71 71
72 extern char __dtb_ocelot_pcb123_begin[]; 72 extern char __dtb_ocelot_pcb123_begin[];
73 73
74 MIPS_MACHINE(ocelot) = { 74 MIPS_MACHINE(ocelot) = {
75 .fdt = __dtb_ocelot_pcb123_begin, 75 .fdt = __dtb_ocelot_pcb123_begin,
76 .fixup_fdt = ocelot_fixup_fdt, 76 .fixup_fdt = ocelot_fixup_fdt,
77 .detect = ocelot_detect, 77 .detect = ocelot_detect,
78 }; 78 };
79 79
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