1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1
2 /*
3 * Copyright (C) 2014 Imagination Technologies
4 * Author: Paul Burton <paul.burton@mips.com>
5 */
6
7 #ifndef __MIPS_ASM_MIPS_MAAR_H__
8 #define __MIPS_ASM_MIPS_MAAR_H__
9
10 #include <asm/hazards.h>
11 #include <asm/mipsregs.h>
12
13 /**
14 * platform_maar_init() - perform platform-lev
15 * @num_pairs: The number of MAAR pairs prese
16 *
17 * Platforms should implement this function su
18 * MAAR pairs as required, from 0 up to the ma
19 * the number that were used. Any further MAAR
20 * invalid. The default implementation of this
21 * that it has configured 0 MAAR pairs.
22 *
23 * Return: The number of MAAR pairs confi
24 */
25 unsigned platform_maar_init(unsigned num_pairs
26
27 /**
28 * write_maar_pair() - write to a pair of MAAR
29 * @idx: The index of the pair (ie. use
30 * @lower: The lowest address that the MA
31 * aligned to a 2^16 byte boundar
32 * @upper: The highest address that the M
33 * aligned to one byte before a 2
34 * @attrs: The accessibility attributes t
35 * MIPS_MAAR_VL/MIPS_MAAR_VH attr
36 *
37 * Program the pair of MAAR registers specifie
38 * specified by attrs to the range of addresse
39 */
40 static inline void write_maar_pair(unsigned id
41 phys_addr_t
42 {
43 /* Addresses begin at bit 16, but are
44 BUG_ON(lower & (0xffff | ~(MIPS_MAAR_A
45 BUG_ON(((upper & 0xffff) != 0xffff)
46 || ((upper & ~0xffffull) & ~(M
47
48 /* Automatically set MIPS_MAAR_VL */
49 attrs |= MIPS_MAAR_VL;
50
51 /*
52 * Write the upper address & attribute
53 * MIPS_MAAR_VH matter)
54 */
55 write_c0_maari(idx << 1);
56 back_to_back_c0_hazard();
57 write_c0_maar(((upper >> 4) & MIPS_MAA
58 back_to_back_c0_hazard();
59 #ifdef CONFIG_XPA
60 upper >>= MIPS_MAARX_ADDR_SHIFT;
61 writex_c0_maar(((upper >> 4) & MIPS_MA
62 back_to_back_c0_hazard();
63 #endif
64
65 /* Write the lower address & attribute
66 write_c0_maari((idx << 1) | 0x1);
67 back_to_back_c0_hazard();
68 write_c0_maar((lower >> 4) | attrs);
69 back_to_back_c0_hazard();
70 #ifdef CONFIG_XPA
71 lower >>= MIPS_MAARX_ADDR_SHIFT;
72 writex_c0_maar(((lower >> 4) & MIPS_MA
73 back_to_back_c0_hazard();
74 #endif
75 }
76
77 /**
78 * maar_init() - initialise MAARs
79 *
80 * Performs initialisation of MAARs for the cu
81 * platforms implementation of platform_maar_i
82 * duplicating the setup it provides on second
83 */
84 extern void maar_init(void);
85
86 /**
87 * struct maar_config - MAAR configuration dat
88 * @lower: The lowest address that the MA
89 * aligned to a 2^16 byte boundar
90 * @upper: The highest address that the M
91 * aligned to one byte before a 2
92 * @attrs: The accessibility attributes t
93 * MIPS_MAAR_VL attribute will au
94 *
95 * Describes the configuration of a pair of Me
96 * Registers - applying attributes from attrs
97 * addresses from lower to upper inclusive.
98 */
99 struct maar_config {
100 phys_addr_t lower;
101 phys_addr_t upper;
102 unsigned attrs;
103 };
104
105 /**
106 * maar_config() - configure MAARs according t
107 * @cfg: Pointer to an array of struct
108 * @num_cfg: The number of structs in the c
109 * @num_pairs: The number of MAAR pairs prese
110 *
111 * Configures as many MAARs as are present and
112 * array with the values taken from the cfg ar
113 *
114 * Return: The number of MAAR pairs confi
115 */
116 static inline unsigned maar_config(const struc
117 unsigned nu
118 {
119 unsigned i;
120
121 for (i = 0; i < min(num_cfg, num_pairs
122 write_maar_pair(i, cfg[i].lowe
123
124 return i;
125 }
126
127 #endif /* __MIPS_ASM_MIPS_MAAR_H__ */
128
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