1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 2 /* ****************************************** 3 * SB1250 Board Support Package 4 * 5 * Register Definitions 6 * 7 * This module contains the addresses of t 8 * on the SB1250. 9 * 10 * SB1250 specification level: 01/02/2002 11 * 12 ****************************************** 13 * 14 * Copyright 2000,2001,2002,2003 15 * Broadcom Corporation. All rights reserv 16 * 17 ****************************************** 18 19 20 #ifndef _SB1250_REGS_H 21 #define _SB1250_REGS_H 22 23 #include <asm/sibyte/sb1250_defs.h> 24 25 26 /* ****************************************** 27 * Some general notes: 28 * 29 * For the most part, when there is more t 30 * of the same type on the SOC, the consta 31 * offsets from the base of each periphera 32 * the MAC registers are described as offs 33 * MAC register, and there will be a MAC_R 34 * to calculate the base address of a give 35 * 36 * The information in this file is based o 37 * manual version 0.2, July 2000. 38 ****************************************** 39 40 41 /* ****************************************** 42 * Memory Controller Registers 43 ****************************************** 44 45 /* 46 * XXX: can't remove MC base 0 if 112x, since 47 * since there is one reg there (but it could 48 */ 49 50 #if SIBYTE_HDR_FEATURE_1250_112x 51 #define A_MC_BASE_0 0x00100510 52 #define A_MC_BASE_1 0x00100520 53 #define MC_REGISTER_SPACING 0x1000 54 55 #define A_MC_BASE(ctlid) ((ctlid)*M 56 #define A_MC_REGISTER(ctlid, reg) (A_MC_BAS 57 58 #define R_MC_CONFIG 0x00000001 59 #define R_MC_DRAMCMD 0x00000001 60 #define R_MC_DRAMMODE 0x00000001 61 #define R_MC_TIMING1 0x00000001 62 #define R_MC_TIMING2 0x00000001 63 #define R_MC_CS_START 0x00000001 64 #define R_MC_CS_END 0x00000001 65 #define R_MC_CS_INTERLEAVE 0x00000001 66 #define S_MC_CS_STARTEND 16 67 68 #define R_MC_CSX_BASE 0x00000002 69 #define R_MC_CSX_ROW 0x00000000 70 #define R_MC_CSX_COL 0x00000000 71 #define R_MC_CSX_BA 0x00000000 72 #define MC_CSX_SPACING 0x00000000 73 74 #define R_MC_CS0_ROW 0x00000002 75 #define R_MC_CS0_COL 0x00000002 76 #define R_MC_CS0_BA 0x00000002 77 #define R_MC_CS1_ROW 0x00000002 78 #define R_MC_CS1_COL 0x00000002 79 #define R_MC_CS1_BA 0x00000002 80 #define R_MC_CS2_ROW 0x00000002 81 #define R_MC_CS2_COL 0x00000002 82 #define R_MC_CS2_BA 0x00000003 83 #define R_MC_CS3_ROW 0x00000003 84 #define R_MC_CS3_COL 0x00000003 85 #define R_MC_CS3_BA 0x00000003 86 #define R_MC_CS_ATTR 0x00000003 87 #define R_MC_TEST_DATA 0x00000004 88 #define R_MC_TEST_ECC 0x00000004 89 #define R_MC_MCLK_CFG 0x00000005 90 91 #endif /* 1250 & 112x */ 92 93 /* ****************************************** 94 * L2 Cache Control Registers 95 ****************************************** 96 97 #if SIBYTE_HDR_FEATURE_1250_112x /* Thi 98 99 #define A_L2_READ_TAG 0x00100400 100 #define A_L2_ECC_TAG 0x00100400 101 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_ 102 #define A_L2_READ_MISC 0x00100400 103 #endif /* 1250 PASS3 || 112x PASS1 */ 104 #define A_L2_WAY_DISABLE 0x00100410 105 #define A_L2_MAKEDISABLE(x) (A_L2_WAY_ 106 #define A_L2_MGMT_TAG_BASE 0x00D00000 107 108 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_ 109 #define A_L2_CACHE_DISABLE 0x001004200 110 #define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE 111 #define A_L2_MISC_CONFIG 0x001004300 112 #endif /* 1250 PASS2 || 112x PASS1 */ 113 114 /* Backward-compatibility definitions. */ 115 /* XXX: discourage people from using these con 116 #define A_L2_READ_ADDRESS A_L2_READ_ 117 #define A_L2_EEC_ADDRESS A_L2_ECC_T 118 119 #endif 120 121 122 /* ****************************************** 123 * PCI Interface Registers 124 ****************************************** 125 126 #if SIBYTE_HDR_FEATURE_1250_112x /* Thi 127 #define A_PCI_TYPE00_HEADER 0x00DE0000 128 #define A_PCI_TYPE01_HEADER 0x00DE0008 129 #endif 130 131 132 /* ****************************************** 133 * Ethernet DMA and MACs 134 ****************************************** 135 136 #define A_MAC_BASE_0 0x00100640 137 #define A_MAC_BASE_1 0x00100650 138 #if SIBYTE_HDR_FEATURE_CHIP(1250) 139 #define A_MAC_BASE_2 0x00100660 140 #endif /* 1250 */ 141 142 #define MAC_SPACING 0x1000 143 #define MAC_DMA_TXRX_SPACING 0x0400 144 #define MAC_DMA_CHANNEL_SPACING 0x0100 145 #define DMA_RX 0 146 #define DMA_TX 1 147 #define MAC_NUM_DMACHAN 2 148 149 /* XXX: not correct; depends on SOC type. */ 150 #define MAC_NUM_PORTS 3 151 152 #define A_MAC_CHANNEL_BASE(macnum) 153 (A_MAC_BASE_0 + 154 MAC_SPACING*(macnum)) 155 156 #define A_MAC_REGISTER(macnum,reg) 157 (A_MAC_BASE_0 + 158 MAC_SPACING*(macnum) + (reg)) 159 160 161 #define R_MAC_DMA_CHANNELS 0x800 162 163 #define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, c 164 ((A_MAC_CHANNEL_BASE(macnum)) + 165 R_MAC_DMA_CHANNELS + 166 (MAC_DMA_TXRX_SPACING*(txrx)) + 167 (MAC_DMA_CHANNEL_SPACING*(chan))) 168 169 #define R_MAC_DMA_CHANNEL_BASE(txrx, chan) 170 (R_MAC_DMA_CHANNELS + 171 (MAC_DMA_TXRX_SPACING*(txrx)) + 172 (MAC_DMA_CHANNEL_SPACING*(chan))) 173 174 #define A_MAC_DMA_REGISTER(macnum, txrx, chan, 175 (A_MAC_DMA_CHANNEL_BASE(macnum, tx 176 (reg)) 177 178 #define R_MAC_DMA_REGISTER(txrx, chan, reg) 179 (R_MAC_DMA_CHANNEL_BASE(txrx, chan 180 (reg)) 181 182 /* 183 * DMA channel registers, relative to A_MAC_DM 184 */ 185 186 #define R_MAC_DMA_CONFIG0 0x0000 187 #define R_MAC_DMA_CONFIG1 0x0000 188 #define R_MAC_DMA_DSCR_BASE 0x0000 189 #define R_MAC_DMA_DSCR_CNT 0x0000 190 #define R_MAC_DMA_CUR_DSCRA 0x0000 191 #define R_MAC_DMA_CUR_DSCRB 0x0000 192 #define R_MAC_DMA_CUR_DSCRADDR 0x0000 193 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_ 194 #define R_MAC_DMA_OODPKTLOST_RX 0x0000 195 #endif /* 1250 PASS3 || 112x PASS1 */ 196 197 /* 198 * RMON Counters 199 */ 200 201 #define R_MAC_RMON_TX_BYTES 0x0000 202 #define R_MAC_RMON_COLLISIONS 0x0000 203 #define R_MAC_RMON_LATE_COL 0x0000 204 #define R_MAC_RMON_EX_COL 0x0000 205 #define R_MAC_RMON_FCS_ERROR 0x0000 206 #define R_MAC_RMON_TX_ABORT 0x0000 207 /* Counter #6 (0x30) now reserved */ 208 #define R_MAC_RMON_TX_BAD 0x0000 209 #define R_MAC_RMON_TX_GOOD 0x0000 210 #define R_MAC_RMON_TX_RUNT 0x0000 211 #define R_MAC_RMON_TX_OVERSIZE 0x0000 212 #define R_MAC_RMON_RX_BYTES 0x0000 213 #define R_MAC_RMON_RX_MCAST 0x0000 214 #define R_MAC_RMON_RX_BCAST 0x0000 215 #define R_MAC_RMON_RX_BAD 0x0000 216 #define R_MAC_RMON_RX_GOOD 0x0000 217 #define R_MAC_RMON_RX_RUNT 0x0000 218 #define R_MAC_RMON_RX_OVERSIZE 0x0000 219 #define R_MAC_RMON_RX_FCS_ERROR 0x0000 220 #define R_MAC_RMON_RX_LENGTH_ERROR 0x0000 221 #define R_MAC_RMON_RX_CODE_ERROR 0x0000 222 #define R_MAC_RMON_RX_ALIGN_ERROR 0x0000 223 224 /* Updated to spec 0.2 */ 225 #define R_MAC_CFG 0x0000 226 #define R_MAC_THRSH_CFG 0x0000 227 #define R_MAC_VLANTAG 0x0000 228 #define R_MAC_FRAMECFG 0x0000 229 #define R_MAC_EOPCNT 0x0000 230 #define R_MAC_FIFO_PTRS 0x0000 231 #define R_MAC_ADFILTER_CFG 0x0000 232 #define R_MAC_ETHERNET_ADDR 0x0000 233 #define R_MAC_PKT_TYPE 0x0000 234 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_ 235 #define R_MAC_ADMASK0 0x0000 236 #define R_MAC_ADMASK1 0x0000 237 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 238 #define R_MAC_HASH_BASE 0x0000 239 #define R_MAC_ADDR_BASE 0x0000 240 #define R_MAC_CHLO0_BASE 0x0000 241 #define R_MAC_CHUP0_BASE 0x0000 242 #define R_MAC_ENABLE 0x0000 243 #define R_MAC_STATUS 0x0000 244 #define R_MAC_INT_MASK 0x0000 245 #define R_MAC_TXD_CTL 0x0000 246 #define R_MAC_MDIO 0x0000 247 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_ 248 #define R_MAC_STATUS1 0x0000 249 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 250 #define R_MAC_DEBUG_STATUS 0x0000 251 252 #define MAC_HASH_COUNT 8 253 #define MAC_ADDR_COUNT 8 254 #define MAC_CHMAP_COUNT 4 255 256 257 /* ****************************************** 258 * DUART Registers 259 ****************************************** 260 261 262 #if SIBYTE_HDR_FEATURE_1250_112x /* This MC 263 #define R_DUART_NUM_PORTS 2 264 265 #define A_DUART 0x00100600 266 267 #define DUART_CHANREG_SPACING 0x100 268 269 #define A_DUART_CHANREG(chan, reg) 270 (A_DUART + DUART_CHANREG_SPACING * ((c 271 #endif /* 1250 & 112x */ 272 273 #define R_DUART_MODE_REG_1 0x000 274 #define R_DUART_MODE_REG_2 0x010 275 #define R_DUART_STATUS 0x020 276 #define R_DUART_CLK_SEL 0x030 277 #define R_DUART_CMD 0x050 278 #define R_DUART_RX_HOLD 0x060 279 #define R_DUART_TX_HOLD 0x070 280 281 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_ 282 #define R_DUART_FULL_CTL 0x040 283 #define R_DUART_OPCR_X 0x080 284 #define R_DUART_AUXCTL_X 0x090 285 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 286 287 288 /* 289 * The IMR and ISR can't be addressed with A_D 290 * so use these macros instead. 291 */ 292 293 #if SIBYTE_HDR_FEATURE_1250_112x /* This MC 294 #define DUART_IMRISR_SPACING 0x20 295 #define DUART_INCHNG_SPACING 0x10 296 297 #define A_DUART_CTRLREG(reg) 298 (A_DUART + DUART_CHANREG_SPACING * 3 + 299 300 #define R_DUART_IMRREG(chan) 301 (R_DUART_IMR_A + (chan) * DUART_IMRISR 302 #define R_DUART_ISRREG(chan) 303 (R_DUART_ISR_A + (chan) * DUART_IMRISR 304 #define R_DUART_INCHREG(chan) 305 (R_DUART_IN_CHNG_A + (chan) * DUART_IN 306 307 #define A_DUART_IMRREG(chan) A_DUART_CT 308 #define A_DUART_ISRREG(chan) A_DUART_CT 309 #define A_DUART_INCHREG(chan) A_DUART_CT 310 #endif /* 1250 & 112x */ 311 312 #define R_DUART_AUX_CTRL 0x010 313 #define R_DUART_ISR_A 0x020 314 #define R_DUART_IMR_A 0x030 315 #define R_DUART_ISR_B 0x040 316 #define R_DUART_IMR_B 0x050 317 #define R_DUART_OUT_PORT 0x060 318 #define R_DUART_OPCR 0x070 319 #define R_DUART_IN_PORT 0x080 320 321 #define R_DUART_SET_OPR 0x0B0 322 #define R_DUART_CLEAR_OPR 0x0C0 323 #define R_DUART_IN_CHNG_A 0x0D0 324 #define R_DUART_IN_CHNG_B 0x0E0 325 326 327 /* 328 * These constants are the absolute addresses. 329 */ 330 331 #define A_DUART_MODE_REG_1_A 0x00100601 332 #define A_DUART_MODE_REG_2_A 0x00100601 333 #define A_DUART_STATUS_A 0x00100601 334 #define A_DUART_CLK_SEL_A 0x00100601 335 #define A_DUART_CMD_A 0x00100601 336 #define A_DUART_RX_HOLD_A 0x00100601 337 #define A_DUART_TX_HOLD_A 0x00100601 338 339 #define A_DUART_MODE_REG_1_B 0x00100602 340 #define A_DUART_MODE_REG_2_B 0x00100602 341 #define A_DUART_STATUS_B 0x00100602 342 #define A_DUART_CLK_SEL_B 0x00100602 343 #define A_DUART_CMD_B 0x00100602 344 #define A_DUART_RX_HOLD_B 0x00100602 345 #define A_DUART_TX_HOLD_B 0x00100602 346 347 #define A_DUART_INPORT_CHNG 0x00100603 348 #define A_DUART_AUX_CTRL 0x00100603 349 #define A_DUART_ISR_A 0x00100603 350 #define A_DUART_IMR_A 0x00100603 351 #define A_DUART_ISR_B 0x00100603 352 #define A_DUART_IMR_B 0x00100603 353 #define A_DUART_OUT_PORT 0x00100603 354 #define A_DUART_OPCR 0x00100603 355 #define A_DUART_IN_PORT 0x00100603 356 #define A_DUART_ISR 0x00100603 357 #define A_DUART_IMR 0x00100603 358 #define A_DUART_SET_OPR 0x00100603 359 #define A_DUART_CLEAR_OPR 0x00100603 360 #define A_DUART_INPORT_CHNG_A 0x00100603 361 #define A_DUART_INPORT_CHNG_B 0x00100603 362 363 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_ 364 #define A_DUART_FULL_CTL_A 0x00100601 365 #define A_DUART_FULL_CTL_B 0x00100602 366 367 #define A_DUART_OPCR_A 0x00100601 368 #define A_DUART_OPCR_B 0x00100602 369 370 #define A_DUART_INPORT_CHNG_DEBUG 0x00100603 371 #endif /* 1250 PASS2 || 112x PASS1 */ 372 373 374 /* ****************************************** 375 * Synchronous Serial Registers 376 ****************************************** 377 378 379 #if SIBYTE_HDR_FEATURE_1250_112x /* syn 380 381 #define A_SER_BASE_0 0x00100604 382 #define A_SER_BASE_1 0x00100608 383 #define SER_SPACING 0x400 384 385 #define SER_DMA_TXRX_SPACING 0x80 386 387 #define SER_NUM_PORTS 2 388 389 #define A_SER_CHANNEL_BASE(sernum) 390 (A_SER_BASE_0 + 391 SER_SPACING*(sernum)) 392 393 #define A_SER_REGISTER(sernum,reg) 394 (A_SER_BASE_0 + 395 SER_SPACING*(sernum) + (reg)) 396 397 398 #define R_SER_DMA_CHANNELS 0 /* 399 400 #define A_SER_DMA_CHANNEL_BASE(sernum,txrx) 401 ((A_SER_CHANNEL_BASE(sernum)) + 402 R_SER_DMA_CHANNELS + 403 (SER_DMA_TXRX_SPACING*(txrx))) 404 405 #define A_SER_DMA_REGISTER(sernum, txrx, reg) 406 (A_SER_DMA_CHANNEL_BASE(sernum, tx 407 (reg)) 408 409 410 /* 411 * DMA channel registers, relative to A_SER_DM 412 */ 413 414 #define R_SER_DMA_CONFIG0 0x00000000 415 #define R_SER_DMA_CONFIG1 0x00000008 416 #define R_SER_DMA_DSCR_BASE 0x00000010 417 #define R_SER_DMA_DSCR_CNT 0x00000018 418 #define R_SER_DMA_CUR_DSCRA 0x00000020 419 #define R_SER_DMA_CUR_DSCRB 0x00000028 420 #define R_SER_DMA_CUR_DSCRADDR 0x00000030 421 422 #define R_SER_DMA_CONFIG0_RX 0x00000000 423 #define R_SER_DMA_CONFIG1_RX 0x00000008 424 #define R_SER_DMA_DSCR_BASE_RX 0x00000010 425 #define R_SER_DMA_DSCR_COUNT_RX 0x00000018 426 #define R_SER_DMA_CUR_DSCR_A_RX 0x00000020 427 #define R_SER_DMA_CUR_DSCR_B_RX 0x00000028 428 #define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030 429 430 #define R_SER_DMA_CONFIG0_TX 0x00000080 431 #define R_SER_DMA_CONFIG1_TX 0x00000088 432 #define R_SER_DMA_DSCR_BASE_TX 0x00000090 433 #define R_SER_DMA_DSCR_COUNT_TX 0x00000098 434 #define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0 435 #define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8 436 #define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0 437 438 #define R_SER_MODE 0x00000100 439 #define R_SER_MINFRM_SZ 0x00000108 440 #define R_SER_MAXFRM_SZ 0x00000110 441 #define R_SER_ADDR 0x00000118 442 #define R_SER_USR0_ADDR 0x00000120 443 #define R_SER_USR1_ADDR 0x00000128 444 #define R_SER_USR2_ADDR 0x00000130 445 #define R_SER_USR3_ADDR 0x00000138 446 #define R_SER_CMD 0x00000140 447 #define R_SER_TX_RD_THRSH 0x00000160 448 #define R_SER_TX_WR_THRSH 0x00000168 449 #define R_SER_RX_RD_THRSH 0x00000170 450 #define R_SER_LINE_MODE 0x00000178 451 #define R_SER_DMA_ENABLE 0x00000180 452 #define R_SER_INT_MASK 0x00000190 453 #define R_SER_STATUS 0x00000188 454 #define R_SER_STATUS_DEBUG 0x000001A8 455 #define R_SER_RX_TABLE_BASE 0x00000200 456 #define SER_RX_TABLE_COUNT 16 457 #define R_SER_TX_TABLE_BASE 0x00000300 458 #define SER_TX_TABLE_COUNT 16 459 460 /* RMON Counters */ 461 #define R_SER_RMON_TX_BYTE_LO 0x000001C0 462 #define R_SER_RMON_TX_BYTE_HI 0x000001C8 463 #define R_SER_RMON_RX_BYTE_LO 0x000001D0 464 #define R_SER_RMON_RX_BYTE_HI 0x000001D8 465 #define R_SER_RMON_TX_UNDERRUN 0x000001E0 466 #define R_SER_RMON_RX_OVERFLOW 0x000001E8 467 #define R_SER_RMON_RX_ERRORS 0x000001F0 468 #define R_SER_RMON_RX_BADADDR 0x000001F8 469 470 #endif /* 1250/112x */ 471 472 /* ****************************************** 473 * Generic Bus Registers 474 ****************************************** 475 476 #define IO_EXT_CFG_COUNT 8 477 478 #define A_IO_EXT_BASE 0x00100610 479 #define A_IO_EXT_REG(r) (A_IO_EXT_ 480 481 #define A_IO_EXT_CFG_BASE 0x00100610 482 #define A_IO_EXT_MULT_SIZE_BASE 0x00100611 483 #define A_IO_EXT_START_ADDR_BASE 0x00100612 484 #define A_IO_EXT_TIME_CFG0_BASE 0x00100616 485 #define A_IO_EXT_TIME_CFG1_BASE 0x00100617 486 487 #define IO_EXT_REGISTER_SPACING 8 488 #define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_ 489 #define R_IO_EXT_REG(reg, cs) ((cs)*IO_E 490 491 #define R_IO_EXT_CFG 0x0000 492 #define R_IO_EXT_MULT_SIZE 0x0100 493 #define R_IO_EXT_START_ADDR 0x0200 494 #define R_IO_EXT_TIME_CFG0 0x0600 495 #define R_IO_EXT_TIME_CFG1 0x0700 496 497 498 #define A_IO_INTERRUPT_STATUS 0x0010061A 499 #define A_IO_INTERRUPT_DATA0 0x0010061A 500 #define A_IO_INTERRUPT_DATA1 0x0010061A 501 #define A_IO_INTERRUPT_DATA2 0x0010061A 502 #define A_IO_INTERRUPT_DATA3 0x0010061A 503 #define A_IO_INTERRUPT_ADDR0 0x0010061A 504 #define A_IO_INTERRUPT_ADDR1 0x0010061A 505 #define A_IO_INTERRUPT_PARITY 0x0010061A 506 #define A_IO_PCMCIA_CFG 0x0010061A 507 #define A_IO_PCMCIA_STATUS 0x0010061A 508 #define A_IO_DRIVE_0 0x00100613 509 #define A_IO_DRIVE_1 0x00100613 510 #define A_IO_DRIVE_2 0x00100613 511 #define A_IO_DRIVE_3 0x00100613 512 #define A_IO_DRIVE_BASE A_IO_DRIVE 513 #define IO_DRIVE_REGISTER_SPACING 8 514 #define R_IO_DRIVE(x) ((x)*IO_DR 515 #define A_IO_DRIVE(x) (A_IO_DRIV 516 517 #define R_IO_INTERRUPT_STATUS 0x0A00 518 #define R_IO_INTERRUPT_DATA0 0x0A10 519 #define R_IO_INTERRUPT_DATA1 0x0A18 520 #define R_IO_INTERRUPT_DATA2 0x0A20 521 #define R_IO_INTERRUPT_DATA3 0x0A28 522 #define R_IO_INTERRUPT_ADDR0 0x0A30 523 #define R_IO_INTERRUPT_ADDR1 0x0A40 524 #define R_IO_INTERRUPT_PARITY 0x0A50 525 #define R_IO_PCMCIA_CFG 0x0A60 526 #define R_IO_PCMCIA_STATUS 0x0A70 527 528 /* ****************************************** 529 * GPIO Registers 530 ****************************************** 531 532 #define A_GPIO_CLR_EDGE 0x0010061A 533 #define A_GPIO_INT_TYPE 0x0010061A 534 #define A_GPIO_INPUT_INVERT 0x0010061A 535 #define A_GPIO_GLITCH 0x0010061A 536 #define A_GPIO_READ 0x0010061A 537 #define A_GPIO_DIRECTION 0x0010061A 538 #define A_GPIO_PIN_CLR 0x0010061A 539 #define A_GPIO_PIN_SET 0x0010061A 540 541 #define A_GPIO_BASE 0x0010061A 542 543 #define R_GPIO_CLR_EDGE 0x00 544 #define R_GPIO_INT_TYPE 0x08 545 #define R_GPIO_INPUT_INVERT 0x10 546 #define R_GPIO_GLITCH 0x18 547 #define R_GPIO_READ 0x20 548 #define R_GPIO_DIRECTION 0x28 549 #define R_GPIO_PIN_CLR 0x30 550 #define R_GPIO_PIN_SET 0x38 551 552 /* ****************************************** 553 * SMBus Registers 554 ****************************************** 555 556 #define A_SMB_XTRA_0 0x00100600 557 #define A_SMB_XTRA_1 0x00100600 558 #define A_SMB_FREQ_0 0x00100600 559 #define A_SMB_FREQ_1 0x00100600 560 #define A_SMB_STATUS_0 0x00100600 561 #define A_SMB_STATUS_1 0x00100600 562 #define A_SMB_CMD_0 0x00100600 563 #define A_SMB_CMD_1 0x00100600 564 #define A_SMB_START_0 0x00100600 565 #define A_SMB_START_1 0x00100600 566 #define A_SMB_DATA_0 0x00100600 567 #define A_SMB_DATA_1 0x00100600 568 #define A_SMB_CONTROL_0 0x00100600 569 #define A_SMB_CONTROL_1 0x00100600 570 #define A_SMB_PEC_0 0x00100600 571 #define A_SMB_PEC_1 0x00100600 572 573 #define A_SMB_0 0x00100600 574 #define A_SMB_1 0x00100600 575 #define SMB_REGISTER_SPACING 0x8 576 #define A_SMB_BASE(idx) (A_SMB_0+( 577 #define A_SMB_REGISTER(idx, reg) (A_SMB_BAS 578 579 #define R_SMB_XTRA 0x00000000 580 #define R_SMB_FREQ 0x00000000 581 #define R_SMB_STATUS 0x00000000 582 #define R_SMB_CMD 0x00000000 583 #define R_SMB_START 0x00000000 584 #define R_SMB_DATA 0x00000000 585 #define R_SMB_CONTROL 0x00000000 586 #define R_SMB_PEC 0x00000000 587 588 /* ****************************************** 589 * Timer Registers 590 ****************************************** 591 592 /* 593 * Watchdog timers 594 */ 595 596 #define A_SCD_WDOG_0 0x00100200 597 #define A_SCD_WDOG_1 0x00100201 598 #define SCD_WDOG_SPACING 0x100 599 #define SCD_NUM_WDOGS 2 600 #define A_SCD_WDOG_BASE(w) (A_SCD_WDO 601 #define A_SCD_WDOG_REGISTER(w, r) (A_SCD_WDO 602 603 #define R_SCD_WDOG_INIT 0x00000000 604 #define R_SCD_WDOG_CNT 0x00000000 605 #define R_SCD_WDOG_CFG 0x00000000 606 607 #define A_SCD_WDOG_INIT_0 0x00100200 608 #define A_SCD_WDOG_CNT_0 0x00100200 609 #define A_SCD_WDOG_CFG_0 0x00100200 610 611 #define A_SCD_WDOG_INIT_1 0x00100201 612 #define A_SCD_WDOG_CNT_1 0x00100201 613 #define A_SCD_WDOG_CFG_1 0x00100201 614 615 /* 616 * Generic timers 617 */ 618 619 #define A_SCD_TIMER_0 0x00100200 620 #define A_SCD_TIMER_1 0x00100200 621 #define A_SCD_TIMER_2 0x00100201 622 #define A_SCD_TIMER_3 0x00100201 623 #define SCD_NUM_TIMERS 4 624 #define A_SCD_TIMER_BASE(w) (A_SCD_TIM 625 #define A_SCD_TIMER_REGISTER(w, r) (A_SCD_TIM 626 627 #define R_SCD_TIMER_INIT 0x00000000 628 #define R_SCD_TIMER_CNT 0x00000000 629 #define R_SCD_TIMER_CFG 0x00000000 630 631 #define A_SCD_TIMER_INIT_0 0x00100200 632 #define A_SCD_TIMER_CNT_0 0x00100200 633 #define A_SCD_TIMER_CFG_0 0x00100200 634 635 #define A_SCD_TIMER_INIT_1 0x00100200 636 #define A_SCD_TIMER_CNT_1 0x00100200 637 #define A_SCD_TIMER_CFG_1 0x00100200 638 639 #define A_SCD_TIMER_INIT_2 0x00100201 640 #define A_SCD_TIMER_CNT_2 0x00100201 641 #define A_SCD_TIMER_CFG_2 0x00100201 642 643 #define A_SCD_TIMER_INIT_3 0x00100201 644 #define A_SCD_TIMER_CNT_3 0x00100201 645 #define A_SCD_TIMER_CFG_3 0x00100201 646 647 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_ 648 #define A_SCD_SCRATCH 0x0010020C1 649 #endif /* 1250 PASS2 || 112x PASS1 */ 650 651 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_ 652 #define A_SCD_ZBBUS_CYCLE_COUNT 0x001003000 653 #define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C0 654 #define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C0 655 #endif 656 657 /* ****************************************** 658 * System Control Registers 659 ****************************************** 660 661 #define A_SCD_SYSTEM_REVISION 0x00100200 662 #define A_SCD_SYSTEM_CFG 0x00100200 663 #define A_SCD_SYSTEM_MANUF 0x00100380 664 665 /* ****************************************** 666 * System Address Trap Registers 667 ****************************************** 668 669 #define A_ADDR_TRAP_INDEX 0x00100200 670 #define A_ADDR_TRAP_REG 0x00100200 671 #define A_ADDR_TRAP_UP_0 0x00100204 672 #define A_ADDR_TRAP_UP_1 0x00100204 673 #define A_ADDR_TRAP_UP_2 0x00100204 674 #define A_ADDR_TRAP_UP_3 0x00100204 675 #define A_ADDR_TRAP_DOWN_0 0x00100204 676 #define A_ADDR_TRAP_DOWN_1 0x00100204 677 #define A_ADDR_TRAP_DOWN_2 0x00100204 678 #define A_ADDR_TRAP_DOWN_3 0x00100204 679 #define A_ADDR_TRAP_CFG_0 0x00100204 680 #define A_ADDR_TRAP_CFG_1 0x00100204 681 #define A_ADDR_TRAP_CFG_2 0x00100204 682 #define A_ADDR_TRAP_CFG_3 0x00100204 683 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_ 684 #define A_ADDR_TRAP_REG_DEBUG 0x00100204 685 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 686 687 #define ADDR_TRAP_SPACING 8 688 #define NUM_ADDR_TRAP 4 689 #define A_ADDR_TRAP_UP(n) (A_ADDR_TRAP_UP_0 + 690 #define A_ADDR_TRAP_DOWN(n) (A_ADDR_TRAP_DOWN_ 691 #define A_ADDR_TRAP_CFG(n) (A_ADDR_TRAP_CFG_0 692 693 694 /* ****************************************** 695 * System Interrupt Mapper Registers 696 ****************************************** 697 698 #define A_IMR_CPU0_BASE 0x0010 699 #define A_IMR_CPU1_BASE 0x0010 700 #define IMR_REGISTER_SPACING 0x2000 701 #define IMR_REGISTER_SPACING_SHIFT 13 702 703 #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cp 704 #define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER 705 706 #define R_IMR_INTERRUPT_DIAG 0x0010 707 #define R_IMR_INTERRUPT_LDT 0x0018 708 #define R_IMR_INTERRUPT_MASK 0x0028 709 #define R_IMR_INTERRUPT_TRACE 0x0038 710 #define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 711 #define R_IMR_LDT_INTERRUPT_SET 0x0048 712 #define R_IMR_LDT_INTERRUPT 0x0018 713 #define R_IMR_LDT_INTERRUPT_CLR 0x0020 714 #define R_IMR_MAILBOX_CPU 0x00c0 715 #define R_IMR_ALIAS_MAILBOX_CPU 0x1000 716 #define R_IMR_MAILBOX_SET_CPU 0x00C8 717 #define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008 718 #define R_IMR_MAILBOX_CLR_CPU 0x00D0 719 #define R_IMR_INTERRUPT_STATUS_BASE 0x0100 720 #define R_IMR_INTERRUPT_STATUS_COUNT 7 721 #define R_IMR_INTERRUPT_MAP_BASE 0x0200 722 #define R_IMR_INTERRUPT_MAP_COUNT 64 723 724 /* 725 * these macros work together to build the add 726 * register, e.g., A_MAILBOX_REGISTER(R_IMR_MA 727 * for mbox_0_set_cpu2 returns 0x00100240C8 728 */ 729 #define A_MAILBOX_REGISTER(reg,cpu) \ 730 (A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPA 731 732 /* ****************************************** 733 * System Performance Counter Registers 734 ****************************************** 735 736 #define A_SCD_PERF_CNT_CFG 0x00100204 737 #define A_SCD_PERF_CNT_0 0x00100204 738 #define A_SCD_PERF_CNT_1 0x00100204 739 #define A_SCD_PERF_CNT_2 0x00100204 740 #define A_SCD_PERF_CNT_3 0x00100204 741 742 #define SCD_NUM_PERF_CNT 4 743 #define SCD_PERF_CNT_SPACING 8 744 #define A_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n 745 746 /* ****************************************** 747 * System Bus Watcher Registers 748 ****************************************** 749 750 #define A_SCD_BUS_ERR_STATUS 0x00100208 751 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_ 752 #define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208 753 #define A_BUS_ERR_STATUS_DEBUG 0x00100208D0 754 #endif /* 1250 PASS2 || 112x PASS1 */ 755 #define A_BUS_ERR_DATA_0 0x00100208 756 #define A_BUS_ERR_DATA_1 0x00100208 757 #define A_BUS_ERR_DATA_2 0x00100208 758 #define A_BUS_ERR_DATA_3 0x00100208 759 #define A_BUS_L2_ERRORS 0x00100208 760 #define A_BUS_MEM_IO_ERRORS 0x00100208 761 762 /* ****************************************** 763 * System Debug Controller Registers 764 ****************************************** 765 766 #define A_SCD_JTAG_BASE 0x00100000 767 768 /* ****************************************** 769 * System Trace Buffer Registers 770 ****************************************** 771 772 #define A_SCD_TRACE_CFG 0x0010020A 773 #define A_SCD_TRACE_READ 0x0010020A 774 #define A_SCD_TRACE_EVENT_0 0x0010020A 775 #define A_SCD_TRACE_EVENT_1 0x0010020A 776 #define A_SCD_TRACE_EVENT_2 0x0010020A 777 #define A_SCD_TRACE_EVENT_3 0x0010020A 778 #define A_SCD_TRACE_SEQUENCE_0 0x0010020A 779 #define A_SCD_TRACE_SEQUENCE_1 0x0010020A 780 #define A_SCD_TRACE_SEQUENCE_2 0x0010020A 781 #define A_SCD_TRACE_SEQUENCE_3 0x0010020A 782 #define A_SCD_TRACE_EVENT_4 0x0010020A 783 #define A_SCD_TRACE_EVENT_5 0x0010020A 784 #define A_SCD_TRACE_EVENT_6 0x0010020A 785 #define A_SCD_TRACE_EVENT_7 0x0010020A 786 #define A_SCD_TRACE_SEQUENCE_4 0x0010020A 787 #define A_SCD_TRACE_SEQUENCE_5 0x0010020A 788 #define A_SCD_TRACE_SEQUENCE_6 0x0010020A 789 #define A_SCD_TRACE_SEQUENCE_7 0x0010020A 790 791 #define TRACE_REGISTER_SPACING 8 792 #define TRACE_NUM_REGISTERS 8 793 #define A_SCD_TRACE_EVENT(n) (((n) & 4) ? \ 794 (A_SCD_TRACE_EVENT_4 + (((n) & 3) * TRACE_R 795 (A_SCD_TRACE_EVENT_0 + ((n) * TRACE_REGISTE 796 #define A_SCD_TRACE_SEQUENCE(n) (((n) & 4) ? \ 797 (A_SCD_TRACE_SEQUENCE_4 + (((n) & 3) * TRAC 798 (A_SCD_TRACE_SEQUENCE_0 + ((n) * TRACE_REGI 799 800 /* ****************************************** 801 * System Generic DMA Registers 802 ****************************************** 803 804 #define A_DM_0 0x0010020B 805 #define A_DM_1 0x0010020B 806 #define A_DM_2 0x0010020B 807 #define A_DM_3 0x0010020B 808 #define DM_REGISTER_SPACING 0x20 809 #define DM_NUM_CHANNELS 4 810 #define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_R 811 #define A_DM_REGISTER(idx, reg) (A_DM_BASE(idx 812 813 #define R_DM_DSCR_BASE 0x00000000 814 #define R_DM_DSCR_COUNT 0x00000000 815 #define R_DM_CUR_DSCR_ADDR 0x00000000 816 #define R_DM_DSCR_BASE_DEBUG 0x00000000 817 818 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_ 819 #define A_DM_PARTIAL_0 0x0010020b 820 #define A_DM_PARTIAL_1 0x0010020b 821 #define A_DM_PARTIAL_2 0x0010020b 822 #define A_DM_PARTIAL_3 0x0010020b 823 #define DM_PARTIAL_REGISTER_SPACING 0x8 824 #define A_DM_PARTIAL(idx) (A_DM_PART 825 #endif /* 1250 PASS3 || 112x PASS1 */ 826 827 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_ 828 #define A_DM_CRC_0 0x0010020b 829 #define A_DM_CRC_1 0x0010020b 830 #define DM_CRC_REGISTER_SPACING 0x10 831 #define DM_CRC_NUM_CHANNELS 2 832 #define A_DM_CRC_BASE(idx) (A_DM_CRC_ 833 #define A_DM_CRC_REGISTER(idx, reg) (A_DM_CRC 834 835 #define R_CRC_DEF_0 0x00 836 #define R_CTCP_DEF_0 0x08 837 #endif /* 1250 PASS3 || 112x PASS1 */ 838 839 /* ****************************************** 840 * Physical Address Map 841 ****************************************** 842 843 #if SIBYTE_HDR_FEATURE_1250_112x 844 #define A_PHYS_MEMORY_0 _SB_MA 845 #define A_PHYS_MEMORY_SIZE _SB_MA 846 #define A_PHYS_SYSTEM_CTL _SB_MA 847 #define A_PHYS_IO_SYSTEM _SB_MA 848 #define A_PHYS_GENBUS _SB_MA 849 #define A_PHYS_GENBUS_END _SB_MA 850 #define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MA 851 #define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MA 852 #define A_PHYS_MEMORY_1 _SB_MA 853 #define A_PHYS_MEMORY_2 _SB_MA 854 #define A_PHYS_MEMORY_3 _SB_MA 855 #define A_PHYS_L2_CACHE_TEST _SB_MA 856 #define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MA 857 #define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MA 858 #define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MA 859 #define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MA 860 #define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MA 861 #define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MA 862 #define A_PHYS_MEMORY_EXP _SB_MA 863 #define A_PHYS_MEMORY_EXP_SIZE _SB_MA 864 #define A_PHYS_LDT_EXP _SB_MA 865 #define A_PHYS_PCI_FULLACCESS_BYTES _SB_MA 866 #define A_PHYS_PCI_FULLACCESS_BITS _SB_MA 867 #define A_PHYS_RESERVED _SB_MA 868 #define A_PHYS_RESERVED_SPECIAL_LDT _SB_MA 869 870 #define A_PHYS_L2CACHE_WAY_SIZE _SB_MA 871 #define PHYS_L2CACHE_NUM_WAYS 4 872 #define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MA 873 #define A_PHYS_L2CACHE_WAY0 _SB_MA 874 #define A_PHYS_L2CACHE_WAY1 _SB_MA 875 #define A_PHYS_L2CACHE_WAY2 _SB_MA 876 #define A_PHYS_L2CACHE_WAY3 _SB_MA 877 #endif 878 879 880 #endif 881
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