1 /* 1 /*
2 * This file is subject to the terms and condi 2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the mai 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf 6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, 7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
>> 8 * Copyright (C) 2001 MIPS Technologies, Inc.
8 * Copyright (C) 2002, 2007 Maciej W. Rozycki 9 * Copyright (C) 2002, 2007 Maciej W. Rozycki
9 * Copyright (C) 2001, 2012 MIPS Technologies, <<
10 */ 10 */
11 #include <linux/init.h> 11 #include <linux/init.h>
12 12
13 #include <asm/asm.h> 13 #include <asm/asm.h>
14 #include <asm/asmmacro.h> 14 #include <asm/asmmacro.h>
15 #include <asm/cacheops.h> 15 #include <asm/cacheops.h>
16 #include <asm/irqflags.h> 16 #include <asm/irqflags.h>
17 #include <asm/regdef.h> 17 #include <asm/regdef.h>
18 #include <asm/fpregdef.h> 18 #include <asm/fpregdef.h>
19 #include <asm/mipsregs.h> 19 #include <asm/mipsregs.h>
20 #include <asm/stackframe.h> 20 #include <asm/stackframe.h>
21 #include <asm/sync.h> !! 21 #include <asm/war.h>
>> 22 #include <asm/page.h>
22 #include <asm/thread_info.h> 23 #include <asm/thread_info.h>
23 24
>> 25 #define PANIC_PIC(msg) \
>> 26 .set push; \
>> 27 .set reorder; \
>> 28 PTR_LA a0,8f; \
>> 29 .set noat; \
>> 30 PTR_LA AT, panic; \
>> 31 jr AT; \
>> 32 9: b 9b; \
>> 33 .set pop; \
>> 34 TEXT(msg)
>> 35
24 __INIT 36 __INIT
25 37
>> 38 NESTED(except_vec0_generic, 0, sp)
>> 39 PANIC_PIC("Exception vector 0 called")
>> 40 END(except_vec0_generic)
>> 41
>> 42 NESTED(except_vec1_generic, 0, sp)
>> 43 PANIC_PIC("Exception vector 1 called")
>> 44 END(except_vec1_generic)
>> 45
26 /* 46 /*
27 * General exception vector for all other CPUs 47 * General exception vector for all other CPUs.
28 * 48 *
29 * Be careful when changing this, it has to be 49 * Be careful when changing this, it has to be at most 128 bytes
30 * to fit into space reserved for the exceptio 50 * to fit into space reserved for the exception handler.
31 */ 51 */
32 NESTED(except_vec3_generic, 0, sp) 52 NESTED(except_vec3_generic, 0, sp)
33 .set push 53 .set push
34 .set noat 54 .set noat
>> 55 #if R5432_CP0_INTERRUPT_WAR
>> 56 mfc0 k0, CP0_INDEX
>> 57 #endif
35 mfc0 k1, CP0_CAUSE 58 mfc0 k1, CP0_CAUSE
36 andi k1, k1, 0x7c 59 andi k1, k1, 0x7c
37 #ifdef CONFIG_64BIT 60 #ifdef CONFIG_64BIT
38 dsll k1, k1, 1 61 dsll k1, k1, 1
39 #endif 62 #endif
40 PTR_L k0, exception_handlers(k1) 63 PTR_L k0, exception_handlers(k1)
41 jr k0 64 jr k0
42 .set pop 65 .set pop
43 END(except_vec3_generic) 66 END(except_vec3_generic)
44 67
45 /* 68 /*
46 * General exception handler for CPUs with vir 69 * General exception handler for CPUs with virtual coherency exception.
47 * 70 *
48 * Be careful when changing this, it has to be 71 * Be careful when changing this, it has to be at most 256 (as a special
49 * exception) bytes to fit into space reserved 72 * exception) bytes to fit into space reserved for the exception handler.
50 */ 73 */
51 NESTED(except_vec3_r4000, 0, sp) 74 NESTED(except_vec3_r4000, 0, sp)
52 .set push 75 .set push
53 .set arch=r4000 !! 76 .set mips3
54 .set noat 77 .set noat
55 mfc0 k1, CP0_CAUSE 78 mfc0 k1, CP0_CAUSE
56 li k0, 31<<2 79 li k0, 31<<2
57 andi k1, k1, 0x7c 80 andi k1, k1, 0x7c
58 .set push 81 .set push
59 .set noreorder 82 .set noreorder
60 .set nomacro 83 .set nomacro
61 beq k1, k0, handle_vced 84 beq k1, k0, handle_vced
62 li k0, 14<<2 85 li k0, 14<<2
63 beq k1, k0, handle_vcei 86 beq k1, k0, handle_vcei
64 #ifdef CONFIG_64BIT 87 #ifdef CONFIG_64BIT
65 dsll k1, k1, 1 88 dsll k1, k1, 1
66 #endif 89 #endif
67 .set pop 90 .set pop
68 PTR_L k0, exception_handlers(k1) 91 PTR_L k0, exception_handlers(k1)
69 jr k0 92 jr k0
70 93
71 /* 94 /*
72 * Big shit, we now may have two dirty 95 * Big shit, we now may have two dirty primary cache lines for the same
73 * physical address. We can safely in 96 * physical address. We can safely invalidate the line pointed to by
74 * c0_badvaddr because after return fr 97 * c0_badvaddr because after return from this exception handler the
75 * load / store will be re-executed. 98 * load / store will be re-executed.
76 */ 99 */
77 handle_vced: 100 handle_vced:
78 MFC0 k0, CP0_BADVADDR 101 MFC0 k0, CP0_BADVADDR
79 li k1, -4 102 li k1, -4 # Is this ...
80 and k0, k1 103 and k0, k1 # ... really needed?
81 mtc0 zero, CP0_TAGLO 104 mtc0 zero, CP0_TAGLO
82 cache Index_Store_Tag_D, (k0) 105 cache Index_Store_Tag_D, (k0)
83 cache Hit_Writeback_Inv_SD, (k0) 106 cache Hit_Writeback_Inv_SD, (k0)
84 #ifdef CONFIG_PROC_FS 107 #ifdef CONFIG_PROC_FS
85 PTR_LA k0, vced_count 108 PTR_LA k0, vced_count
86 lw k1, (k0) 109 lw k1, (k0)
87 addiu k1, 1 110 addiu k1, 1
88 sw k1, (k0) 111 sw k1, (k0)
89 #endif 112 #endif
90 eret 113 eret
91 114
92 handle_vcei: 115 handle_vcei:
93 MFC0 k0, CP0_BADVADDR 116 MFC0 k0, CP0_BADVADDR
94 cache Hit_Writeback_Inv_SD, (k0) 117 cache Hit_Writeback_Inv_SD, (k0) # also cleans pi
95 #ifdef CONFIG_PROC_FS 118 #ifdef CONFIG_PROC_FS
96 PTR_LA k0, vcei_count 119 PTR_LA k0, vcei_count
97 lw k1, (k0) 120 lw k1, (k0)
98 addiu k1, 1 121 addiu k1, 1
99 sw k1, (k0) 122 sw k1, (k0)
100 #endif 123 #endif
101 eret 124 eret
102 .set pop 125 .set pop
103 END(except_vec3_r4000) 126 END(except_vec3_r4000)
104 127
105 __FINIT 128 __FINIT
106 129
107 .align 5 /* 32 byte rollback re 130 .align 5 /* 32 byte rollback region */
108 LEAF(__r4k_wait) !! 131 LEAF(r4k_wait)
109 .set push 132 .set push
110 .set noreorder 133 .set noreorder
111 /* start of rollback region */ 134 /* start of rollback region */
112 LONG_L t0, TI_FLAGS($28) 135 LONG_L t0, TI_FLAGS($28)
113 nop 136 nop
114 andi t0, _TIF_NEED_RESCHED 137 andi t0, _TIF_NEED_RESCHED
115 bnez t0, 1f 138 bnez t0, 1f
116 nop 139 nop
117 nop 140 nop
118 nop 141 nop
119 #ifdef CONFIG_CPU_MICROMIPS !! 142 .set mips3
120 nop <<
121 nop <<
122 nop <<
123 nop <<
124 #endif <<
125 .set MIPS_ISA_ARCH_LEVEL_RAW <<
126 wait 143 wait
127 /* end of rollback region (the region 144 /* end of rollback region (the region size must be power of two) */
>> 145 .set pop
128 1: 146 1:
129 jr ra 147 jr ra
130 nop !! 148 END(r4k_wait)
131 .set pop <<
132 END(__r4k_wait) <<
133 149
134 .macro BUILD_ROLLBACK_PROLOGUE handle 150 .macro BUILD_ROLLBACK_PROLOGUE handler
135 FEXPORT(rollback_\handler) 151 FEXPORT(rollback_\handler)
136 .set push 152 .set push
137 .set noat 153 .set noat
138 MFC0 k0, CP0_EPC 154 MFC0 k0, CP0_EPC
139 PTR_LA k1, __r4k_wait !! 155 PTR_LA k1, r4k_wait
140 ori k0, 0x1f /* 32 byte rol 156 ori k0, 0x1f /* 32 byte rollback region */
141 xori k0, 0x1f 157 xori k0, 0x1f
142 bne k0, k1, \handler !! 158 bne k0, k1, 9f
143 MTC0 k0, CP0_EPC 159 MTC0 k0, CP0_EPC
>> 160 9:
144 .set pop 161 .set pop
145 .endm 162 .endm
146 163
147 .align 5 !! 164 .align 5
148 BUILD_ROLLBACK_PROLOGUE handle_int 165 BUILD_ROLLBACK_PROLOGUE handle_int
149 NESTED(handle_int, PT_SIZE, sp) 166 NESTED(handle_int, PT_SIZE, sp)
150 .cfi_signal_frame <<
151 #ifdef CONFIG_TRACE_IRQFLAGS 167 #ifdef CONFIG_TRACE_IRQFLAGS
152 /* 168 /*
153 * Check to see if the interrupted cod 169 * Check to see if the interrupted code has just disabled
154 * interrupts and ignore this interrup 170 * interrupts and ignore this interrupt for now if so.
155 * 171 *
156 * local_irq_disable() disables interr 172 * local_irq_disable() disables interrupts and then calls
157 * trace_hardirqs_off() to track the s 173 * trace_hardirqs_off() to track the state. If an interrupt is taken
158 * after interrupts are disabled but b 174 * after interrupts are disabled but before the state is updated
159 * it will appear to restore_all that 175 * it will appear to restore_all that it is incorrectly returning with
160 * interrupts disabled 176 * interrupts disabled
161 */ 177 */
162 .set push 178 .set push
163 .set noat 179 .set noat
164 mfc0 k0, CP0_STATUS 180 mfc0 k0, CP0_STATUS
165 #if defined(CONFIG_CPU_R3000) !! 181 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
166 and k0, ST0_IEP 182 and k0, ST0_IEP
167 bnez k0, 1f 183 bnez k0, 1f
168 184
169 mfc0 k0, CP0_EPC 185 mfc0 k0, CP0_EPC
170 .set noreorder 186 .set noreorder
171 j k0 187 j k0
172 rfe !! 188 rfe
173 #else 189 #else
174 and k0, ST0_IE 190 and k0, ST0_IE
175 bnez k0, 1f 191 bnez k0, 1f
176 192
177 eret 193 eret
178 #endif 194 #endif
179 1: 195 1:
180 .set pop 196 .set pop
181 #endif 197 #endif
182 SAVE_ALL docfi=1 !! 198 SAVE_ALL
183 CLI 199 CLI
184 TRACE_IRQS_OFF 200 TRACE_IRQS_OFF
185 201
186 LONG_L s0, TI_REGS($28) 202 LONG_L s0, TI_REGS($28)
187 LONG_S sp, TI_REGS($28) 203 LONG_S sp, TI_REGS($28)
188 !! 204 PTR_LA ra, ret_from_irq
189 /* !! 205 j plat_irq_dispatch
190 * SAVE_ALL ensures we are using a val <<
191 * Check if we are already using the I <<
192 */ <<
193 move s1, sp # Preserve the sp <<
194 <<
195 /* Get IRQ stack for this CPU */ <<
196 ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG <<
197 #if defined(CONFIG_32BIT) || defined(KBUILD_64 <<
198 lui k1, %hi(irq_stack) <<
199 #else <<
200 lui k1, %highest(irq_stack) <<
201 daddiu k1, %higher(irq_stack) <<
202 dsll k1, 16 <<
203 daddiu k1, %hi(irq_stack) <<
204 dsll k1, 16 <<
205 #endif <<
206 LONG_SRL k0, SMP_CPUID_PTRSHIFT <<
207 LONG_ADDU k1, k0 <<
208 LONG_L t0, %lo(irq_stack)(k1) <<
209 <<
210 # Check if already on IRQ stack <<
211 PTR_LI t1, ~(_THREAD_SIZE-1) <<
212 and t1, t1, sp <<
213 beq t0, t1, 2f <<
214 <<
215 /* Switch to IRQ stack */ <<
216 li t1, _IRQ_STACK_START <<
217 PTR_ADD sp, t0, t1 <<
218 <<
219 /* Save task's sp on IRQ stack so that <<
220 LONG_S s1, 0(sp) <<
221 2: <<
222 jal plat_irq_dispatch <<
223 <<
224 /* Restore sp */ <<
225 move sp, s1 <<
226 <<
227 j ret_from_irq <<
228 #ifdef CONFIG_CPU_MICROMIPS <<
229 nop <<
230 #endif <<
231 END(handle_int) 206 END(handle_int)
232 207
233 __INIT 208 __INIT
234 209
235 /* 210 /*
236 * Special interrupt vector for MIPS64 ISA & e 211 * Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
237 * This is a dedicated interrupt exception vec 212 * This is a dedicated interrupt exception vector which reduces the
238 * interrupt processing overhead. The jump in 213 * interrupt processing overhead. The jump instruction will be replaced
239 * at the initialization time. 214 * at the initialization time.
240 * 215 *
241 * Be careful when changing this, it has to be 216 * Be careful when changing this, it has to be at most 128 bytes
242 * to fit into space reserved for the exceptio 217 * to fit into space reserved for the exception handler.
243 */ 218 */
244 NESTED(except_vec4, 0, sp) 219 NESTED(except_vec4, 0, sp)
245 1: j 1b /* Dum 220 1: j 1b /* Dummy, will be replaced */
246 END(except_vec4) 221 END(except_vec4)
247 222
248 /* 223 /*
249 * EJTAG debug exception handler. 224 * EJTAG debug exception handler.
250 * The EJTAG debug exception entry point is 0x 225 * The EJTAG debug exception entry point is 0xbfc00480, which
251 * normally is in the boot PROM, so the boot P !! 226 * normally is in the boot PROM, so the boot PROM must do a
252 * unconditional jump to this vector. 227 * unconditional jump to this vector.
253 */ 228 */
254 NESTED(except_vec_ejtag_debug, 0, sp) 229 NESTED(except_vec_ejtag_debug, 0, sp)
255 j ejtag_debug_handler 230 j ejtag_debug_handler
256 #ifdef CONFIG_CPU_MICROMIPS <<
257 nop <<
258 #endif <<
259 END(except_vec_ejtag_debug) 231 END(except_vec_ejtag_debug)
260 232
261 __FINIT 233 __FINIT
262 234
263 /* 235 /*
264 * Vectored interrupt handler. 236 * Vectored interrupt handler.
265 * This prototype is copied to ebase + n*IntCt 237 * This prototype is copied to ebase + n*IntCtl.VS and patched
266 * to invoke the handler 238 * to invoke the handler
267 */ 239 */
268 BUILD_ROLLBACK_PROLOGUE except_vec_vi 240 BUILD_ROLLBACK_PROLOGUE except_vec_vi
269 NESTED(except_vec_vi, 0, sp) 241 NESTED(except_vec_vi, 0, sp)
270 SAVE_SOME docfi=1 !! 242 SAVE_SOME
271 SAVE_AT docfi=1 !! 243 SAVE_AT
272 .set push 244 .set push
273 .set noreorder 245 .set noreorder
274 PTR_LA v1, except_vec_vi_handler !! 246 #ifdef CONFIG_MIPS_MT_SMTC
275 jr v1 !! 247 /*
>> 248 * To keep from blindly blocking *all* interrupts
>> 249 * during service by SMTC kernel, we also want to
>> 250 * pass the IM value to be cleared.
>> 251 */
>> 252 FEXPORT(except_vec_vi_mori)
>> 253 ori a0, $0, 0
>> 254 #endif /* CONFIG_MIPS_MT_SMTC */
>> 255 FEXPORT(except_vec_vi_lui)
>> 256 lui v0, 0 /* Patched */
>> 257 j except_vec_vi_handler
276 FEXPORT(except_vec_vi_ori) 258 FEXPORT(except_vec_vi_ori)
277 ori v0, zero, 0 /* Off !! 259 ori v0, 0 /* Patched */
278 .set pop 260 .set pop
279 END(except_vec_vi) 261 END(except_vec_vi)
280 EXPORT(except_vec_vi_end) 262 EXPORT(except_vec_vi_end)
281 263
282 /* 264 /*
283 * Common Vectored Interrupt code 265 * Common Vectored Interrupt code
284 * Complete the register saves and invoke the !! 266 * Complete the register saves and invoke the handler which is passed in $v0
285 * offset into vi_handlers[] <<
286 */ 267 */
287 NESTED(except_vec_vi_handler, 0, sp) 268 NESTED(except_vec_vi_handler, 0, sp)
288 SAVE_TEMP 269 SAVE_TEMP
289 SAVE_STATIC 270 SAVE_STATIC
>> 271 #ifdef CONFIG_MIPS_MT_SMTC
>> 272 /*
>> 273 * SMTC has an interesting problem that interrupts are level-triggered,
>> 274 * and the CLI macro will clear EXL, potentially causing a duplicate
>> 275 * interrupt service invocation. So we need to clear the associated
>> 276 * IM bit of Status prior to doing CLI, and restore it after the
>> 277 * service routine has been invoked - we must assume that the
>> 278 * service routine will have cleared the state, and any active
>> 279 * level represents a new or otherwised unserviced event...
>> 280 */
>> 281 mfc0 t1, CP0_STATUS
>> 282 and t0, a0, t1
>> 283 #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
>> 284 mfc0 t2, CP0_TCCONTEXT
>> 285 or t2, t0, t2
>> 286 mtc0 t2, CP0_TCCONTEXT
>> 287 #endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
>> 288 xor t1, t1, t0
>> 289 mtc0 t1, CP0_STATUS
>> 290 _ehb
>> 291 #endif /* CONFIG_MIPS_MT_SMTC */
290 CLI 292 CLI
291 #ifdef CONFIG_TRACE_IRQFLAGS 293 #ifdef CONFIG_TRACE_IRQFLAGS
292 move s0, v0 294 move s0, v0
>> 295 #ifdef CONFIG_MIPS_MT_SMTC
>> 296 move s1, a0
>> 297 #endif
293 TRACE_IRQS_OFF 298 TRACE_IRQS_OFF
>> 299 #ifdef CONFIG_MIPS_MT_SMTC
>> 300 move a0, s1
>> 301 #endif
294 move v0, s0 302 move v0, s0
295 #endif 303 #endif
296 304
297 LONG_L s0, TI_REGS($28) 305 LONG_L s0, TI_REGS($28)
298 LONG_S sp, TI_REGS($28) 306 LONG_S sp, TI_REGS($28)
299 !! 307 PTR_LA ra, ret_from_irq
300 /* !! 308 jr v0
301 * SAVE_ALL ensures we are using a val <<
302 * Check if we are already using the I <<
303 */ <<
304 move s1, sp # Preserve the sp <<
305 <<
306 /* Get IRQ stack for this CPU */ <<
307 ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG <<
308 #if defined(CONFIG_32BIT) || defined(KBUILD_64 <<
309 lui k1, %hi(irq_stack) <<
310 #else <<
311 lui k1, %highest(irq_stack) <<
312 daddiu k1, %higher(irq_stack) <<
313 dsll k1, 16 <<
314 daddiu k1, %hi(irq_stack) <<
315 dsll k1, 16 <<
316 #endif <<
317 LONG_SRL k0, SMP_CPUID_PTRSHIFT <<
318 LONG_ADDU k1, k0 <<
319 LONG_L t0, %lo(irq_stack)(k1) <<
320 <<
321 # Check if already on IRQ stack <<
322 PTR_LI t1, ~(_THREAD_SIZE-1) <<
323 and t1, t1, sp <<
324 beq t0, t1, 2f <<
325 <<
326 /* Switch to IRQ stack */ <<
327 li t1, _IRQ_STACK_START <<
328 PTR_ADD sp, t0, t1 <<
329 <<
330 /* Save task's sp on IRQ stack so that <<
331 LONG_S s1, 0(sp) <<
332 2: <<
333 PTR_L v0, vi_handlers(v0) <<
334 jalr v0 <<
335 <<
336 /* Restore sp */ <<
337 move sp, s1 <<
338 <<
339 j ret_from_irq <<
340 END(except_vec_vi_handler) 309 END(except_vec_vi_handler)
341 310
342 /* 311 /*
343 * EJTAG debug exception handler. 312 * EJTAG debug exception handler.
344 */ 313 */
345 NESTED(ejtag_debug_handler, PT_SIZE, sp) 314 NESTED(ejtag_debug_handler, PT_SIZE, sp)
346 .set push 315 .set push
347 .set noat 316 .set noat
348 MTC0 k0, CP0_DESAVE 317 MTC0 k0, CP0_DESAVE
349 mfc0 k0, CP0_DEBUG 318 mfc0 k0, CP0_DEBUG
350 319
351 andi k0, k0, MIPS_DEBUG_DBP # Chec !! 320 sll k0, k0, 30 # Check for SDBBP.
352 beqz k0, ejtag_return !! 321 bgez k0, ejtag_return
353 <<
354 #ifdef CONFIG_SMP <<
355 1: PTR_LA k0, ejtag_debug_buffer_spinloc <<
356 __SYNC(full, loongson3_war) <<
357 2: ll k0, 0(k0) <<
358 bnez k0, 2b <<
359 PTR_LA k0, ejtag_debug_buffer_spinloc <<
360 sc k0, 0(k0) <<
361 beqz k0, 1b <<
362 # ifdef CONFIG_WEAK_REORDERING_BEYOND_LLSC <<
363 sync <<
364 # endif <<
365 <<
366 PTR_LA k0, ejtag_debug_buffer <<
367 LONG_S k1, 0(k0) <<
368 <<
369 ASM_CPUID_MFC0 k1, ASM_SMP_CPUID_REG <<
370 PTR_SRL k1, SMP_CPUID_PTRSHIFT <<
371 PTR_SLL k1, LONGLOG <<
372 PTR_LA k0, ejtag_debug_buffer_per_cpu <<
373 PTR_ADDU k0, k1 <<
374 322
375 PTR_LA k1, ejtag_debug_buffer <<
376 LONG_L k1, 0(k1) <<
377 LONG_S k1, 0(k0) <<
378 <<
379 PTR_LA k0, ejtag_debug_buffer_spinloc <<
380 sw zero, 0(k0) <<
381 #else <<
382 PTR_LA k0, ejtag_debug_buffer 323 PTR_LA k0, ejtag_debug_buffer
383 LONG_S k1, 0(k0) 324 LONG_S k1, 0(k0)
384 #endif <<
385 <<
386 SAVE_ALL 325 SAVE_ALL
387 move a0, sp 326 move a0, sp
388 jal ejtag_exception_handler 327 jal ejtag_exception_handler
389 RESTORE_ALL 328 RESTORE_ALL
390 <<
391 #ifdef CONFIG_SMP <<
392 ASM_CPUID_MFC0 k1, ASM_SMP_CPUID_REG <<
393 PTR_SRL k1, SMP_CPUID_PTRSHIFT <<
394 PTR_SLL k1, LONGLOG <<
395 PTR_LA k0, ejtag_debug_buffer_per_cpu <<
396 PTR_ADDU k0, k1 <<
397 LONG_L k1, 0(k0) <<
398 #else <<
399 PTR_LA k0, ejtag_debug_buffer 329 PTR_LA k0, ejtag_debug_buffer
400 LONG_L k1, 0(k0) 330 LONG_L k1, 0(k0)
401 #endif <<
402 331
403 ejtag_return: 332 ejtag_return:
404 back_to_back_c0_hazard <<
405 MFC0 k0, CP0_DESAVE 333 MFC0 k0, CP0_DESAVE
406 .set mips32 334 .set mips32
407 deret 335 deret
408 .set pop !! 336 .set pop
409 END(ejtag_debug_handler) 337 END(ejtag_debug_handler)
410 338
411 /* 339 /*
412 * This buffer is reserved for the use of the 340 * This buffer is reserved for the use of the EJTAG debug
413 * handler. 341 * handler.
414 */ 342 */
415 .data 343 .data
416 EXPORT(ejtag_debug_buffer) 344 EXPORT(ejtag_debug_buffer)
417 .fill LONGSIZE 345 .fill LONGSIZE
418 #ifdef CONFIG_SMP <<
419 EXPORT(ejtag_debug_buffer_spinlock) <<
420 .fill LONGSIZE <<
421 EXPORT(ejtag_debug_buffer_per_cpu) <<
422 .fill LONGSIZE * NR_CPUS <<
423 #endif <<
424 .previous 346 .previous
425 347
426 __INIT 348 __INIT
427 349
428 /* 350 /*
429 * NMI debug exception handler for MIPS refere 351 * NMI debug exception handler for MIPS reference boards.
430 * The NMI debug exception entry point is 0xbf 352 * The NMI debug exception entry point is 0xbfc00000, which
431 * normally is in the boot PROM, so the boot P 353 * normally is in the boot PROM, so the boot PROM must do a
432 * unconditional jump to this vector. 354 * unconditional jump to this vector.
433 */ 355 */
434 NESTED(except_vec_nmi, 0, sp) 356 NESTED(except_vec_nmi, 0, sp)
435 j nmi_handler 357 j nmi_handler
436 #ifdef CONFIG_CPU_MICROMIPS <<
437 nop <<
438 #endif <<
439 END(except_vec_nmi) 358 END(except_vec_nmi)
440 359
441 __FINIT 360 __FINIT
442 361
443 NESTED(nmi_handler, PT_SIZE, sp) 362 NESTED(nmi_handler, PT_SIZE, sp)
444 .cfi_signal_frame <<
445 .set push 363 .set push
446 .set noat 364 .set noat
447 /* <<
448 * Clear ERL - restore segment mapping <<
449 * Clear BEV - required for page fault <<
450 */ <<
451 mfc0 k0, CP0_STATUS <<
452 ori k0, k0, ST0_EXL <<
453 li k1, ~(ST0_BEV | ST0_ERL) <<
454 and k0, k0, k1 <<
455 mtc0 k0, CP0_STATUS <<
456 _ehb <<
457 SAVE_ALL 365 SAVE_ALL
458 move a0, sp !! 366 move a0, sp
459 jal nmi_exception_handler 367 jal nmi_exception_handler
460 /* nmi_exception_handler never returns !! 368 RESTORE_ALL
>> 369 .set mips3
>> 370 eret
461 .set pop 371 .set pop
462 END(nmi_handler) 372 END(nmi_handler)
463 373
464 .macro __build_clear_none 374 .macro __build_clear_none
465 .endm 375 .endm
466 376
467 .macro __build_clear_sti 377 .macro __build_clear_sti
468 TRACE_IRQS_ON 378 TRACE_IRQS_ON
469 STI 379 STI
470 .endm 380 .endm
471 381
472 .macro __build_clear_cli 382 .macro __build_clear_cli
473 CLI 383 CLI
474 TRACE_IRQS_OFF 384 TRACE_IRQS_OFF
475 .endm 385 .endm
476 386
477 .macro __build_clear_fpe 387 .macro __build_clear_fpe
478 CLI <<
479 TRACE_IRQS_OFF <<
480 .set push 388 .set push
481 /* gas fails to assemble cfc1 for some 389 /* gas fails to assemble cfc1 for some archs (octeon).*/ \
482 .set mips1 390 .set mips1
483 .set hardfloat <<
484 cfc1 a1, fcr31 391 cfc1 a1, fcr31
>> 392 li a2, ~(0x3f << 12)
>> 393 and a2, a1
>> 394 ctc1 a2, fcr31
485 .set pop 395 .set pop
486 .endm !! 396 TRACE_IRQS_ON
487 !! 397 STI
488 .macro __build_clear_msa_fpe <<
489 CLI <<
490 TRACE_IRQS_OFF <<
491 _cfcmsa a1, MSA_CSR <<
492 .endm 398 .endm
493 399
494 .macro __build_clear_ade 400 .macro __build_clear_ade
495 MFC0 t0, CP0_BADVADDR 401 MFC0 t0, CP0_BADVADDR
496 PTR_S t0, PT_BVADDR(sp) 402 PTR_S t0, PT_BVADDR(sp)
497 KMODE 403 KMODE
498 .endm 404 .endm
499 405
500 .macro __build_clear_gsexc <<
501 .set push <<
502 /* <<
503 * We need to specify a selector to ac <<
504 * register. All GSExc-equipped proces <<
505 */ <<
506 .set mips32 <<
507 mfc0 a1, CP0_DIAGNOSTIC1 <<
508 .set pop <<
509 TRACE_IRQS_ON <<
510 STI <<
511 .endm <<
512 <<
513 .macro __BUILD_silent exception 406 .macro __BUILD_silent exception
514 .endm 407 .endm
515 408
516 /* Gas tries to parse the ASM_PRINT ar !! 409 /* Gas tries to parse the PRINT argument as a string containing
517 string escapes and emits bogus warn 410 string escapes and emits bogus warnings if it believes to
518 recognize an unknown escape code. 411 recognize an unknown escape code. So make the arguments
519 start with an n and gas will believ 412 start with an n and gas will believe \n is ok ... */
520 .macro __BUILD_verbose nexception !! 413 .macro __BUILD_verbose nexception
521 LONG_L a1, PT_EPC(sp) 414 LONG_L a1, PT_EPC(sp)
522 #ifdef CONFIG_32BIT 415 #ifdef CONFIG_32BIT
523 ASM_PRINT("Got \nexception at %08lx\01 !! 416 PRINT("Got \nexception at %08lx\012")
524 #endif 417 #endif
525 #ifdef CONFIG_64BIT 418 #ifdef CONFIG_64BIT
526 ASM_PRINT("Got \nexception at %016lx\0 !! 419 PRINT("Got \nexception at %016lx\012")
527 #endif 420 #endif
528 .endm 421 .endm
529 422
530 .macro __BUILD_count exception 423 .macro __BUILD_count exception
531 LONG_L t0,exception_count_\exception 424 LONG_L t0,exception_count_\exception
532 LONG_ADDIU t0, 1 !! 425 LONG_ADDIU t0, 1
533 LONG_S t0,exception_count_\exception 426 LONG_S t0,exception_count_\exception
534 .comm exception_count\exception, 8, 427 .comm exception_count\exception, 8, 8
535 .endm 428 .endm
536 429
537 .macro __BUILD_HANDLER exception hand 430 .macro __BUILD_HANDLER exception handler clear verbose ext
538 .align 5 431 .align 5
539 NESTED(handle_\exception, PT_SIZE, sp) 432 NESTED(handle_\exception, PT_SIZE, sp)
540 .cfi_signal_frame <<
541 .set noat 433 .set noat
542 SAVE_ALL 434 SAVE_ALL
543 FEXPORT(handle_\exception\ext) 435 FEXPORT(handle_\exception\ext)
544 __build_clear_\clear !! 436 __BUILD_clear_\clear
545 .set at 437 .set at
546 __BUILD_\verbose \exception 438 __BUILD_\verbose \exception
547 move a0, sp 439 move a0, sp
548 jal do_\handler !! 440 PTR_LA ra, ret_from_exception
549 j ret_from_exception !! 441 j do_\handler
550 END(handle_\exception) 442 END(handle_\exception)
551 .endm 443 .endm
552 444
553 .macro BUILD_HANDLER exception handle 445 .macro BUILD_HANDLER exception handler clear verbose
554 __BUILD_HANDLER \exception \handler \c !! 446 __BUILD_HANDLER \exception \handler \clear \verbose _int
555 .endm 447 .endm
556 448
557 BUILD_HANDLER adel ade ade silent 449 BUILD_HANDLER adel ade ade silent /* #4 */
558 BUILD_HANDLER ades ade ade silent 450 BUILD_HANDLER ades ade ade silent /* #5 */
559 BUILD_HANDLER ibe be cli silent 451 BUILD_HANDLER ibe be cli silent /* #6 */
560 BUILD_HANDLER dbe be cli silent 452 BUILD_HANDLER dbe be cli silent /* #7 */
561 BUILD_HANDLER bp bp sti silent 453 BUILD_HANDLER bp bp sti silent /* #9 */
562 BUILD_HANDLER ri ri sti silent 454 BUILD_HANDLER ri ri sti silent /* #10 */
563 BUILD_HANDLER cpu cpu sti silent 455 BUILD_HANDLER cpu cpu sti silent /* #11 */
564 BUILD_HANDLER ov ov sti silent 456 BUILD_HANDLER ov ov sti silent /* #12 */
565 BUILD_HANDLER tr tr sti silent 457 BUILD_HANDLER tr tr sti silent /* #13 */
566 BUILD_HANDLER msa_fpe msa_fpe msa_fpe <<
567 #ifdef CONFIG_MIPS_FP_SUPPORT <<
568 BUILD_HANDLER fpe fpe fpe silent 458 BUILD_HANDLER fpe fpe fpe silent /* #15 */
569 #endif <<
570 BUILD_HANDLER ftlb ftlb none silent <<
571 BUILD_HANDLER gsexc gsexc gsexc silent <<
572 BUILD_HANDLER msa msa sti silent <<
573 BUILD_HANDLER mdmx mdmx sti silent 459 BUILD_HANDLER mdmx mdmx sti silent /* #22 */
574 #ifdef CONFIG_HARDWARE_WATCHPOINTS !! 460 #ifdef CONFIG_HARDWARE_WATCHPOINTS
575 /* 461 /*
576 * For watch, interrupts will be enabl 462 * For watch, interrupts will be enabled after the watch
577 * registers are read. 463 * registers are read.
578 */ 464 */
579 BUILD_HANDLER watch watch cli silent 465 BUILD_HANDLER watch watch cli silent /* #23 */
580 #else 466 #else
581 BUILD_HANDLER watch watch sti verbose 467 BUILD_HANDLER watch watch sti verbose /* #23 */
582 #endif 468 #endif
583 BUILD_HANDLER mcheck mcheck cli verbos 469 BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
584 BUILD_HANDLER mt mt sti silent 470 BUILD_HANDLER mt mt sti silent /* #25 */
585 BUILD_HANDLER dsp dsp sti silent 471 BUILD_HANDLER dsp dsp sti silent /* #26 */
586 BUILD_HANDLER reserved reserved sti ve 472 BUILD_HANDLER reserved reserved sti verbose /* others */
587 473
588 .align 5 474 .align 5
589 LEAF(handle_ri_rdhwr_tlbp) !! 475 LEAF(handle_ri_rdhwr_vivt)
>> 476 #ifdef CONFIG_MIPS_MT_SMTC
>> 477 PANIC_PIC("handle_ri_rdhwr_vivt called")
>> 478 #else
590 .set push 479 .set push
591 .set noat 480 .set noat
592 .set noreorder 481 .set noreorder
593 /* check if TLB contains a entry for E 482 /* check if TLB contains a entry for EPC */
594 MFC0 k1, CP0_ENTRYHI 483 MFC0 k1, CP0_ENTRYHI
595 andi k1, MIPS_ENTRYHI_ASID | MIPS_E !! 484 andi k1, 0xff /* ASID_MASK */
596 MFC0 k0, CP0_EPC 485 MFC0 k0, CP0_EPC
597 PTR_SRL k0, _PAGE_SHIFT + 1 !! 486 PTR_SRL k0, PAGE_SHIFT + 1
598 PTR_SLL k0, _PAGE_SHIFT + 1 !! 487 PTR_SLL k0, PAGE_SHIFT + 1
599 or k1, k0 488 or k1, k0
600 MTC0 k1, CP0_ENTRYHI 489 MTC0 k1, CP0_ENTRYHI
601 mtc0_tlbw_hazard 490 mtc0_tlbw_hazard
602 tlbp 491 tlbp
603 tlb_probe_hazard 492 tlb_probe_hazard
604 mfc0 k1, CP0_INDEX 493 mfc0 k1, CP0_INDEX
605 .set pop 494 .set pop
606 bltz k1, handle_ri /* slow path * 495 bltz k1, handle_ri /* slow path */
607 /* fall thru */ 496 /* fall thru */
608 END(handle_ri_rdhwr_tlbp) !! 497 #endif
>> 498 END(handle_ri_rdhwr_vivt)
609 499
610 LEAF(handle_ri_rdhwr) 500 LEAF(handle_ri_rdhwr)
611 .set push 501 .set push
612 .set noat 502 .set noat
613 .set noreorder 503 .set noreorder
614 /* MIPS32: 0x7c03e83b: rdhwr v1,$29 !! 504 /* 0x7c03e83b: rdhwr v1,$29 */
615 /* microMIPS: 0x007d6b3c: rdhwr v1,$29 <<
616 MFC0 k1, CP0_EPC 505 MFC0 k1, CP0_EPC
617 #if defined(CONFIG_CPU_MICROMIPS) || defined(C <<
618 and k0, k1, 1 <<
619 beqz k0, 1f <<
620 xor k1, k0 <<
621 lhu k0, (k1) <<
622 lhu k1, 2(k1) <<
623 ins k1, k0, 16, 16 <<
624 lui k0, 0x007d <<
625 b docheck <<
626 ori k0, 0x6b3c <<
627 1: <<
628 lui k0, 0x7c03 506 lui k0, 0x7c03
629 lw k1, (k1) 507 lw k1, (k1)
630 ori k0, 0xe83b 508 ori k0, 0xe83b
631 #else <<
632 andi k0, k1, 1 <<
633 bnez k0, handle_ri <<
634 lui k0, 0x7c03 <<
635 lw k1, (k1) <<
636 ori k0, 0xe83b <<
637 #endif <<
638 .set reorder 509 .set reorder
639 docheck: <<
640 bne k0, k1, handle_ri /* if 510 bne k0, k1, handle_ri /* if not ours */
641 <<
642 isrdhwr: <<
643 /* The insn is rdhwr. No need to chec 511 /* The insn is rdhwr. No need to check CAUSE.BD here. */
644 get_saved_sp /* k1 := current_threa 512 get_saved_sp /* k1 := current_thread_info */
645 .set noreorder 513 .set noreorder
646 MFC0 k0, CP0_EPC 514 MFC0 k0, CP0_EPC
647 #if defined(CONFIG_CPU_R3000) !! 515 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
648 ori k1, _THREAD_MASK 516 ori k1, _THREAD_MASK
649 xori k1, _THREAD_MASK 517 xori k1, _THREAD_MASK
650 LONG_L v1, TI_TP_VALUE(k1) 518 LONG_L v1, TI_TP_VALUE(k1)
651 LONG_ADDIU k0, 4 519 LONG_ADDIU k0, 4
652 jr k0 520 jr k0
653 rfe 521 rfe
654 #else 522 #else
655 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS 523 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
656 LONG_ADDIU k0, 4 /* sta 524 LONG_ADDIU k0, 4 /* stall on $k0 */
657 #else 525 #else
658 .set at=v1 526 .set at=v1
659 LONG_ADDIU k0, 4 527 LONG_ADDIU k0, 4
660 .set noat 528 .set noat
661 #endif 529 #endif
662 MTC0 k0, CP0_EPC 530 MTC0 k0, CP0_EPC
663 /* I hope three instructions between M 531 /* I hope three instructions between MTC0 and ERET are enough... */
664 ori k1, _THREAD_MASK 532 ori k1, _THREAD_MASK
665 xori k1, _THREAD_MASK 533 xori k1, _THREAD_MASK
666 LONG_L v1, TI_TP_VALUE(k1) 534 LONG_L v1, TI_TP_VALUE(k1)
667 .set push !! 535 .set mips3
668 .set arch=r4000 <<
669 eret 536 eret
670 .set pop !! 537 .set mips0
671 #endif 538 #endif
672 .set pop 539 .set pop
673 END(handle_ri_rdhwr) 540 END(handle_ri_rdhwr)
674 541
675 #ifdef CONFIG_CPU_R4X00_BUGS64 !! 542 #ifdef CONFIG_64BIT
676 /* A temporary overflow handler used by check_ 543 /* A temporary overflow handler used by check_daddi(). */
677 544
678 __INIT 545 __INIT
679 546
680 BUILD_HANDLER daddi_ov daddi_ov none 547 BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */
681 #endif 548 #endif
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