1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * GT641xx IRQ routines. 2 * GT641xx IRQ routines.
4 * 3 *
5 * Copyright (C) 2007 Yoichi Yuasa <yuasa@li 4 * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
>> 5 *
>> 6 * This program is free software; you can redistribute it and/or modify
>> 7 * it under the terms of the GNU General Public License as published by
>> 8 * the Free Software Foundation; either version 2 of the License, or
>> 9 * (at your option) any later version.
>> 10 *
>> 11 * This program is distributed in the hope that it will be useful,
>> 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 14 * GNU General Public License for more details.
>> 15 *
>> 16 * You should have received a copy of the GNU General Public License
>> 17 * along with this program; if not, write to the Free Software
>> 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
6 */ 19 */
7 #include <linux/hardirq.h> 20 #include <linux/hardirq.h>
8 #include <linux/init.h> 21 #include <linux/init.h>
9 #include <linux/irq.h> 22 #include <linux/irq.h>
10 #include <linux/spinlock.h> 23 #include <linux/spinlock.h>
11 #include <linux/types.h> 24 #include <linux/types.h>
12 25
13 #include <asm/gt64120.h> 26 #include <asm/gt64120.h>
14 27
15 #define GT641XX_IRQ_TO_BIT(irq) (1U << (irq - 28 #define GT641XX_IRQ_TO_BIT(irq) (1U << (irq - GT641XX_IRQ_BASE))
16 29
17 static DEFINE_RAW_SPINLOCK(gt641xx_irq_lock); 30 static DEFINE_RAW_SPINLOCK(gt641xx_irq_lock);
18 31
19 static void ack_gt641xx_irq(struct irq_data *d 32 static void ack_gt641xx_irq(struct irq_data *d)
20 { 33 {
21 unsigned long flags; 34 unsigned long flags;
22 u32 cause; 35 u32 cause;
23 36
24 raw_spin_lock_irqsave(>641xx_irq_loc 37 raw_spin_lock_irqsave(>641xx_irq_lock, flags);
25 cause = GT_READ(GT_INTRCAUSE_OFS); 38 cause = GT_READ(GT_INTRCAUSE_OFS);
26 cause &= ~GT641XX_IRQ_TO_BIT(d->irq); 39 cause &= ~GT641XX_IRQ_TO_BIT(d->irq);
27 GT_WRITE(GT_INTRCAUSE_OFS, cause); 40 GT_WRITE(GT_INTRCAUSE_OFS, cause);
28 raw_spin_unlock_irqrestore(>641xx_ir 41 raw_spin_unlock_irqrestore(>641xx_irq_lock, flags);
29 } 42 }
30 43
31 static void mask_gt641xx_irq(struct irq_data * 44 static void mask_gt641xx_irq(struct irq_data *d)
32 { 45 {
33 unsigned long flags; 46 unsigned long flags;
34 u32 mask; 47 u32 mask;
35 48
36 raw_spin_lock_irqsave(>641xx_irq_loc 49 raw_spin_lock_irqsave(>641xx_irq_lock, flags);
37 mask = GT_READ(GT_INTRMASK_OFS); 50 mask = GT_READ(GT_INTRMASK_OFS);
38 mask &= ~GT641XX_IRQ_TO_BIT(d->irq); 51 mask &= ~GT641XX_IRQ_TO_BIT(d->irq);
39 GT_WRITE(GT_INTRMASK_OFS, mask); 52 GT_WRITE(GT_INTRMASK_OFS, mask);
40 raw_spin_unlock_irqrestore(>641xx_ir 53 raw_spin_unlock_irqrestore(>641xx_irq_lock, flags);
41 } 54 }
42 55
43 static void mask_ack_gt641xx_irq(struct irq_da 56 static void mask_ack_gt641xx_irq(struct irq_data *d)
44 { 57 {
45 unsigned long flags; 58 unsigned long flags;
46 u32 cause, mask; 59 u32 cause, mask;
47 60
48 raw_spin_lock_irqsave(>641xx_irq_loc 61 raw_spin_lock_irqsave(>641xx_irq_lock, flags);
49 mask = GT_READ(GT_INTRMASK_OFS); 62 mask = GT_READ(GT_INTRMASK_OFS);
50 mask &= ~GT641XX_IRQ_TO_BIT(d->irq); 63 mask &= ~GT641XX_IRQ_TO_BIT(d->irq);
51 GT_WRITE(GT_INTRMASK_OFS, mask); 64 GT_WRITE(GT_INTRMASK_OFS, mask);
52 65
53 cause = GT_READ(GT_INTRCAUSE_OFS); 66 cause = GT_READ(GT_INTRCAUSE_OFS);
54 cause &= ~GT641XX_IRQ_TO_BIT(d->irq); 67 cause &= ~GT641XX_IRQ_TO_BIT(d->irq);
55 GT_WRITE(GT_INTRCAUSE_OFS, cause); 68 GT_WRITE(GT_INTRCAUSE_OFS, cause);
56 raw_spin_unlock_irqrestore(>641xx_ir 69 raw_spin_unlock_irqrestore(>641xx_irq_lock, flags);
57 } 70 }
58 71
59 static void unmask_gt641xx_irq(struct irq_data 72 static void unmask_gt641xx_irq(struct irq_data *d)
60 { 73 {
61 unsigned long flags; 74 unsigned long flags;
62 u32 mask; 75 u32 mask;
63 76
64 raw_spin_lock_irqsave(>641xx_irq_loc 77 raw_spin_lock_irqsave(>641xx_irq_lock, flags);
65 mask = GT_READ(GT_INTRMASK_OFS); 78 mask = GT_READ(GT_INTRMASK_OFS);
66 mask |= GT641XX_IRQ_TO_BIT(d->irq); 79 mask |= GT641XX_IRQ_TO_BIT(d->irq);
67 GT_WRITE(GT_INTRMASK_OFS, mask); 80 GT_WRITE(GT_INTRMASK_OFS, mask);
68 raw_spin_unlock_irqrestore(>641xx_ir 81 raw_spin_unlock_irqrestore(>641xx_irq_lock, flags);
69 } 82 }
70 83
71 static struct irq_chip gt641xx_irq_chip = { 84 static struct irq_chip gt641xx_irq_chip = {
72 .name = "GT641xx", 85 .name = "GT641xx",
73 .irq_ack = ack_gt641xx_irq, 86 .irq_ack = ack_gt641xx_irq,
74 .irq_mask = mask_gt641xx_irq, 87 .irq_mask = mask_gt641xx_irq,
75 .irq_mask_ack = mask_ack_gt641xx_irq 88 .irq_mask_ack = mask_ack_gt641xx_irq,
76 .irq_unmask = unmask_gt641xx_irq, 89 .irq_unmask = unmask_gt641xx_irq,
77 }; 90 };
78 91
79 void gt641xx_irq_dispatch(void) 92 void gt641xx_irq_dispatch(void)
80 { 93 {
81 u32 cause, mask; 94 u32 cause, mask;
82 int i; 95 int i;
83 96
84 cause = GT_READ(GT_INTRCAUSE_OFS); 97 cause = GT_READ(GT_INTRCAUSE_OFS);
85 mask = GT_READ(GT_INTRMASK_OFS); 98 mask = GT_READ(GT_INTRMASK_OFS);
86 cause &= mask; 99 cause &= mask;
87 100
88 /* 101 /*
89 * bit0 : logical or of all the interr 102 * bit0 : logical or of all the interrupt bits.
90 * bit30: logical or of bits[29:26,20: 103 * bit30: logical or of bits[29:26,20:1].
91 * bit31: logical or of bits[25:1]. 104 * bit31: logical or of bits[25:1].
92 */ 105 */
93 for (i = 1; i < 30; i++) { 106 for (i = 1; i < 30; i++) {
94 if (cause & (1U << i)) { 107 if (cause & (1U << i)) {
95 do_IRQ(GT641XX_IRQ_BAS 108 do_IRQ(GT641XX_IRQ_BASE + i);
96 return; 109 return;
97 } 110 }
98 } 111 }
99 112
100 atomic_inc(&irq_err_count); 113 atomic_inc(&irq_err_count);
101 } 114 }
102 115
103 void __init gt641xx_irq_init(void) 116 void __init gt641xx_irq_init(void)
104 { 117 {
105 int i; 118 int i;
106 119
107 GT_WRITE(GT_INTRMASK_OFS, 0); 120 GT_WRITE(GT_INTRMASK_OFS, 0);
108 GT_WRITE(GT_INTRCAUSE_OFS, 0); 121 GT_WRITE(GT_INTRCAUSE_OFS, 0);
109 122
110 /* 123 /*
111 * bit0 : logical or of all the interr 124 * bit0 : logical or of all the interrupt bits.
112 * bit30: logical or of bits[29:26,20: 125 * bit30: logical or of bits[29:26,20:1].
113 * bit31: logical or of bits[25:1]. 126 * bit31: logical or of bits[25:1].
114 */ 127 */
115 for (i = 1; i < 30; i++) 128 for (i = 1; i < 30; i++)
116 irq_set_chip_and_handler(GT641 129 irq_set_chip_and_handler(GT641XX_IRQ_BASE + i,
117 >64 130 >641xx_irq_chip, handle_level_irq);
118 } 131 }
119 132
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