1 // SPDX-License-Identifier: GPL-2.0 <<
2 /* 1 /*
3 * General MIPS MT support routines, usable in !! 2 * General MIPS MT support routines, usable in AP/SP, SMVP, or SMTC kernels
4 * Copyright (C) 2005 Mips Technologies, Inc 3 * Copyright (C) 2005 Mips Technologies, Inc
5 */ 4 */
6 5
7 #include <linux/device.h> 6 #include <linux/device.h>
8 #include <linux/kernel.h> 7 #include <linux/kernel.h>
9 #include <linux/sched.h> 8 #include <linux/sched.h>
10 #include <linux/export.h> !! 9 #include <linux/module.h>
11 #include <linux/interrupt.h> 10 #include <linux/interrupt.h>
12 #include <linux/security.h> 11 #include <linux/security.h>
13 12
14 #include <asm/cpu.h> 13 #include <asm/cpu.h>
15 #include <asm/processor.h> 14 #include <asm/processor.h>
16 #include <linux/atomic.h> !! 15 #include <asm/atomic.h>
>> 16 #include <asm/system.h>
17 #include <asm/hardirq.h> 17 #include <asm/hardirq.h>
18 #include <asm/mmu_context.h> 18 #include <asm/mmu_context.h>
19 #include <asm/mipsmtregs.h> 19 #include <asm/mipsmtregs.h>
20 #include <asm/r4kcache.h> 20 #include <asm/r4kcache.h>
21 #include <asm/cacheflush.h> 21 #include <asm/cacheflush.h>
22 #include <asm/mips_mt.h> <<
23 22
24 int vpelimit; 23 int vpelimit;
25 24
26 static int __init maxvpes(char *str) 25 static int __init maxvpes(char *str)
27 { 26 {
28 get_option(&str, &vpelimit); 27 get_option(&str, &vpelimit);
29 28
30 return 1; 29 return 1;
31 } 30 }
32 31
33 __setup("maxvpes=", maxvpes); 32 __setup("maxvpes=", maxvpes);
34 33
35 int tclimit; 34 int tclimit;
36 35
37 static int __init maxtcs(char *str) 36 static int __init maxtcs(char *str)
38 { 37 {
39 get_option(&str, &tclimit); 38 get_option(&str, &tclimit);
40 39
41 return 1; 40 return 1;
42 } 41 }
43 42
44 __setup("maxtcs=", maxtcs); 43 __setup("maxtcs=", maxtcs);
45 44
46 /* 45 /*
47 * Dump new MIPS MT state for the core. Does n 46 * Dump new MIPS MT state for the core. Does not leave TCs halted.
48 * Takes an argument which taken to be a pre-c 47 * Takes an argument which taken to be a pre-call MVPControl value.
49 */ 48 */
50 49
51 void mips_mt_regdump(unsigned long mvpctl) 50 void mips_mt_regdump(unsigned long mvpctl)
52 { 51 {
53 unsigned long flags; 52 unsigned long flags;
54 unsigned long vpflags; 53 unsigned long vpflags;
55 unsigned long mvpconf0; 54 unsigned long mvpconf0;
56 int nvpe; 55 int nvpe;
57 int ntc; 56 int ntc;
58 int i; 57 int i;
59 int tc; 58 int tc;
60 unsigned long haltval; 59 unsigned long haltval;
61 unsigned long tcstatval; 60 unsigned long tcstatval;
>> 61 #ifdef CONFIG_MIPS_MT_SMTC
>> 62 void smtc_soft_dump(void);
>> 63 #endif /* CONFIG_MIPT_MT_SMTC */
62 64
63 local_irq_save(flags); 65 local_irq_save(flags);
64 vpflags = dvpe(); 66 vpflags = dvpe();
65 printk("=== MIPS MT State Dump ===\n") 67 printk("=== MIPS MT State Dump ===\n");
66 printk("-- Global State --\n"); 68 printk("-- Global State --\n");
67 printk(" MVPControl Passed: %08lx\n" 69 printk(" MVPControl Passed: %08lx\n", mvpctl);
68 printk(" MVPControl Read: %08lx\n", 70 printk(" MVPControl Read: %08lx\n", vpflags);
69 printk(" MVPConf0 : %08lx\n", (mvpco 71 printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
70 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> 72 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
71 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MV 73 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
72 printk("-- per-VPE State --\n"); 74 printk("-- per-VPE State --\n");
73 for (i = 0; i < nvpe; i++) { 75 for (i = 0; i < nvpe; i++) {
74 for (tc = 0; tc < ntc; tc++) { 76 for (tc = 0; tc < ntc; tc++) {
75 settc(tc); 77 settc(tc);
76 if ((read_tc_c0_tcbind 78 if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
77 printk(" VPE 79 printk(" VPE %d\n", i);
78 printk(" VPE 80 printk(" VPEControl : %08lx\n",
79 read_vp 81 read_vpe_c0_vpecontrol());
80 printk(" VPE 82 printk(" VPEConf0 : %08lx\n",
81 read_vp 83 read_vpe_c0_vpeconf0());
82 printk(" VPE 84 printk(" VPE%d.Status : %08lx\n",
83 i, read 85 i, read_vpe_c0_status());
84 printk(" VPE 86 printk(" VPE%d.EPC : %08lx %pS\n",
85 i, read 87 i, read_vpe_c0_epc(),
86 (void * 88 (void *) read_vpe_c0_epc());
87 printk(" VPE 89 printk(" VPE%d.Cause : %08lx\n",
88 i, read 90 i, read_vpe_c0_cause());
89 printk(" VPE 91 printk(" VPE%d.Config7 : %08lx\n",
90 i, read 92 i, read_vpe_c0_config7());
91 break; /* Next 93 break; /* Next VPE */
92 } 94 }
93 } 95 }
94 } 96 }
95 printk("-- per-TC State --\n"); 97 printk("-- per-TC State --\n");
96 for (tc = 0; tc < ntc; tc++) { 98 for (tc = 0; tc < ntc; tc++) {
97 settc(tc); 99 settc(tc);
98 if (read_tc_c0_tcbind() == rea 100 if (read_tc_c0_tcbind() == read_c0_tcbind()) {
99 /* Are we dumping ours 101 /* Are we dumping ourself? */
100 haltval = 0; /* Then w 102 haltval = 0; /* Then we're not halted, and mustn't be */
101 tcstatval = flags; /* 103 tcstatval = flags; /* And pre-dump TCStatus is flags */
102 printk(" TC %d (curre 104 printk(" TC %d (current TC with VPE EPC above)\n", tc);
103 } else { 105 } else {
104 haltval = read_tc_c0_t 106 haltval = read_tc_c0_tchalt();
105 write_tc_c0_tchalt(1); 107 write_tc_c0_tchalt(1);
106 tcstatval = read_tc_c0 108 tcstatval = read_tc_c0_tcstatus();
107 printk(" TC %d\n", tc 109 printk(" TC %d\n", tc);
108 } 110 }
109 printk(" TCStatus : %08lx\n" 111 printk(" TCStatus : %08lx\n", tcstatval);
110 printk(" TCBind : %08lx\n", 112 printk(" TCBind : %08lx\n", read_tc_c0_tcbind());
111 printk(" TCRestart : %08lx % 113 printk(" TCRestart : %08lx %pS\n",
112 read_tc_c0_tcrestart(), 114 read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart());
113 printk(" TCHalt : %08lx\n", 115 printk(" TCHalt : %08lx\n", haltval);
114 printk(" TCContext : %08lx\n 116 printk(" TCContext : %08lx\n", read_tc_c0_tccontext());
115 if (!haltval) 117 if (!haltval)
116 write_tc_c0_tchalt(0); 118 write_tc_c0_tchalt(0);
117 } 119 }
>> 120 #ifdef CONFIG_MIPS_MT_SMTC
>> 121 smtc_soft_dump();
>> 122 #endif /* CONFIG_MIPT_MT_SMTC */
118 printk("===========================\n" 123 printk("===========================\n");
119 evpe(vpflags); 124 evpe(vpflags);
120 local_irq_restore(flags); 125 local_irq_restore(flags);
121 } 126 }
122 127
>> 128 static int mt_opt_norps;
123 static int mt_opt_rpsctl = -1; 129 static int mt_opt_rpsctl = -1;
124 static int mt_opt_nblsu = -1; 130 static int mt_opt_nblsu = -1;
125 static int mt_opt_forceconfig7; 131 static int mt_opt_forceconfig7;
126 static int mt_opt_config7 = -1; 132 static int mt_opt_config7 = -1;
127 133
>> 134 static int __init rps_disable(char *s)
>> 135 {
>> 136 mt_opt_norps = 1;
>> 137 return 1;
>> 138 }
>> 139 __setup("norps", rps_disable);
>> 140
128 static int __init rpsctl_set(char *str) 141 static int __init rpsctl_set(char *str)
129 { 142 {
130 get_option(&str, &mt_opt_rpsctl); 143 get_option(&str, &mt_opt_rpsctl);
131 return 1; 144 return 1;
132 } 145 }
133 __setup("rpsctl=", rpsctl_set); 146 __setup("rpsctl=", rpsctl_set);
134 147
135 static int __init nblsu_set(char *str) 148 static int __init nblsu_set(char *str)
136 { 149 {
137 get_option(&str, &mt_opt_nblsu); 150 get_option(&str, &mt_opt_nblsu);
138 return 1; 151 return 1;
139 } 152 }
140 __setup("nblsu=", nblsu_set); 153 __setup("nblsu=", nblsu_set);
141 154
142 static int __init config7_set(char *str) 155 static int __init config7_set(char *str)
143 { 156 {
144 get_option(&str, &mt_opt_config7); 157 get_option(&str, &mt_opt_config7);
145 mt_opt_forceconfig7 = 1; 158 mt_opt_forceconfig7 = 1;
146 return 1; 159 return 1;
147 } 160 }
148 __setup("config7=", config7_set); 161 __setup("config7=", config7_set);
149 162
>> 163 /* Experimental cache flush control parameters that should go away some day */
>> 164 int mt_protiflush;
>> 165 int mt_protdflush;
>> 166 int mt_n_iflushes = 1;
>> 167 int mt_n_dflushes = 1;
>> 168
>> 169 static int __init set_protiflush(char *s)
>> 170 {
>> 171 mt_protiflush = 1;
>> 172 return 1;
>> 173 }
>> 174 __setup("protiflush", set_protiflush);
>> 175
>> 176 static int __init set_protdflush(char *s)
>> 177 {
>> 178 mt_protdflush = 1;
>> 179 return 1;
>> 180 }
>> 181 __setup("protdflush", set_protdflush);
>> 182
>> 183 static int __init niflush(char *s)
>> 184 {
>> 185 get_option(&s, &mt_n_iflushes);
>> 186 return 1;
>> 187 }
>> 188 __setup("niflush=", niflush);
>> 189
>> 190 static int __init ndflush(char *s)
>> 191 {
>> 192 get_option(&s, &mt_n_dflushes);
>> 193 return 1;
>> 194 }
>> 195 __setup("ndflush=", ndflush);
>> 196
150 static unsigned int itc_base; 197 static unsigned int itc_base;
151 198
152 static int __init set_itc_base(char *str) 199 static int __init set_itc_base(char *str)
153 { 200 {
154 get_option(&str, &itc_base); 201 get_option(&str, &itc_base);
155 return 1; 202 return 1;
156 } 203 }
157 204
158 __setup("itcbase=", set_itc_base); 205 __setup("itcbase=", set_itc_base);
159 206
160 void mips_mt_set_cpuoptions(void) 207 void mips_mt_set_cpuoptions(void)
161 { 208 {
162 unsigned int oconfig7 = read_c0_config 209 unsigned int oconfig7 = read_c0_config7();
163 unsigned int nconfig7 = oconfig7; 210 unsigned int nconfig7 = oconfig7;
164 211
>> 212 if (mt_opt_norps) {
>> 213 printk("\"norps\" option deprectated: use \"rpsctl=\"\n");
>> 214 }
165 if (mt_opt_rpsctl >= 0) { 215 if (mt_opt_rpsctl >= 0) {
166 printk("34K return prediction 216 printk("34K return prediction stack override set to %d.\n",
167 mt_opt_rpsctl); 217 mt_opt_rpsctl);
168 if (mt_opt_rpsctl) 218 if (mt_opt_rpsctl)
169 nconfig7 |= (1 << 2); 219 nconfig7 |= (1 << 2);
170 else 220 else
171 nconfig7 &= ~(1 << 2); 221 nconfig7 &= ~(1 << 2);
172 } 222 }
173 if (mt_opt_nblsu >= 0) { 223 if (mt_opt_nblsu >= 0) {
174 printk("34K ALU/LSU sync overr 224 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
175 if (mt_opt_nblsu) 225 if (mt_opt_nblsu)
176 nconfig7 |= (1 << 5); 226 nconfig7 |= (1 << 5);
177 else 227 else
178 nconfig7 &= ~(1 << 5); 228 nconfig7 &= ~(1 << 5);
179 } 229 }
180 if (mt_opt_forceconfig7) { 230 if (mt_opt_forceconfig7) {
181 printk("CP0.Config7 forced to 231 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
182 nconfig7 = mt_opt_config7; 232 nconfig7 = mt_opt_config7;
183 } 233 }
184 if (oconfig7 != nconfig7) { 234 if (oconfig7 != nconfig7) {
185 __asm__ __volatile("sync"); 235 __asm__ __volatile("sync");
186 write_c0_config7(nconfig7); 236 write_c0_config7(nconfig7);
187 ehb(); 237 ehb();
188 printk("Config7: 0x%08x\n", re 238 printk("Config7: 0x%08x\n", read_c0_config7());
189 } 239 }
190 240
>> 241 /* Report Cache management debug options */
>> 242 if (mt_protiflush)
>> 243 printk("I-cache flushes single-threaded\n");
>> 244 if (mt_protdflush)
>> 245 printk("D-cache flushes single-threaded\n");
>> 246 if (mt_n_iflushes != 1)
>> 247 printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes);
>> 248 if (mt_n_dflushes != 1)
>> 249 printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes);
>> 250
191 if (itc_base != 0) { 251 if (itc_base != 0) {
192 /* 252 /*
193 * Configure ITC mapping. Thi 253 * Configure ITC mapping. This code is very
194 * specific to the 34K core fa 254 * specific to the 34K core family, which uses
195 * a special mode bit ("ITC") 255 * a special mode bit ("ITC") in the ErrCtl
196 * register to enable access t 256 * register to enable access to ITC control
197 * registers via cache "tag" o 257 * registers via cache "tag" operations.
198 */ 258 */
199 unsigned long ectlval; 259 unsigned long ectlval;
200 unsigned long itcblkgrn; 260 unsigned long itcblkgrn;
201 261
202 /* ErrCtl register is known as 262 /* ErrCtl register is known as "ecc" to Linux */
203 ectlval = read_c0_ecc(); 263 ectlval = read_c0_ecc();
204 write_c0_ecc(ectlval | (0x1 << 264 write_c0_ecc(ectlval | (0x1 << 26));
205 ehb(); 265 ehb();
206 #define INDEX_0 (0x80000000) 266 #define INDEX_0 (0x80000000)
207 #define INDEX_8 (0x80000008) 267 #define INDEX_8 (0x80000008)
208 /* Read "cache tag" for Dcache 268 /* Read "cache tag" for Dcache pseudo-index 8 */
209 cache_op(Index_Load_Tag_D, IND 269 cache_op(Index_Load_Tag_D, INDEX_8);
210 ehb(); 270 ehb();
211 itcblkgrn = read_c0_dtaglo(); 271 itcblkgrn = read_c0_dtaglo();
212 itcblkgrn &= 0xfffe0000; 272 itcblkgrn &= 0xfffe0000;
213 /* Set for 128 byte pitch of I 273 /* Set for 128 byte pitch of ITC cells */
214 itcblkgrn |= 0x00000c00; 274 itcblkgrn |= 0x00000c00;
215 /* Stage in Tag register */ 275 /* Stage in Tag register */
216 write_c0_dtaglo(itcblkgrn); 276 write_c0_dtaglo(itcblkgrn);
217 ehb(); 277 ehb();
218 /* Write out to ITU with CACHE 278 /* Write out to ITU with CACHE op */
219 cache_op(Index_Store_Tag_D, IN 279 cache_op(Index_Store_Tag_D, INDEX_8);
220 /* Now set base address, and t 280 /* Now set base address, and turn ITC on with 0x1 bit */
221 write_c0_dtaglo((itc_base & 0x 281 write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
222 ehb(); 282 ehb();
223 /* Write out to ITU with CACHE 283 /* Write out to ITU with CACHE op */
224 cache_op(Index_Store_Tag_D, IN 284 cache_op(Index_Store_Tag_D, INDEX_0);
225 write_c0_ecc(ectlval); 285 write_c0_ecc(ectlval);
226 ehb(); 286 ehb();
227 printk("Mapped %ld ITC cells s 287 printk("Mapped %ld ITC cells starting at 0x%08x\n",
228 ((itcblkgrn & 0x7fe000 288 ((itcblkgrn & 0x7fe00000) >> 20), itc_base);
229 } 289 }
230 } 290 }
231 291
232 const struct class mt_class = { !! 292 /*
233 .name = "mt", !! 293 * Function to protect cache flushes from concurrent execution
234 }; !! 294 * depends on MP software model chosen.
>> 295 */
>> 296
>> 297 void mt_cflush_lockdown(void)
>> 298 {
>> 299 #ifdef CONFIG_MIPS_MT_SMTC
>> 300 void smtc_cflush_lockdown(void);
>> 301
>> 302 smtc_cflush_lockdown();
>> 303 #endif /* CONFIG_MIPS_MT_SMTC */
>> 304 /* FILL IN VSMP and AP/SP VERSIONS HERE */
>> 305 }
>> 306
>> 307 void mt_cflush_release(void)
>> 308 {
>> 309 #ifdef CONFIG_MIPS_MT_SMTC
>> 310 void smtc_cflush_release(void);
>> 311
>> 312 smtc_cflush_release();
>> 313 #endif /* CONFIG_MIPS_MT_SMTC */
>> 314 /* FILL IN VSMP and AP/SP VERSIONS HERE */
>> 315 }
235 316
236 static int __init mips_mt_init(void) !! 317 struct class *mt_class;
>> 318
>> 319 static int __init mt_init(void)
237 { 320 {
238 return class_register(&mt_class); !! 321 struct class *mtc;
>> 322
>> 323 mtc = class_create(THIS_MODULE, "mt");
>> 324 if (IS_ERR(mtc))
>> 325 return PTR_ERR(mtc);
>> 326
>> 327 mt_class = mtc;
>> 328
>> 329 return 0;
239 } 330 }
240 331
241 subsys_initcall(mips_mt_init); !! 332 subsys_initcall(mt_init);
242 333
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