1 // SPDX-License-Identifier: GPL-2.0 << 2 /* 1 /* 3 * General MIPS MT support routines, usable in 2 * General MIPS MT support routines, usable in AP/SP and SMVP. 4 * Copyright (C) 2005 Mips Technologies, Inc 3 * Copyright (C) 2005 Mips Technologies, Inc 5 */ 4 */ 6 5 7 #include <linux/device.h> 6 #include <linux/device.h> 8 #include <linux/kernel.h> 7 #include <linux/kernel.h> 9 #include <linux/sched.h> 8 #include <linux/sched.h> 10 #include <linux/export.h> 9 #include <linux/export.h> 11 #include <linux/interrupt.h> 10 #include <linux/interrupt.h> 12 #include <linux/security.h> 11 #include <linux/security.h> 13 12 14 #include <asm/cpu.h> 13 #include <asm/cpu.h> 15 #include <asm/processor.h> 14 #include <asm/processor.h> 16 #include <linux/atomic.h> 15 #include <linux/atomic.h> 17 #include <asm/hardirq.h> 16 #include <asm/hardirq.h> 18 #include <asm/mmu_context.h> 17 #include <asm/mmu_context.h> 19 #include <asm/mipsmtregs.h> 18 #include <asm/mipsmtregs.h> 20 #include <asm/r4kcache.h> 19 #include <asm/r4kcache.h> 21 #include <asm/cacheflush.h> 20 #include <asm/cacheflush.h> 22 #include <asm/mips_mt.h> << 23 21 24 int vpelimit; 22 int vpelimit; 25 23 26 static int __init maxvpes(char *str) 24 static int __init maxvpes(char *str) 27 { 25 { 28 get_option(&str, &vpelimit); 26 get_option(&str, &vpelimit); 29 27 30 return 1; 28 return 1; 31 } 29 } 32 30 33 __setup("maxvpes=", maxvpes); 31 __setup("maxvpes=", maxvpes); 34 32 35 int tclimit; 33 int tclimit; 36 34 37 static int __init maxtcs(char *str) 35 static int __init maxtcs(char *str) 38 { 36 { 39 get_option(&str, &tclimit); 37 get_option(&str, &tclimit); 40 38 41 return 1; 39 return 1; 42 } 40 } 43 41 44 __setup("maxtcs=", maxtcs); 42 __setup("maxtcs=", maxtcs); 45 43 46 /* 44 /* 47 * Dump new MIPS MT state for the core. Does n 45 * Dump new MIPS MT state for the core. Does not leave TCs halted. 48 * Takes an argument which taken to be a pre-c 46 * Takes an argument which taken to be a pre-call MVPControl value. 49 */ 47 */ 50 48 51 void mips_mt_regdump(unsigned long mvpctl) 49 void mips_mt_regdump(unsigned long mvpctl) 52 { 50 { 53 unsigned long flags; 51 unsigned long flags; 54 unsigned long vpflags; 52 unsigned long vpflags; 55 unsigned long mvpconf0; 53 unsigned long mvpconf0; 56 int nvpe; 54 int nvpe; 57 int ntc; 55 int ntc; 58 int i; 56 int i; 59 int tc; 57 int tc; 60 unsigned long haltval; 58 unsigned long haltval; 61 unsigned long tcstatval; 59 unsigned long tcstatval; 62 60 63 local_irq_save(flags); 61 local_irq_save(flags); 64 vpflags = dvpe(); 62 vpflags = dvpe(); 65 printk("=== MIPS MT State Dump ===\n") 63 printk("=== MIPS MT State Dump ===\n"); 66 printk("-- Global State --\n"); 64 printk("-- Global State --\n"); 67 printk(" MVPControl Passed: %08lx\n" 65 printk(" MVPControl Passed: %08lx\n", mvpctl); 68 printk(" MVPControl Read: %08lx\n", 66 printk(" MVPControl Read: %08lx\n", vpflags); 69 printk(" MVPConf0 : %08lx\n", (mvpco 67 printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0())); 70 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> 68 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; 71 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MV 69 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; 72 printk("-- per-VPE State --\n"); 70 printk("-- per-VPE State --\n"); 73 for (i = 0; i < nvpe; i++) { 71 for (i = 0; i < nvpe; i++) { 74 for (tc = 0; tc < ntc; tc++) { 72 for (tc = 0; tc < ntc; tc++) { 75 settc(tc); 73 settc(tc); 76 if ((read_tc_c0_tcbind 74 if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) { 77 printk(" VPE 75 printk(" VPE %d\n", i); 78 printk(" VPE 76 printk(" VPEControl : %08lx\n", 79 read_vp 77 read_vpe_c0_vpecontrol()); 80 printk(" VPE 78 printk(" VPEConf0 : %08lx\n", 81 read_vp 79 read_vpe_c0_vpeconf0()); 82 printk(" VPE 80 printk(" VPE%d.Status : %08lx\n", 83 i, read 81 i, read_vpe_c0_status()); 84 printk(" VPE 82 printk(" VPE%d.EPC : %08lx %pS\n", 85 i, read 83 i, read_vpe_c0_epc(), 86 (void * 84 (void *) read_vpe_c0_epc()); 87 printk(" VPE 85 printk(" VPE%d.Cause : %08lx\n", 88 i, read 86 i, read_vpe_c0_cause()); 89 printk(" VPE 87 printk(" VPE%d.Config7 : %08lx\n", 90 i, read 88 i, read_vpe_c0_config7()); 91 break; /* Next 89 break; /* Next VPE */ 92 } 90 } 93 } 91 } 94 } 92 } 95 printk("-- per-TC State --\n"); 93 printk("-- per-TC State --\n"); 96 for (tc = 0; tc < ntc; tc++) { 94 for (tc = 0; tc < ntc; tc++) { 97 settc(tc); 95 settc(tc); 98 if (read_tc_c0_tcbind() == rea 96 if (read_tc_c0_tcbind() == read_c0_tcbind()) { 99 /* Are we dumping ours 97 /* Are we dumping ourself? */ 100 haltval = 0; /* Then w 98 haltval = 0; /* Then we're not halted, and mustn't be */ 101 tcstatval = flags; /* 99 tcstatval = flags; /* And pre-dump TCStatus is flags */ 102 printk(" TC %d (curre 100 printk(" TC %d (current TC with VPE EPC above)\n", tc); 103 } else { 101 } else { 104 haltval = read_tc_c0_t 102 haltval = read_tc_c0_tchalt(); 105 write_tc_c0_tchalt(1); 103 write_tc_c0_tchalt(1); 106 tcstatval = read_tc_c0 104 tcstatval = read_tc_c0_tcstatus(); 107 printk(" TC %d\n", tc 105 printk(" TC %d\n", tc); 108 } 106 } 109 printk(" TCStatus : %08lx\n" 107 printk(" TCStatus : %08lx\n", tcstatval); 110 printk(" TCBind : %08lx\n", 108 printk(" TCBind : %08lx\n", read_tc_c0_tcbind()); 111 printk(" TCRestart : %08lx % 109 printk(" TCRestart : %08lx %pS\n", 112 read_tc_c0_tcrestart(), 110 read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart()); 113 printk(" TCHalt : %08lx\n", 111 printk(" TCHalt : %08lx\n", haltval); 114 printk(" TCContext : %08lx\n 112 printk(" TCContext : %08lx\n", read_tc_c0_tccontext()); 115 if (!haltval) 113 if (!haltval) 116 write_tc_c0_tchalt(0); 114 write_tc_c0_tchalt(0); 117 } 115 } 118 printk("===========================\n" 116 printk("===========================\n"); 119 evpe(vpflags); 117 evpe(vpflags); 120 local_irq_restore(flags); 118 local_irq_restore(flags); 121 } 119 } 122 120 >> 121 static int mt_opt_norps; 123 static int mt_opt_rpsctl = -1; 122 static int mt_opt_rpsctl = -1; 124 static int mt_opt_nblsu = -1; 123 static int mt_opt_nblsu = -1; 125 static int mt_opt_forceconfig7; 124 static int mt_opt_forceconfig7; 126 static int mt_opt_config7 = -1; 125 static int mt_opt_config7 = -1; 127 126 >> 127 static int __init rps_disable(char *s) >> 128 { >> 129 mt_opt_norps = 1; >> 130 return 1; >> 131 } >> 132 __setup("norps", rps_disable); >> 133 128 static int __init rpsctl_set(char *str) 134 static int __init rpsctl_set(char *str) 129 { 135 { 130 get_option(&str, &mt_opt_rpsctl); 136 get_option(&str, &mt_opt_rpsctl); 131 return 1; 137 return 1; 132 } 138 } 133 __setup("rpsctl=", rpsctl_set); 139 __setup("rpsctl=", rpsctl_set); 134 140 135 static int __init nblsu_set(char *str) 141 static int __init nblsu_set(char *str) 136 { 142 { 137 get_option(&str, &mt_opt_nblsu); 143 get_option(&str, &mt_opt_nblsu); 138 return 1; 144 return 1; 139 } 145 } 140 __setup("nblsu=", nblsu_set); 146 __setup("nblsu=", nblsu_set); 141 147 142 static int __init config7_set(char *str) 148 static int __init config7_set(char *str) 143 { 149 { 144 get_option(&str, &mt_opt_config7); 150 get_option(&str, &mt_opt_config7); 145 mt_opt_forceconfig7 = 1; 151 mt_opt_forceconfig7 = 1; 146 return 1; 152 return 1; 147 } 153 } 148 __setup("config7=", config7_set); 154 __setup("config7=", config7_set); 149 155 >> 156 /* Experimental cache flush control parameters that should go away some day */ >> 157 int mt_protiflush; >> 158 int mt_protdflush; >> 159 int mt_n_iflushes = 1; >> 160 int mt_n_dflushes = 1; >> 161 >> 162 static int __init set_protiflush(char *s) >> 163 { >> 164 mt_protiflush = 1; >> 165 return 1; >> 166 } >> 167 __setup("protiflush", set_protiflush); >> 168 >> 169 static int __init set_protdflush(char *s) >> 170 { >> 171 mt_protdflush = 1; >> 172 return 1; >> 173 } >> 174 __setup("protdflush", set_protdflush); >> 175 >> 176 static int __init niflush(char *s) >> 177 { >> 178 get_option(&s, &mt_n_iflushes); >> 179 return 1; >> 180 } >> 181 __setup("niflush=", niflush); >> 182 >> 183 static int __init ndflush(char *s) >> 184 { >> 185 get_option(&s, &mt_n_dflushes); >> 186 return 1; >> 187 } >> 188 __setup("ndflush=", ndflush); >> 189 150 static unsigned int itc_base; 190 static unsigned int itc_base; 151 191 152 static int __init set_itc_base(char *str) 192 static int __init set_itc_base(char *str) 153 { 193 { 154 get_option(&str, &itc_base); 194 get_option(&str, &itc_base); 155 return 1; 195 return 1; 156 } 196 } 157 197 158 __setup("itcbase=", set_itc_base); 198 __setup("itcbase=", set_itc_base); 159 199 160 void mips_mt_set_cpuoptions(void) 200 void mips_mt_set_cpuoptions(void) 161 { 201 { 162 unsigned int oconfig7 = read_c0_config 202 unsigned int oconfig7 = read_c0_config7(); 163 unsigned int nconfig7 = oconfig7; 203 unsigned int nconfig7 = oconfig7; 164 204 >> 205 if (mt_opt_norps) { >> 206 printk("\"norps\" option deprecated: use \"rpsctl=\"\n"); >> 207 } 165 if (mt_opt_rpsctl >= 0) { 208 if (mt_opt_rpsctl >= 0) { 166 printk("34K return prediction 209 printk("34K return prediction stack override set to %d.\n", 167 mt_opt_rpsctl); 210 mt_opt_rpsctl); 168 if (mt_opt_rpsctl) 211 if (mt_opt_rpsctl) 169 nconfig7 |= (1 << 2); 212 nconfig7 |= (1 << 2); 170 else 213 else 171 nconfig7 &= ~(1 << 2); 214 nconfig7 &= ~(1 << 2); 172 } 215 } 173 if (mt_opt_nblsu >= 0) { 216 if (mt_opt_nblsu >= 0) { 174 printk("34K ALU/LSU sync overr 217 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu); 175 if (mt_opt_nblsu) 218 if (mt_opt_nblsu) 176 nconfig7 |= (1 << 5); 219 nconfig7 |= (1 << 5); 177 else 220 else 178 nconfig7 &= ~(1 << 5); 221 nconfig7 &= ~(1 << 5); 179 } 222 } 180 if (mt_opt_forceconfig7) { 223 if (mt_opt_forceconfig7) { 181 printk("CP0.Config7 forced to 224 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7); 182 nconfig7 = mt_opt_config7; 225 nconfig7 = mt_opt_config7; 183 } 226 } 184 if (oconfig7 != nconfig7) { 227 if (oconfig7 != nconfig7) { 185 __asm__ __volatile("sync"); 228 __asm__ __volatile("sync"); 186 write_c0_config7(nconfig7); 229 write_c0_config7(nconfig7); 187 ehb(); 230 ehb(); 188 printk("Config7: 0x%08x\n", re 231 printk("Config7: 0x%08x\n", read_c0_config7()); 189 } 232 } 190 233 >> 234 /* Report Cache management debug options */ >> 235 if (mt_protiflush) >> 236 printk("I-cache flushes single-threaded\n"); >> 237 if (mt_protdflush) >> 238 printk("D-cache flushes single-threaded\n"); >> 239 if (mt_n_iflushes != 1) >> 240 printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes); >> 241 if (mt_n_dflushes != 1) >> 242 printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes); >> 243 191 if (itc_base != 0) { 244 if (itc_base != 0) { 192 /* 245 /* 193 * Configure ITC mapping. Thi 246 * Configure ITC mapping. This code is very 194 * specific to the 34K core fa 247 * specific to the 34K core family, which uses 195 * a special mode bit ("ITC") 248 * a special mode bit ("ITC") in the ErrCtl 196 * register to enable access t 249 * register to enable access to ITC control 197 * registers via cache "tag" o 250 * registers via cache "tag" operations. 198 */ 251 */ 199 unsigned long ectlval; 252 unsigned long ectlval; 200 unsigned long itcblkgrn; 253 unsigned long itcblkgrn; 201 254 202 /* ErrCtl register is known as 255 /* ErrCtl register is known as "ecc" to Linux */ 203 ectlval = read_c0_ecc(); 256 ectlval = read_c0_ecc(); 204 write_c0_ecc(ectlval | (0x1 << 257 write_c0_ecc(ectlval | (0x1 << 26)); 205 ehb(); 258 ehb(); 206 #define INDEX_0 (0x80000000) 259 #define INDEX_0 (0x80000000) 207 #define INDEX_8 (0x80000008) 260 #define INDEX_8 (0x80000008) 208 /* Read "cache tag" for Dcache 261 /* Read "cache tag" for Dcache pseudo-index 8 */ 209 cache_op(Index_Load_Tag_D, IND 262 cache_op(Index_Load_Tag_D, INDEX_8); 210 ehb(); 263 ehb(); 211 itcblkgrn = read_c0_dtaglo(); 264 itcblkgrn = read_c0_dtaglo(); 212 itcblkgrn &= 0xfffe0000; 265 itcblkgrn &= 0xfffe0000; 213 /* Set for 128 byte pitch of I 266 /* Set for 128 byte pitch of ITC cells */ 214 itcblkgrn |= 0x00000c00; 267 itcblkgrn |= 0x00000c00; 215 /* Stage in Tag register */ 268 /* Stage in Tag register */ 216 write_c0_dtaglo(itcblkgrn); 269 write_c0_dtaglo(itcblkgrn); 217 ehb(); 270 ehb(); 218 /* Write out to ITU with CACHE 271 /* Write out to ITU with CACHE op */ 219 cache_op(Index_Store_Tag_D, IN 272 cache_op(Index_Store_Tag_D, INDEX_8); 220 /* Now set base address, and t 273 /* Now set base address, and turn ITC on with 0x1 bit */ 221 write_c0_dtaglo((itc_base & 0x 274 write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 ); 222 ehb(); 275 ehb(); 223 /* Write out to ITU with CACHE 276 /* Write out to ITU with CACHE op */ 224 cache_op(Index_Store_Tag_D, IN 277 cache_op(Index_Store_Tag_D, INDEX_0); 225 write_c0_ecc(ectlval); 278 write_c0_ecc(ectlval); 226 ehb(); 279 ehb(); 227 printk("Mapped %ld ITC cells s 280 printk("Mapped %ld ITC cells starting at 0x%08x\n", 228 ((itcblkgrn & 0x7fe000 281 ((itcblkgrn & 0x7fe00000) >> 20), itc_base); 229 } 282 } 230 } 283 } 231 284 232 const struct class mt_class = { !! 285 /* 233 .name = "mt", !! 286 * Function to protect cache flushes from concurrent execution 234 }; !! 287 * depends on MP software model chosen. >> 288 */ 235 289 236 static int __init mips_mt_init(void) !! 290 void mt_cflush_lockdown(void) 237 { 291 { 238 return class_register(&mt_class); !! 292 /* FILL IN VSMP and AP/SP VERSIONS HERE */ >> 293 } >> 294 >> 295 void mt_cflush_release(void) >> 296 { >> 297 /* FILL IN VSMP and AP/SP VERSIONS HERE */ >> 298 } >> 299 >> 300 struct class *mt_class; >> 301 >> 302 static int __init mt_init(void) >> 303 { >> 304 struct class *mtc; >> 305 >> 306 mtc = class_create(THIS_MODULE, "mt"); >> 307 if (IS_ERR(mtc)) >> 308 return PTR_ERR(mtc); >> 309 >> 310 mt_class = mtc; >> 311 >> 312 return 0; 239 } 313 } 240 314 241 subsys_initcall(mips_mt_init); !! 315 subsys_initcall(mt_init); 242 316
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