1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0 2 /* 2 /* 3 * General MIPS MT support routines, usable in 3 * General MIPS MT support routines, usable in AP/SP and SMVP. 4 * Copyright (C) 2005 Mips Technologies, Inc 4 * Copyright (C) 2005 Mips Technologies, Inc 5 */ 5 */ 6 6 7 #include <linux/device.h> 7 #include <linux/device.h> 8 #include <linux/kernel.h> 8 #include <linux/kernel.h> 9 #include <linux/sched.h> 9 #include <linux/sched.h> 10 #include <linux/export.h> 10 #include <linux/export.h> 11 #include <linux/interrupt.h> 11 #include <linux/interrupt.h> 12 #include <linux/security.h> 12 #include <linux/security.h> 13 13 14 #include <asm/cpu.h> 14 #include <asm/cpu.h> 15 #include <asm/processor.h> 15 #include <asm/processor.h> 16 #include <linux/atomic.h> 16 #include <linux/atomic.h> 17 #include <asm/hardirq.h> 17 #include <asm/hardirq.h> 18 #include <asm/mmu_context.h> 18 #include <asm/mmu_context.h> 19 #include <asm/mipsmtregs.h> 19 #include <asm/mipsmtregs.h> 20 #include <asm/r4kcache.h> 20 #include <asm/r4kcache.h> 21 #include <asm/cacheflush.h> 21 #include <asm/cacheflush.h> 22 #include <asm/mips_mt.h> << 23 22 24 int vpelimit; 23 int vpelimit; 25 24 26 static int __init maxvpes(char *str) 25 static int __init maxvpes(char *str) 27 { 26 { 28 get_option(&str, &vpelimit); 27 get_option(&str, &vpelimit); 29 28 30 return 1; 29 return 1; 31 } 30 } 32 31 33 __setup("maxvpes=", maxvpes); 32 __setup("maxvpes=", maxvpes); 34 33 35 int tclimit; 34 int tclimit; 36 35 37 static int __init maxtcs(char *str) 36 static int __init maxtcs(char *str) 38 { 37 { 39 get_option(&str, &tclimit); 38 get_option(&str, &tclimit); 40 39 41 return 1; 40 return 1; 42 } 41 } 43 42 44 __setup("maxtcs=", maxtcs); 43 __setup("maxtcs=", maxtcs); 45 44 46 /* 45 /* 47 * Dump new MIPS MT state for the core. Does n 46 * Dump new MIPS MT state for the core. Does not leave TCs halted. 48 * Takes an argument which taken to be a pre-c 47 * Takes an argument which taken to be a pre-call MVPControl value. 49 */ 48 */ 50 49 51 void mips_mt_regdump(unsigned long mvpctl) 50 void mips_mt_regdump(unsigned long mvpctl) 52 { 51 { 53 unsigned long flags; 52 unsigned long flags; 54 unsigned long vpflags; 53 unsigned long vpflags; 55 unsigned long mvpconf0; 54 unsigned long mvpconf0; 56 int nvpe; 55 int nvpe; 57 int ntc; 56 int ntc; 58 int i; 57 int i; 59 int tc; 58 int tc; 60 unsigned long haltval; 59 unsigned long haltval; 61 unsigned long tcstatval; 60 unsigned long tcstatval; 62 61 63 local_irq_save(flags); 62 local_irq_save(flags); 64 vpflags = dvpe(); 63 vpflags = dvpe(); 65 printk("=== MIPS MT State Dump ===\n") 64 printk("=== MIPS MT State Dump ===\n"); 66 printk("-- Global State --\n"); 65 printk("-- Global State --\n"); 67 printk(" MVPControl Passed: %08lx\n" 66 printk(" MVPControl Passed: %08lx\n", mvpctl); 68 printk(" MVPControl Read: %08lx\n", 67 printk(" MVPControl Read: %08lx\n", vpflags); 69 printk(" MVPConf0 : %08lx\n", (mvpco 68 printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0())); 70 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> 69 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; 71 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MV 70 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; 72 printk("-- per-VPE State --\n"); 71 printk("-- per-VPE State --\n"); 73 for (i = 0; i < nvpe; i++) { 72 for (i = 0; i < nvpe; i++) { 74 for (tc = 0; tc < ntc; tc++) { 73 for (tc = 0; tc < ntc; tc++) { 75 settc(tc); 74 settc(tc); 76 if ((read_tc_c0_tcbind 75 if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) { 77 printk(" VPE 76 printk(" VPE %d\n", i); 78 printk(" VPE 77 printk(" VPEControl : %08lx\n", 79 read_vp 78 read_vpe_c0_vpecontrol()); 80 printk(" VPE 79 printk(" VPEConf0 : %08lx\n", 81 read_vp 80 read_vpe_c0_vpeconf0()); 82 printk(" VPE 81 printk(" VPE%d.Status : %08lx\n", 83 i, read 82 i, read_vpe_c0_status()); 84 printk(" VPE 83 printk(" VPE%d.EPC : %08lx %pS\n", 85 i, read 84 i, read_vpe_c0_epc(), 86 (void * 85 (void *) read_vpe_c0_epc()); 87 printk(" VPE 86 printk(" VPE%d.Cause : %08lx\n", 88 i, read 87 i, read_vpe_c0_cause()); 89 printk(" VPE 88 printk(" VPE%d.Config7 : %08lx\n", 90 i, read 89 i, read_vpe_c0_config7()); 91 break; /* Next 90 break; /* Next VPE */ 92 } 91 } 93 } 92 } 94 } 93 } 95 printk("-- per-TC State --\n"); 94 printk("-- per-TC State --\n"); 96 for (tc = 0; tc < ntc; tc++) { 95 for (tc = 0; tc < ntc; tc++) { 97 settc(tc); 96 settc(tc); 98 if (read_tc_c0_tcbind() == rea 97 if (read_tc_c0_tcbind() == read_c0_tcbind()) { 99 /* Are we dumping ours 98 /* Are we dumping ourself? */ 100 haltval = 0; /* Then w 99 haltval = 0; /* Then we're not halted, and mustn't be */ 101 tcstatval = flags; /* 100 tcstatval = flags; /* And pre-dump TCStatus is flags */ 102 printk(" TC %d (curre 101 printk(" TC %d (current TC with VPE EPC above)\n", tc); 103 } else { 102 } else { 104 haltval = read_tc_c0_t 103 haltval = read_tc_c0_tchalt(); 105 write_tc_c0_tchalt(1); 104 write_tc_c0_tchalt(1); 106 tcstatval = read_tc_c0 105 tcstatval = read_tc_c0_tcstatus(); 107 printk(" TC %d\n", tc 106 printk(" TC %d\n", tc); 108 } 107 } 109 printk(" TCStatus : %08lx\n" 108 printk(" TCStatus : %08lx\n", tcstatval); 110 printk(" TCBind : %08lx\n", 109 printk(" TCBind : %08lx\n", read_tc_c0_tcbind()); 111 printk(" TCRestart : %08lx % 110 printk(" TCRestart : %08lx %pS\n", 112 read_tc_c0_tcrestart(), 111 read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart()); 113 printk(" TCHalt : %08lx\n", 112 printk(" TCHalt : %08lx\n", haltval); 114 printk(" TCContext : %08lx\n 113 printk(" TCContext : %08lx\n", read_tc_c0_tccontext()); 115 if (!haltval) 114 if (!haltval) 116 write_tc_c0_tchalt(0); 115 write_tc_c0_tchalt(0); 117 } 116 } 118 printk("===========================\n" 117 printk("===========================\n"); 119 evpe(vpflags); 118 evpe(vpflags); 120 local_irq_restore(flags); 119 local_irq_restore(flags); 121 } 120 } 122 121 >> 122 static int mt_opt_norps; 123 static int mt_opt_rpsctl = -1; 123 static int mt_opt_rpsctl = -1; 124 static int mt_opt_nblsu = -1; 124 static int mt_opt_nblsu = -1; 125 static int mt_opt_forceconfig7; 125 static int mt_opt_forceconfig7; 126 static int mt_opt_config7 = -1; 126 static int mt_opt_config7 = -1; 127 127 >> 128 static int __init rps_disable(char *s) >> 129 { >> 130 mt_opt_norps = 1; >> 131 return 1; >> 132 } >> 133 __setup("norps", rps_disable); >> 134 128 static int __init rpsctl_set(char *str) 135 static int __init rpsctl_set(char *str) 129 { 136 { 130 get_option(&str, &mt_opt_rpsctl); 137 get_option(&str, &mt_opt_rpsctl); 131 return 1; 138 return 1; 132 } 139 } 133 __setup("rpsctl=", rpsctl_set); 140 __setup("rpsctl=", rpsctl_set); 134 141 135 static int __init nblsu_set(char *str) 142 static int __init nblsu_set(char *str) 136 { 143 { 137 get_option(&str, &mt_opt_nblsu); 144 get_option(&str, &mt_opt_nblsu); 138 return 1; 145 return 1; 139 } 146 } 140 __setup("nblsu=", nblsu_set); 147 __setup("nblsu=", nblsu_set); 141 148 142 static int __init config7_set(char *str) 149 static int __init config7_set(char *str) 143 { 150 { 144 get_option(&str, &mt_opt_config7); 151 get_option(&str, &mt_opt_config7); 145 mt_opt_forceconfig7 = 1; 152 mt_opt_forceconfig7 = 1; 146 return 1; 153 return 1; 147 } 154 } 148 __setup("config7=", config7_set); 155 __setup("config7=", config7_set); 149 156 >> 157 /* Experimental cache flush control parameters that should go away some day */ >> 158 int mt_protiflush; >> 159 int mt_protdflush; >> 160 int mt_n_iflushes = 1; >> 161 int mt_n_dflushes = 1; >> 162 >> 163 static int __init set_protiflush(char *s) >> 164 { >> 165 mt_protiflush = 1; >> 166 return 1; >> 167 } >> 168 __setup("protiflush", set_protiflush); >> 169 >> 170 static int __init set_protdflush(char *s) >> 171 { >> 172 mt_protdflush = 1; >> 173 return 1; >> 174 } >> 175 __setup("protdflush", set_protdflush); >> 176 >> 177 static int __init niflush(char *s) >> 178 { >> 179 get_option(&s, &mt_n_iflushes); >> 180 return 1; >> 181 } >> 182 __setup("niflush=", niflush); >> 183 >> 184 static int __init ndflush(char *s) >> 185 { >> 186 get_option(&s, &mt_n_dflushes); >> 187 return 1; >> 188 } >> 189 __setup("ndflush=", ndflush); >> 190 150 static unsigned int itc_base; 191 static unsigned int itc_base; 151 192 152 static int __init set_itc_base(char *str) 193 static int __init set_itc_base(char *str) 153 { 194 { 154 get_option(&str, &itc_base); 195 get_option(&str, &itc_base); 155 return 1; 196 return 1; 156 } 197 } 157 198 158 __setup("itcbase=", set_itc_base); 199 __setup("itcbase=", set_itc_base); 159 200 160 void mips_mt_set_cpuoptions(void) 201 void mips_mt_set_cpuoptions(void) 161 { 202 { 162 unsigned int oconfig7 = read_c0_config 203 unsigned int oconfig7 = read_c0_config7(); 163 unsigned int nconfig7 = oconfig7; 204 unsigned int nconfig7 = oconfig7; 164 205 >> 206 if (mt_opt_norps) { >> 207 printk("\"norps\" option deprecated: use \"rpsctl=\"\n"); >> 208 } 165 if (mt_opt_rpsctl >= 0) { 209 if (mt_opt_rpsctl >= 0) { 166 printk("34K return prediction 210 printk("34K return prediction stack override set to %d.\n", 167 mt_opt_rpsctl); 211 mt_opt_rpsctl); 168 if (mt_opt_rpsctl) 212 if (mt_opt_rpsctl) 169 nconfig7 |= (1 << 2); 213 nconfig7 |= (1 << 2); 170 else 214 else 171 nconfig7 &= ~(1 << 2); 215 nconfig7 &= ~(1 << 2); 172 } 216 } 173 if (mt_opt_nblsu >= 0) { 217 if (mt_opt_nblsu >= 0) { 174 printk("34K ALU/LSU sync overr 218 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu); 175 if (mt_opt_nblsu) 219 if (mt_opt_nblsu) 176 nconfig7 |= (1 << 5); 220 nconfig7 |= (1 << 5); 177 else 221 else 178 nconfig7 &= ~(1 << 5); 222 nconfig7 &= ~(1 << 5); 179 } 223 } 180 if (mt_opt_forceconfig7) { 224 if (mt_opt_forceconfig7) { 181 printk("CP0.Config7 forced to 225 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7); 182 nconfig7 = mt_opt_config7; 226 nconfig7 = mt_opt_config7; 183 } 227 } 184 if (oconfig7 != nconfig7) { 228 if (oconfig7 != nconfig7) { 185 __asm__ __volatile("sync"); 229 __asm__ __volatile("sync"); 186 write_c0_config7(nconfig7); 230 write_c0_config7(nconfig7); 187 ehb(); 231 ehb(); 188 printk("Config7: 0x%08x\n", re 232 printk("Config7: 0x%08x\n", read_c0_config7()); 189 } 233 } 190 234 >> 235 /* Report Cache management debug options */ >> 236 if (mt_protiflush) >> 237 printk("I-cache flushes single-threaded\n"); >> 238 if (mt_protdflush) >> 239 printk("D-cache flushes single-threaded\n"); >> 240 if (mt_n_iflushes != 1) >> 241 printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes); >> 242 if (mt_n_dflushes != 1) >> 243 printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes); >> 244 191 if (itc_base != 0) { 245 if (itc_base != 0) { 192 /* 246 /* 193 * Configure ITC mapping. Thi 247 * Configure ITC mapping. This code is very 194 * specific to the 34K core fa 248 * specific to the 34K core family, which uses 195 * a special mode bit ("ITC") 249 * a special mode bit ("ITC") in the ErrCtl 196 * register to enable access t 250 * register to enable access to ITC control 197 * registers via cache "tag" o 251 * registers via cache "tag" operations. 198 */ 252 */ 199 unsigned long ectlval; 253 unsigned long ectlval; 200 unsigned long itcblkgrn; 254 unsigned long itcblkgrn; 201 255 202 /* ErrCtl register is known as 256 /* ErrCtl register is known as "ecc" to Linux */ 203 ectlval = read_c0_ecc(); 257 ectlval = read_c0_ecc(); 204 write_c0_ecc(ectlval | (0x1 << 258 write_c0_ecc(ectlval | (0x1 << 26)); 205 ehb(); 259 ehb(); 206 #define INDEX_0 (0x80000000) 260 #define INDEX_0 (0x80000000) 207 #define INDEX_8 (0x80000008) 261 #define INDEX_8 (0x80000008) 208 /* Read "cache tag" for Dcache 262 /* Read "cache tag" for Dcache pseudo-index 8 */ 209 cache_op(Index_Load_Tag_D, IND 263 cache_op(Index_Load_Tag_D, INDEX_8); 210 ehb(); 264 ehb(); 211 itcblkgrn = read_c0_dtaglo(); 265 itcblkgrn = read_c0_dtaglo(); 212 itcblkgrn &= 0xfffe0000; 266 itcblkgrn &= 0xfffe0000; 213 /* Set for 128 byte pitch of I 267 /* Set for 128 byte pitch of ITC cells */ 214 itcblkgrn |= 0x00000c00; 268 itcblkgrn |= 0x00000c00; 215 /* Stage in Tag register */ 269 /* Stage in Tag register */ 216 write_c0_dtaglo(itcblkgrn); 270 write_c0_dtaglo(itcblkgrn); 217 ehb(); 271 ehb(); 218 /* Write out to ITU with CACHE 272 /* Write out to ITU with CACHE op */ 219 cache_op(Index_Store_Tag_D, IN 273 cache_op(Index_Store_Tag_D, INDEX_8); 220 /* Now set base address, and t 274 /* Now set base address, and turn ITC on with 0x1 bit */ 221 write_c0_dtaglo((itc_base & 0x 275 write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 ); 222 ehb(); 276 ehb(); 223 /* Write out to ITU with CACHE 277 /* Write out to ITU with CACHE op */ 224 cache_op(Index_Store_Tag_D, IN 278 cache_op(Index_Store_Tag_D, INDEX_0); 225 write_c0_ecc(ectlval); 279 write_c0_ecc(ectlval); 226 ehb(); 280 ehb(); 227 printk("Mapped %ld ITC cells s 281 printk("Mapped %ld ITC cells starting at 0x%08x\n", 228 ((itcblkgrn & 0x7fe000 282 ((itcblkgrn & 0x7fe00000) >> 20), itc_base); 229 } 283 } 230 } 284 } 231 285 232 const struct class mt_class = { !! 286 /* 233 .name = "mt", !! 287 * Function to protect cache flushes from concurrent execution 234 }; !! 288 * depends on MP software model chosen. >> 289 */ 235 290 236 static int __init mips_mt_init(void) !! 291 void mt_cflush_lockdown(void) 237 { 292 { 238 return class_register(&mt_class); !! 293 /* FILL IN VSMP and AP/SP VERSIONS HERE */ >> 294 } >> 295 >> 296 void mt_cflush_release(void) >> 297 { >> 298 /* FILL IN VSMP and AP/SP VERSIONS HERE */ >> 299 } >> 300 >> 301 struct class *mt_class; >> 302 >> 303 static int __init mt_init(void) >> 304 { >> 305 struct class *mtc; >> 306 >> 307 mtc = class_create(THIS_MODULE, "mt"); >> 308 if (IS_ERR(mtc)) >> 309 return PTR_ERR(mtc); >> 310 >> 311 mt_class = mtc; >> 312 >> 313 return 0; 239 } 314 } 240 315 241 subsys_initcall(mips_mt_init); !! 316 subsys_initcall(mt_init); 242 317
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