1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * General MIPS MT support routines, usable in 3 * General MIPS MT support routines, usable in AP/SP and SMVP.
4 * Copyright (C) 2005 Mips Technologies, Inc 4 * Copyright (C) 2005 Mips Technologies, Inc
5 */ 5 */
6 6
7 #include <linux/device.h> 7 #include <linux/device.h>
8 #include <linux/kernel.h> 8 #include <linux/kernel.h>
9 #include <linux/sched.h> 9 #include <linux/sched.h>
10 #include <linux/export.h> 10 #include <linux/export.h>
11 #include <linux/interrupt.h> 11 #include <linux/interrupt.h>
12 #include <linux/security.h> 12 #include <linux/security.h>
13 13
14 #include <asm/cpu.h> 14 #include <asm/cpu.h>
15 #include <asm/processor.h> 15 #include <asm/processor.h>
16 #include <linux/atomic.h> 16 #include <linux/atomic.h>
17 #include <asm/hardirq.h> 17 #include <asm/hardirq.h>
18 #include <asm/mmu_context.h> 18 #include <asm/mmu_context.h>
19 #include <asm/mipsmtregs.h> 19 #include <asm/mipsmtregs.h>
20 #include <asm/r4kcache.h> 20 #include <asm/r4kcache.h>
21 #include <asm/cacheflush.h> 21 #include <asm/cacheflush.h>
22 #include <asm/mips_mt.h> <<
23 22
24 int vpelimit; 23 int vpelimit;
25 24
26 static int __init maxvpes(char *str) 25 static int __init maxvpes(char *str)
27 { 26 {
28 get_option(&str, &vpelimit); 27 get_option(&str, &vpelimit);
29 28
30 return 1; 29 return 1;
31 } 30 }
32 31
33 __setup("maxvpes=", maxvpes); 32 __setup("maxvpes=", maxvpes);
34 33
35 int tclimit; 34 int tclimit;
36 35
37 static int __init maxtcs(char *str) 36 static int __init maxtcs(char *str)
38 { 37 {
39 get_option(&str, &tclimit); 38 get_option(&str, &tclimit);
40 39
41 return 1; 40 return 1;
42 } 41 }
43 42
44 __setup("maxtcs=", maxtcs); 43 __setup("maxtcs=", maxtcs);
45 44
>> 45 /*
>> 46 * Dump new MIPS MT state for the core. Does not leave TCs halted.
>> 47 * Takes an argument which taken to be a pre-call MVPControl value.
>> 48 */
>> 49
>> 50 void mips_mt_regdump(unsigned long mvpctl)
>> 51 {
>> 52 unsigned long flags;
>> 53 unsigned long vpflags;
>> 54 unsigned long mvpconf0;
>> 55 int nvpe;
>> 56 int ntc;
>> 57 int i;
>> 58 int tc;
>> 59 unsigned long haltval;
>> 60 unsigned long tcstatval;
>> 61
>> 62 local_irq_save(flags);
>> 63 vpflags = dvpe();
>> 64 printk("=== MIPS MT State Dump ===\n");
>> 65 printk("-- Global State --\n");
>> 66 printk(" MVPControl Passed: %08lx\n", mvpctl);
>> 67 printk(" MVPControl Read: %08lx\n", vpflags);
>> 68 printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
>> 69 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
>> 70 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
>> 71 printk("-- per-VPE State --\n");
>> 72 for (i = 0; i < nvpe; i++) {
>> 73 for (tc = 0; tc < ntc; tc++) {
>> 74 settc(tc);
>> 75 if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
>> 76 printk(" VPE %d\n", i);
>> 77 printk(" VPEControl : %08lx\n",
>> 78 read_vpe_c0_vpecontrol());
>> 79 printk(" VPEConf0 : %08lx\n",
>> 80 read_vpe_c0_vpeconf0());
>> 81 printk(" VPE%d.Status : %08lx\n",
>> 82 i, read_vpe_c0_status());
>> 83 printk(" VPE%d.EPC : %08lx %pS\n",
>> 84 i, read_vpe_c0_epc(),
>> 85 (void *) read_vpe_c0_epc());
>> 86 printk(" VPE%d.Cause : %08lx\n",
>> 87 i, read_vpe_c0_cause());
>> 88 printk(" VPE%d.Config7 : %08lx\n",
>> 89 i, read_vpe_c0_config7());
>> 90 break; /* Next VPE */
>> 91 }
>> 92 }
>> 93 }
>> 94 printk("-- per-TC State --\n");
>> 95 for (tc = 0; tc < ntc; tc++) {
>> 96 settc(tc);
>> 97 if (read_tc_c0_tcbind() == read_c0_tcbind()) {
>> 98 /* Are we dumping ourself? */
>> 99 haltval = 0; /* Then we're not halted, and mustn't be */
>> 100 tcstatval = flags; /* And pre-dump TCStatus is flags */
>> 101 printk(" TC %d (current TC with VPE EPC above)\n", tc);
>> 102 } else {
>> 103 haltval = read_tc_c0_tchalt();
>> 104 write_tc_c0_tchalt(1);
>> 105 tcstatval = read_tc_c0_tcstatus();
>> 106 printk(" TC %d\n", tc);
>> 107 }
>> 108 printk(" TCStatus : %08lx\n", tcstatval);
>> 109 printk(" TCBind : %08lx\n", read_tc_c0_tcbind());
>> 110 printk(" TCRestart : %08lx %pS\n",
>> 111 read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart());
>> 112 printk(" TCHalt : %08lx\n", haltval);
>> 113 printk(" TCContext : %08lx\n", read_tc_c0_tccontext());
>> 114 if (!haltval)
>> 115 write_tc_c0_tchalt(0);
>> 116 }
>> 117 printk("===========================\n");
>> 118 evpe(vpflags);
>> 119 local_irq_restore(flags);
>> 120 }
>> 121
46 static int mt_opt_rpsctl = -1; 122 static int mt_opt_rpsctl = -1;
47 static int mt_opt_nblsu = -1; 123 static int mt_opt_nblsu = -1;
48 static int mt_opt_forceconfig7; 124 static int mt_opt_forceconfig7;
49 static int mt_opt_config7 = -1; 125 static int mt_opt_config7 = -1;
50 126
51 static int __init rpsctl_set(char *str) 127 static int __init rpsctl_set(char *str)
52 { 128 {
53 get_option(&str, &mt_opt_rpsctl); 129 get_option(&str, &mt_opt_rpsctl);
54 return 1; 130 return 1;
55 } 131 }
56 __setup("rpsctl=", rpsctl_set); 132 __setup("rpsctl=", rpsctl_set);
57 133
58 static int __init nblsu_set(char *str) 134 static int __init nblsu_set(char *str)
59 { 135 {
60 get_option(&str, &mt_opt_nblsu); 136 get_option(&str, &mt_opt_nblsu);
61 return 1; 137 return 1;
62 } 138 }
63 __setup("nblsu=", nblsu_set); 139 __setup("nblsu=", nblsu_set);
64 140
65 static int __init config7_set(char *str) 141 static int __init config7_set(char *str)
66 { 142 {
67 get_option(&str, &mt_opt_config7); 143 get_option(&str, &mt_opt_config7);
68 mt_opt_forceconfig7 = 1; 144 mt_opt_forceconfig7 = 1;
69 return 1; 145 return 1;
70 } 146 }
71 __setup("config7=", config7_set); 147 __setup("config7=", config7_set);
72 148
73 static unsigned int itc_base; 149 static unsigned int itc_base;
74 150
75 static int __init set_itc_base(char *str) 151 static int __init set_itc_base(char *str)
76 { 152 {
77 get_option(&str, &itc_base); 153 get_option(&str, &itc_base);
78 return 1; 154 return 1;
79 } 155 }
80 156
81 __setup("itcbase=", set_itc_base); 157 __setup("itcbase=", set_itc_base);
82 158
83 void mips_mt_set_cpuoptions(void) 159 void mips_mt_set_cpuoptions(void)
84 { 160 {
85 unsigned int oconfig7 = read_c0_config 161 unsigned int oconfig7 = read_c0_config7();
86 unsigned int nconfig7 = oconfig7; 162 unsigned int nconfig7 = oconfig7;
87 163
88 if (mt_opt_rpsctl >= 0) { 164 if (mt_opt_rpsctl >= 0) {
89 printk("34K return prediction 165 printk("34K return prediction stack override set to %d.\n",
90 mt_opt_rpsctl); 166 mt_opt_rpsctl);
91 if (mt_opt_rpsctl) 167 if (mt_opt_rpsctl)
92 nconfig7 |= (1 << 2); 168 nconfig7 |= (1 << 2);
93 else 169 else
94 nconfig7 &= ~(1 << 2); 170 nconfig7 &= ~(1 << 2);
95 } 171 }
96 if (mt_opt_nblsu >= 0) { 172 if (mt_opt_nblsu >= 0) {
97 printk("34K ALU/LSU sync overr 173 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
98 if (mt_opt_nblsu) 174 if (mt_opt_nblsu)
99 nconfig7 |= (1 << 5); 175 nconfig7 |= (1 << 5);
100 else 176 else
101 nconfig7 &= ~(1 << 5); 177 nconfig7 &= ~(1 << 5);
102 } 178 }
103 if (mt_opt_forceconfig7) { 179 if (mt_opt_forceconfig7) {
104 printk("CP0.Config7 forced to 180 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
105 nconfig7 = mt_opt_config7; 181 nconfig7 = mt_opt_config7;
106 } 182 }
107 if (oconfig7 != nconfig7) { 183 if (oconfig7 != nconfig7) {
108 __asm__ __volatile("sync"); 184 __asm__ __volatile("sync");
109 write_c0_config7(nconfig7); 185 write_c0_config7(nconfig7);
110 ehb(); 186 ehb();
111 printk("Config7: 0x%08x\n", re 187 printk("Config7: 0x%08x\n", read_c0_config7());
112 } 188 }
113 189
114 if (itc_base != 0) { 190 if (itc_base != 0) {
115 /* 191 /*
116 * Configure ITC mapping. Thi 192 * Configure ITC mapping. This code is very
117 * specific to the 34K core fa 193 * specific to the 34K core family, which uses
118 * a special mode bit ("ITC") 194 * a special mode bit ("ITC") in the ErrCtl
119 * register to enable access t 195 * register to enable access to ITC control
120 * registers via cache "tag" o 196 * registers via cache "tag" operations.
121 */ 197 */
122 unsigned long ectlval; 198 unsigned long ectlval;
123 unsigned long itcblkgrn; 199 unsigned long itcblkgrn;
124 200
125 /* ErrCtl register is known as 201 /* ErrCtl register is known as "ecc" to Linux */
126 ectlval = read_c0_ecc(); 202 ectlval = read_c0_ecc();
127 write_c0_ecc(ectlval | (0x1 << 203 write_c0_ecc(ectlval | (0x1 << 26));
128 ehb(); 204 ehb();
129 #define INDEX_0 (0x80000000) 205 #define INDEX_0 (0x80000000)
130 #define INDEX_8 (0x80000008) 206 #define INDEX_8 (0x80000008)
131 /* Read "cache tag" for Dcache 207 /* Read "cache tag" for Dcache pseudo-index 8 */
132 cache_op(Index_Load_Tag_D, IND 208 cache_op(Index_Load_Tag_D, INDEX_8);
133 ehb(); 209 ehb();
134 itcblkgrn = read_c0_dtaglo(); 210 itcblkgrn = read_c0_dtaglo();
135 itcblkgrn &= 0xfffe0000; 211 itcblkgrn &= 0xfffe0000;
136 /* Set for 128 byte pitch of I 212 /* Set for 128 byte pitch of ITC cells */
137 itcblkgrn |= 0x00000c00; 213 itcblkgrn |= 0x00000c00;
138 /* Stage in Tag register */ 214 /* Stage in Tag register */
139 write_c0_dtaglo(itcblkgrn); 215 write_c0_dtaglo(itcblkgrn);
140 ehb(); 216 ehb();
141 /* Write out to ITU with CACHE 217 /* Write out to ITU with CACHE op */
142 cache_op(Index_Store_Tag_D, IN 218 cache_op(Index_Store_Tag_D, INDEX_8);
143 /* Now set base address, and t 219 /* Now set base address, and turn ITC on with 0x1 bit */
144 write_c0_dtaglo((itc_base & 0x 220 write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
145 ehb(); 221 ehb();
146 /* Write out to ITU with CACHE 222 /* Write out to ITU with CACHE op */
147 cache_op(Index_Store_Tag_D, IN 223 cache_op(Index_Store_Tag_D, INDEX_0);
148 write_c0_ecc(ectlval); 224 write_c0_ecc(ectlval);
149 ehb(); 225 ehb();
150 printk("Mapped %ld ITC cells s 226 printk("Mapped %ld ITC cells starting at 0x%08x\n",
151 ((itcblkgrn & 0x7fe000 227 ((itcblkgrn & 0x7fe00000) >> 20), itc_base);
152 } 228 }
153 } 229 }
154 230
155 const struct class mt_class = { !! 231 struct class *mt_class;
156 .name = "mt", <<
157 }; <<
158 232
159 static int __init mips_mt_init(void) !! 233 static int __init mt_init(void)
160 { 234 {
161 return class_register(&mt_class); !! 235 struct class *mtc;
>> 236
>> 237 mtc = class_create(THIS_MODULE, "mt");
>> 238 if (IS_ERR(mtc))
>> 239 return PTR_ERR(mtc);
>> 240
>> 241 mt_class = mtc;
>> 242
>> 243 return 0;
162 } 244 }
163 245
164 subsys_initcall(mips_mt_init); !! 246 subsys_initcall(mt_init);
165 247
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