1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * General MIPS MT support routines, usable in 3 * General MIPS MT support routines, usable in AP/SP and SMVP.
4 * Copyright (C) 2005 Mips Technologies, Inc 4 * Copyright (C) 2005 Mips Technologies, Inc
5 */ 5 */
6 6
7 #include <linux/device.h> 7 #include <linux/device.h>
8 #include <linux/kernel.h> 8 #include <linux/kernel.h>
9 #include <linux/sched.h> 9 #include <linux/sched.h>
10 #include <linux/export.h> 10 #include <linux/export.h>
11 #include <linux/interrupt.h> 11 #include <linux/interrupt.h>
12 #include <linux/security.h> 12 #include <linux/security.h>
13 13
14 #include <asm/cpu.h> 14 #include <asm/cpu.h>
15 #include <asm/processor.h> 15 #include <asm/processor.h>
16 #include <linux/atomic.h> 16 #include <linux/atomic.h>
17 #include <asm/hardirq.h> 17 #include <asm/hardirq.h>
18 #include <asm/mmu_context.h> 18 #include <asm/mmu_context.h>
19 #include <asm/mipsmtregs.h> 19 #include <asm/mipsmtregs.h>
20 #include <asm/r4kcache.h> 20 #include <asm/r4kcache.h>
21 #include <asm/cacheflush.h> 21 #include <asm/cacheflush.h>
22 #include <asm/mips_mt.h> 22 #include <asm/mips_mt.h>
23 23
24 int vpelimit; 24 int vpelimit;
25 25
26 static int __init maxvpes(char *str) 26 static int __init maxvpes(char *str)
27 { 27 {
28 get_option(&str, &vpelimit); 28 get_option(&str, &vpelimit);
29 29
30 return 1; 30 return 1;
31 } 31 }
32 32
33 __setup("maxvpes=", maxvpes); 33 __setup("maxvpes=", maxvpes);
34 34
35 int tclimit; 35 int tclimit;
36 36
37 static int __init maxtcs(char *str) 37 static int __init maxtcs(char *str)
38 { 38 {
39 get_option(&str, &tclimit); 39 get_option(&str, &tclimit);
40 40
41 return 1; 41 return 1;
42 } 42 }
43 43
44 __setup("maxtcs=", maxtcs); 44 __setup("maxtcs=", maxtcs);
45 45
>> 46 /*
>> 47 * Dump new MIPS MT state for the core. Does not leave TCs halted.
>> 48 * Takes an argument which taken to be a pre-call MVPControl value.
>> 49 */
>> 50
>> 51 void mips_mt_regdump(unsigned long mvpctl)
>> 52 {
>> 53 unsigned long flags;
>> 54 unsigned long vpflags;
>> 55 unsigned long mvpconf0;
>> 56 int nvpe;
>> 57 int ntc;
>> 58 int i;
>> 59 int tc;
>> 60 unsigned long haltval;
>> 61 unsigned long tcstatval;
>> 62
>> 63 local_irq_save(flags);
>> 64 vpflags = dvpe();
>> 65 printk("=== MIPS MT State Dump ===\n");
>> 66 printk("-- Global State --\n");
>> 67 printk(" MVPControl Passed: %08lx\n", mvpctl);
>> 68 printk(" MVPControl Read: %08lx\n", vpflags);
>> 69 printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
>> 70 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
>> 71 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
>> 72 printk("-- per-VPE State --\n");
>> 73 for (i = 0; i < nvpe; i++) {
>> 74 for (tc = 0; tc < ntc; tc++) {
>> 75 settc(tc);
>> 76 if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
>> 77 printk(" VPE %d\n", i);
>> 78 printk(" VPEControl : %08lx\n",
>> 79 read_vpe_c0_vpecontrol());
>> 80 printk(" VPEConf0 : %08lx\n",
>> 81 read_vpe_c0_vpeconf0());
>> 82 printk(" VPE%d.Status : %08lx\n",
>> 83 i, read_vpe_c0_status());
>> 84 printk(" VPE%d.EPC : %08lx %pS\n",
>> 85 i, read_vpe_c0_epc(),
>> 86 (void *) read_vpe_c0_epc());
>> 87 printk(" VPE%d.Cause : %08lx\n",
>> 88 i, read_vpe_c0_cause());
>> 89 printk(" VPE%d.Config7 : %08lx\n",
>> 90 i, read_vpe_c0_config7());
>> 91 break; /* Next VPE */
>> 92 }
>> 93 }
>> 94 }
>> 95 printk("-- per-TC State --\n");
>> 96 for (tc = 0; tc < ntc; tc++) {
>> 97 settc(tc);
>> 98 if (read_tc_c0_tcbind() == read_c0_tcbind()) {
>> 99 /* Are we dumping ourself? */
>> 100 haltval = 0; /* Then we're not halted, and mustn't be */
>> 101 tcstatval = flags; /* And pre-dump TCStatus is flags */
>> 102 printk(" TC %d (current TC with VPE EPC above)\n", tc);
>> 103 } else {
>> 104 haltval = read_tc_c0_tchalt();
>> 105 write_tc_c0_tchalt(1);
>> 106 tcstatval = read_tc_c0_tcstatus();
>> 107 printk(" TC %d\n", tc);
>> 108 }
>> 109 printk(" TCStatus : %08lx\n", tcstatval);
>> 110 printk(" TCBind : %08lx\n", read_tc_c0_tcbind());
>> 111 printk(" TCRestart : %08lx %pS\n",
>> 112 read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart());
>> 113 printk(" TCHalt : %08lx\n", haltval);
>> 114 printk(" TCContext : %08lx\n", read_tc_c0_tccontext());
>> 115 if (!haltval)
>> 116 write_tc_c0_tchalt(0);
>> 117 }
>> 118 printk("===========================\n");
>> 119 evpe(vpflags);
>> 120 local_irq_restore(flags);
>> 121 }
>> 122
46 static int mt_opt_rpsctl = -1; 123 static int mt_opt_rpsctl = -1;
47 static int mt_opt_nblsu = -1; 124 static int mt_opt_nblsu = -1;
48 static int mt_opt_forceconfig7; 125 static int mt_opt_forceconfig7;
49 static int mt_opt_config7 = -1; 126 static int mt_opt_config7 = -1;
50 127
51 static int __init rpsctl_set(char *str) 128 static int __init rpsctl_set(char *str)
52 { 129 {
53 get_option(&str, &mt_opt_rpsctl); 130 get_option(&str, &mt_opt_rpsctl);
54 return 1; 131 return 1;
55 } 132 }
56 __setup("rpsctl=", rpsctl_set); 133 __setup("rpsctl=", rpsctl_set);
57 134
58 static int __init nblsu_set(char *str) 135 static int __init nblsu_set(char *str)
59 { 136 {
60 get_option(&str, &mt_opt_nblsu); 137 get_option(&str, &mt_opt_nblsu);
61 return 1; 138 return 1;
62 } 139 }
63 __setup("nblsu=", nblsu_set); 140 __setup("nblsu=", nblsu_set);
64 141
65 static int __init config7_set(char *str) 142 static int __init config7_set(char *str)
66 { 143 {
67 get_option(&str, &mt_opt_config7); 144 get_option(&str, &mt_opt_config7);
68 mt_opt_forceconfig7 = 1; 145 mt_opt_forceconfig7 = 1;
69 return 1; 146 return 1;
70 } 147 }
71 __setup("config7=", config7_set); 148 __setup("config7=", config7_set);
72 149
73 static unsigned int itc_base; 150 static unsigned int itc_base;
74 151
75 static int __init set_itc_base(char *str) 152 static int __init set_itc_base(char *str)
76 { 153 {
77 get_option(&str, &itc_base); 154 get_option(&str, &itc_base);
78 return 1; 155 return 1;
79 } 156 }
80 157
81 __setup("itcbase=", set_itc_base); 158 __setup("itcbase=", set_itc_base);
82 159
83 void mips_mt_set_cpuoptions(void) 160 void mips_mt_set_cpuoptions(void)
84 { 161 {
85 unsigned int oconfig7 = read_c0_config 162 unsigned int oconfig7 = read_c0_config7();
86 unsigned int nconfig7 = oconfig7; 163 unsigned int nconfig7 = oconfig7;
87 164
88 if (mt_opt_rpsctl >= 0) { 165 if (mt_opt_rpsctl >= 0) {
89 printk("34K return prediction 166 printk("34K return prediction stack override set to %d.\n",
90 mt_opt_rpsctl); 167 mt_opt_rpsctl);
91 if (mt_opt_rpsctl) 168 if (mt_opt_rpsctl)
92 nconfig7 |= (1 << 2); 169 nconfig7 |= (1 << 2);
93 else 170 else
94 nconfig7 &= ~(1 << 2); 171 nconfig7 &= ~(1 << 2);
95 } 172 }
96 if (mt_opt_nblsu >= 0) { 173 if (mt_opt_nblsu >= 0) {
97 printk("34K ALU/LSU sync overr 174 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
98 if (mt_opt_nblsu) 175 if (mt_opt_nblsu)
99 nconfig7 |= (1 << 5); 176 nconfig7 |= (1 << 5);
100 else 177 else
101 nconfig7 &= ~(1 << 5); 178 nconfig7 &= ~(1 << 5);
102 } 179 }
103 if (mt_opt_forceconfig7) { 180 if (mt_opt_forceconfig7) {
104 printk("CP0.Config7 forced to 181 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
105 nconfig7 = mt_opt_config7; 182 nconfig7 = mt_opt_config7;
106 } 183 }
107 if (oconfig7 != nconfig7) { 184 if (oconfig7 != nconfig7) {
108 __asm__ __volatile("sync"); 185 __asm__ __volatile("sync");
109 write_c0_config7(nconfig7); 186 write_c0_config7(nconfig7);
110 ehb(); 187 ehb();
111 printk("Config7: 0x%08x\n", re 188 printk("Config7: 0x%08x\n", read_c0_config7());
112 } 189 }
113 190
114 if (itc_base != 0) { 191 if (itc_base != 0) {
115 /* 192 /*
116 * Configure ITC mapping. Thi 193 * Configure ITC mapping. This code is very
117 * specific to the 34K core fa 194 * specific to the 34K core family, which uses
118 * a special mode bit ("ITC") 195 * a special mode bit ("ITC") in the ErrCtl
119 * register to enable access t 196 * register to enable access to ITC control
120 * registers via cache "tag" o 197 * registers via cache "tag" operations.
121 */ 198 */
122 unsigned long ectlval; 199 unsigned long ectlval;
123 unsigned long itcblkgrn; 200 unsigned long itcblkgrn;
124 201
125 /* ErrCtl register is known as 202 /* ErrCtl register is known as "ecc" to Linux */
126 ectlval = read_c0_ecc(); 203 ectlval = read_c0_ecc();
127 write_c0_ecc(ectlval | (0x1 << 204 write_c0_ecc(ectlval | (0x1 << 26));
128 ehb(); 205 ehb();
129 #define INDEX_0 (0x80000000) 206 #define INDEX_0 (0x80000000)
130 #define INDEX_8 (0x80000008) 207 #define INDEX_8 (0x80000008)
131 /* Read "cache tag" for Dcache 208 /* Read "cache tag" for Dcache pseudo-index 8 */
132 cache_op(Index_Load_Tag_D, IND 209 cache_op(Index_Load_Tag_D, INDEX_8);
133 ehb(); 210 ehb();
134 itcblkgrn = read_c0_dtaglo(); 211 itcblkgrn = read_c0_dtaglo();
135 itcblkgrn &= 0xfffe0000; 212 itcblkgrn &= 0xfffe0000;
136 /* Set for 128 byte pitch of I 213 /* Set for 128 byte pitch of ITC cells */
137 itcblkgrn |= 0x00000c00; 214 itcblkgrn |= 0x00000c00;
138 /* Stage in Tag register */ 215 /* Stage in Tag register */
139 write_c0_dtaglo(itcblkgrn); 216 write_c0_dtaglo(itcblkgrn);
140 ehb(); 217 ehb();
141 /* Write out to ITU with CACHE 218 /* Write out to ITU with CACHE op */
142 cache_op(Index_Store_Tag_D, IN 219 cache_op(Index_Store_Tag_D, INDEX_8);
143 /* Now set base address, and t 220 /* Now set base address, and turn ITC on with 0x1 bit */
144 write_c0_dtaglo((itc_base & 0x 221 write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
145 ehb(); 222 ehb();
146 /* Write out to ITU with CACHE 223 /* Write out to ITU with CACHE op */
147 cache_op(Index_Store_Tag_D, IN 224 cache_op(Index_Store_Tag_D, INDEX_0);
148 write_c0_ecc(ectlval); 225 write_c0_ecc(ectlval);
149 ehb(); 226 ehb();
150 printk("Mapped %ld ITC cells s 227 printk("Mapped %ld ITC cells starting at 0x%08x\n",
151 ((itcblkgrn & 0x7fe000 228 ((itcblkgrn & 0x7fe00000) >> 20), itc_base);
152 } 229 }
153 } 230 }
154 231
155 const struct class mt_class = { !! 232 struct class *mt_class;
156 .name = "mt", <<
157 }; <<
158 233
159 static int __init mips_mt_init(void) 234 static int __init mips_mt_init(void)
160 { 235 {
161 return class_register(&mt_class); !! 236 struct class *mtc;
>> 237
>> 238 mtc = class_create("mt");
>> 239 if (IS_ERR(mtc))
>> 240 return PTR_ERR(mtc);
>> 241
>> 242 mt_class = mtc;
>> 243
>> 244 return 0;
162 } 245 }
163 246
164 subsys_initcall(mips_mt_init); 247 subsys_initcall(mips_mt_init);
165 248
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