1 // SPDX-License-Identifier: GPL-2.0 1
2 /*
3 * General MIPS MT support routines, usable in
4 * Copyright (C) 2005 Mips Technologies, Inc
5 */
6
7 #include <linux/device.h>
8 #include <linux/kernel.h>
9 #include <linux/sched.h>
10 #include <linux/export.h>
11 #include <linux/interrupt.h>
12 #include <linux/security.h>
13
14 #include <asm/cpu.h>
15 #include <asm/processor.h>
16 #include <linux/atomic.h>
17 #include <asm/hardirq.h>
18 #include <asm/mmu_context.h>
19 #include <asm/mipsmtregs.h>
20 #include <asm/r4kcache.h>
21 #include <asm/cacheflush.h>
22 #include <asm/mips_mt.h>
23
24 int vpelimit;
25
26 static int __init maxvpes(char *str)
27 {
28 get_option(&str, &vpelimit);
29
30 return 1;
31 }
32
33 __setup("maxvpes=", maxvpes);
34
35 int tclimit;
36
37 static int __init maxtcs(char *str)
38 {
39 get_option(&str, &tclimit);
40
41 return 1;
42 }
43
44 __setup("maxtcs=", maxtcs);
45
46 /*
47 * Dump new MIPS MT state for the core. Does n
48 * Takes an argument which taken to be a pre-c
49 */
50
51 void mips_mt_regdump(unsigned long mvpctl)
52 {
53 unsigned long flags;
54 unsigned long vpflags;
55 unsigned long mvpconf0;
56 int nvpe;
57 int ntc;
58 int i;
59 int tc;
60 unsigned long haltval;
61 unsigned long tcstatval;
62
63 local_irq_save(flags);
64 vpflags = dvpe();
65 printk("=== MIPS MT State Dump ===\n")
66 printk("-- Global State --\n");
67 printk(" MVPControl Passed: %08lx\n"
68 printk(" MVPControl Read: %08lx\n",
69 printk(" MVPConf0 : %08lx\n", (mvpco
70 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >>
71 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MV
72 printk("-- per-VPE State --\n");
73 for (i = 0; i < nvpe; i++) {
74 for (tc = 0; tc < ntc; tc++) {
75 settc(tc);
76 if ((read_tc_c0_tcbind
77 printk(" VPE
78 printk(" VPE
79 read_vp
80 printk(" VPE
81 read_vp
82 printk(" VPE
83 i, read
84 printk(" VPE
85 i, read
86 (void *
87 printk(" VPE
88 i, read
89 printk(" VPE
90 i, read
91 break; /* Next
92 }
93 }
94 }
95 printk("-- per-TC State --\n");
96 for (tc = 0; tc < ntc; tc++) {
97 settc(tc);
98 if (read_tc_c0_tcbind() == rea
99 /* Are we dumping ours
100 haltval = 0; /* Then w
101 tcstatval = flags; /*
102 printk(" TC %d (curre
103 } else {
104 haltval = read_tc_c0_t
105 write_tc_c0_tchalt(1);
106 tcstatval = read_tc_c0
107 printk(" TC %d\n", tc
108 }
109 printk(" TCStatus : %08lx\n"
110 printk(" TCBind : %08lx\n",
111 printk(" TCRestart : %08lx %
112 read_tc_c0_tcrestart(),
113 printk(" TCHalt : %08lx\n",
114 printk(" TCContext : %08lx\n
115 if (!haltval)
116 write_tc_c0_tchalt(0);
117 }
118 printk("===========================\n"
119 evpe(vpflags);
120 local_irq_restore(flags);
121 }
122
123 static int mt_opt_rpsctl = -1;
124 static int mt_opt_nblsu = -1;
125 static int mt_opt_forceconfig7;
126 static int mt_opt_config7 = -1;
127
128 static int __init rpsctl_set(char *str)
129 {
130 get_option(&str, &mt_opt_rpsctl);
131 return 1;
132 }
133 __setup("rpsctl=", rpsctl_set);
134
135 static int __init nblsu_set(char *str)
136 {
137 get_option(&str, &mt_opt_nblsu);
138 return 1;
139 }
140 __setup("nblsu=", nblsu_set);
141
142 static int __init config7_set(char *str)
143 {
144 get_option(&str, &mt_opt_config7);
145 mt_opt_forceconfig7 = 1;
146 return 1;
147 }
148 __setup("config7=", config7_set);
149
150 static unsigned int itc_base;
151
152 static int __init set_itc_base(char *str)
153 {
154 get_option(&str, &itc_base);
155 return 1;
156 }
157
158 __setup("itcbase=", set_itc_base);
159
160 void mips_mt_set_cpuoptions(void)
161 {
162 unsigned int oconfig7 = read_c0_config
163 unsigned int nconfig7 = oconfig7;
164
165 if (mt_opt_rpsctl >= 0) {
166 printk("34K return prediction
167 mt_opt_rpsctl);
168 if (mt_opt_rpsctl)
169 nconfig7 |= (1 << 2);
170 else
171 nconfig7 &= ~(1 << 2);
172 }
173 if (mt_opt_nblsu >= 0) {
174 printk("34K ALU/LSU sync overr
175 if (mt_opt_nblsu)
176 nconfig7 |= (1 << 5);
177 else
178 nconfig7 &= ~(1 << 5);
179 }
180 if (mt_opt_forceconfig7) {
181 printk("CP0.Config7 forced to
182 nconfig7 = mt_opt_config7;
183 }
184 if (oconfig7 != nconfig7) {
185 __asm__ __volatile("sync");
186 write_c0_config7(nconfig7);
187 ehb();
188 printk("Config7: 0x%08x\n", re
189 }
190
191 if (itc_base != 0) {
192 /*
193 * Configure ITC mapping. Thi
194 * specific to the 34K core fa
195 * a special mode bit ("ITC")
196 * register to enable access t
197 * registers via cache "tag" o
198 */
199 unsigned long ectlval;
200 unsigned long itcblkgrn;
201
202 /* ErrCtl register is known as
203 ectlval = read_c0_ecc();
204 write_c0_ecc(ectlval | (0x1 <<
205 ehb();
206 #define INDEX_0 (0x80000000)
207 #define INDEX_8 (0x80000008)
208 /* Read "cache tag" for Dcache
209 cache_op(Index_Load_Tag_D, IND
210 ehb();
211 itcblkgrn = read_c0_dtaglo();
212 itcblkgrn &= 0xfffe0000;
213 /* Set for 128 byte pitch of I
214 itcblkgrn |= 0x00000c00;
215 /* Stage in Tag register */
216 write_c0_dtaglo(itcblkgrn);
217 ehb();
218 /* Write out to ITU with CACHE
219 cache_op(Index_Store_Tag_D, IN
220 /* Now set base address, and t
221 write_c0_dtaglo((itc_base & 0x
222 ehb();
223 /* Write out to ITU with CACHE
224 cache_op(Index_Store_Tag_D, IN
225 write_c0_ecc(ectlval);
226 ehb();
227 printk("Mapped %ld ITC cells s
228 ((itcblkgrn & 0x7fe000
229 }
230 }
231
232 const struct class mt_class = {
233 .name = "mt",
234 };
235
236 static int __init mips_mt_init(void)
237 {
238 return class_register(&mt_class);
239 }
240
241 subsys_initcall(mips_mt_init);
242
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