1 // SPDX-License-Identifier: GPL-2.0-or-later 1
2 /*
3 * the EHCI Virtual Support Module of AMD CS55
4 *
5 * Copyright (C) 2007 Lemote, Inc.
6 * Author : jlliu, liujl@lemote.com
7 *
8 * Copyright (C) 2009 Lemote, Inc.
9 * Author: Wu Zhangjin, wuzhangjin@gmail.com
10 */
11
12 #include <cs5536/cs5536.h>
13 #include <cs5536/cs5536_pci.h>
14
15 void pci_ehci_write_reg(int reg, u32 value)
16 {
17 u32 hi = 0, lo = value;
18
19 switch (reg) {
20 case PCI_COMMAND:
21 _rdmsr(USB_MSR_REG(USB_EHCI),
22 if (value & PCI_COMMAND_MASTER
23 hi |= PCI_COMMAND_MAST
24 else
25 hi &= ~PCI_COMMAND_MAS
26
27 if (value & PCI_COMMAND_MEMORY
28 hi |= PCI_COMMAND_MEMO
29 else
30 hi &= ~PCI_COMMAND_MEM
31 _wrmsr(USB_MSR_REG(USB_EHCI),
32 break;
33 case PCI_STATUS:
34 if (value & PCI_STATUS_PARITY)
35 _rdmsr(SB_MSR_REG(SB_E
36 if (lo & SB_PARE_ERR_F
37 lo = (lo & 0x0
38 _wrmsr(SB_MSR_
39 }
40 }
41 break;
42 case PCI_BAR0_REG:
43 if (value == PCI_BAR_RANGE_MAS
44 _rdmsr(GLCP_MSR_REG(GL
45 lo |= SOFT_BAR_EHCI_FL
46 _wrmsr(GLCP_MSR_REG(GL
47 } else if ((value & 0x01) == 0
48 _rdmsr(USB_MSR_REG(USB
49 lo = value;
50 _wrmsr(USB_MSR_REG(USB
51
52 value &= 0xfffffff0;
53 hi = 0x40000000 | ((va
54 lo = 0x000fffff | ((va
55 _wrmsr(GLIU_MSR_REG(GL
56 }
57 break;
58 case PCI_EHCI_LEGSMIEN_REG:
59 _rdmsr(USB_MSR_REG(USB_EHCI),
60 hi &= 0x003f0000;
61 hi |= (value & 0x3f) << 16;
62 _wrmsr(USB_MSR_REG(USB_EHCI),
63 break;
64 case PCI_EHCI_FLADJ_REG:
65 _rdmsr(USB_MSR_REG(USB_EHCI),
66 hi &= ~0x00003f00;
67 hi |= value & 0x00003f00;
68 _wrmsr(USB_MSR_REG(USB_EHCI),
69 break;
70 default:
71 break;
72 }
73 }
74
75 u32 pci_ehci_read_reg(int reg)
76 {
77 u32 conf_data = 0;
78 u32 hi, lo;
79
80 switch (reg) {
81 case PCI_VENDOR_ID:
82 conf_data =
83 CFG_PCI_VENDOR_ID(CS5536_E
84 break;
85 case PCI_COMMAND:
86 _rdmsr(USB_MSR_REG(USB_EHCI),
87 if (hi & PCI_COMMAND_MASTER)
88 conf_data |= PCI_COMMA
89 if (hi & PCI_COMMAND_MEMORY)
90 conf_data |= PCI_COMMA
91 break;
92 case PCI_STATUS:
93 conf_data |= PCI_STATUS_66MHZ;
94 conf_data |= PCI_STATUS_FAST_B
95 _rdmsr(SB_MSR_REG(SB_ERROR), &
96 if (lo & SB_PARE_ERR_FLAG)
97 conf_data |= PCI_STATU
98 conf_data |= PCI_STATUS_DEVSEL
99 break;
100 case PCI_CLASS_REVISION:
101 _rdmsr(USB_MSR_REG(USB_CAP), &
102 conf_data = lo & 0x000000ff;
103 conf_data |= (CS5536_EHCI_CLAS
104 break;
105 case PCI_CACHE_LINE_SIZE:
106 conf_data =
107 CFG_PCI_CACHE_LINE_SIZE(PC
108 PC
109 break;
110 case PCI_BAR0_REG:
111 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_
112 if (lo & SOFT_BAR_EHCI_FLAG) {
113 conf_data = CS5536_EHC
114 PCI_BASE_ADDRESS_S
115 lo &= ~SOFT_BAR_EHCI_F
116 _wrmsr(GLCP_MSR_REG(GL
117 } else {
118 _rdmsr(USB_MSR_REG(USB
119 conf_data = lo & 0xfff
120 }
121 break;
122 case PCI_CARDBUS_CIS:
123 conf_data = PCI_CARDBUS_CIS_PO
124 break;
125 case PCI_SUBSYSTEM_VENDOR_ID:
126 conf_data =
127 CFG_PCI_VENDOR_ID(CS5536_E
128 break;
129 case PCI_ROM_ADDRESS:
130 conf_data = PCI_EXPANSION_ROM_
131 break;
132 case PCI_CAPABILITY_LIST:
133 conf_data = PCI_CAPLIST_USB_PO
134 break;
135 case PCI_INTERRUPT_LINE:
136 conf_data =
137 CFG_PCI_INTERRUPT_LINE(PCI
138 break;
139 case PCI_EHCI_LEGSMIEN_REG:
140 _rdmsr(USB_MSR_REG(USB_EHCI),
141 conf_data = (hi & 0x003f0000)
142 break;
143 case PCI_EHCI_LEGSMISTS_REG:
144 _rdmsr(USB_MSR_REG(USB_EHCI),
145 conf_data = (hi & 0x3f000000)
146 break;
147 case PCI_EHCI_FLADJ_REG:
148 _rdmsr(USB_MSR_REG(USB_EHCI),
149 conf_data = hi & 0x00003f00;
150 break;
151 default:
152 break;
153 }
154
155 return conf_data;
156 }
157
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