1 /* 1 /*
2 * Cobalt Qube/Raq PCI support 2 * Cobalt Qube/Raq PCI support
3 * 3 *
4 * This file is subject to the terms and condi 4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the mai 5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details. 6 * for more details.
7 * 7 *
8 * Copyright (C) 1995, 1996, 1997, 2002, 2003 8 * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle
9 * Copyright (C) 2001, 2002, 2003 by Liam Davi 9 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
10 */ 10 */
11 #include <linux/types.h> 11 #include <linux/types.h>
12 #include <linux/pci.h> 12 #include <linux/pci.h>
13 #include <linux/kernel.h> 13 #include <linux/kernel.h>
14 #include <linux/init.h> 14 #include <linux/init.h>
15 15
16 #include <asm/io.h> 16 #include <asm/io.h>
17 #include <asm/gt64120.h> 17 #include <asm/gt64120.h>
18 18
19 #include <cobalt.h> 19 #include <cobalt.h>
20 #include <irq.h> 20 #include <irq.h>
21 21
22 /* 22 /*
23 * PCI slot numbers 23 * PCI slot numbers
24 */ 24 */
25 #define COBALT_PCICONF_CPU 0x06 25 #define COBALT_PCICONF_CPU 0x06
26 #define COBALT_PCICONF_ETH0 0x07 26 #define COBALT_PCICONF_ETH0 0x07
27 #define COBALT_PCICONF_RAQSCSI 0x08 27 #define COBALT_PCICONF_RAQSCSI 0x08
28 #define COBALT_PCICONF_VIA 0x09 28 #define COBALT_PCICONF_VIA 0x09
29 #define COBALT_PCICONF_PCISLOT 0x0A 29 #define COBALT_PCICONF_PCISLOT 0x0A
30 #define COBALT_PCICONF_ETH1 0x0C 30 #define COBALT_PCICONF_ETH1 0x0C
31 31
32 /* 32 /*
33 * The Cobalt board ID information. The board 33 * The Cobalt board ID information. The boards have an ID number wired
34 * into the VIA that is available in the high 34 * into the VIA that is available in the high nibble of register 94.
35 */ 35 */
36 #define VIA_COBALT_BRD_ID_REG 0x94 36 #define VIA_COBALT_BRD_ID_REG 0x94
37 #define VIA_COBALT_BRD_REG_to_ID(reg) ((unsi 37 #define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4)
38 38
39 /* <<
40 * Default value of PCI Class Code on GT64111 <<
41 * instead of PCI_CLASS_BRIDGE_HOST (0x0600). <<
42 * document "GT-64111 System Controller for RC <<
43 * section "6.5.3 PCI Autoconfiguration at RES <<
44 * <<
45 * Some PCs refuse to configure host bridges <<
46 * a PCI slot (ask the BIOS vendors why...). <<
47 * Code does not cause a problem for these n <<
48 * this as the default in the GT-64111. <<
49 * <<
50 * So fix the incorrect default value of PCI C <<
51 * https://lore.kernel.org/r/20211102154831.xt <<
52 * https://lore.kernel.org/r/20211102150201.GA <<
53 */ <<
54 static void qube_raq_galileo_early_fixup(struc 39 static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
55 { 40 {
56 if (dev->devfn == PCI_DEVFN(0, 0) && 41 if (dev->devfn == PCI_DEVFN(0, 0) &&
57 (dev->class >> 8) == PCI_CLASS 42 (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
58 43
59 dev->class = (PCI_CLASS_BRIDGE 44 dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
60 45
61 printk(KERN_INFO "Galileo: fix 46 printk(KERN_INFO "Galileo: fixed bridge class\n");
62 } 47 }
63 } 48 }
64 49
65 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, 50 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
66 qube_raq_galileo_early_fixup); 51 qube_raq_galileo_early_fixup);
67 52
68 static void qube_raq_via_bmIDE_fixup(struct pc 53 static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
69 { 54 {
70 unsigned short cfgword; 55 unsigned short cfgword;
71 unsigned char lt; 56 unsigned char lt;
72 57
73 /* Enable Bus Mastering and fast back 58 /* Enable Bus Mastering and fast back to back. */
74 pci_read_config_word(dev, PCI_COMMAND, 59 pci_read_config_word(dev, PCI_COMMAND, &cfgword);
75 cfgword |= (PCI_COMMAND_FAST_BACK | PC 60 cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
76 pci_write_config_word(dev, PCI_COMMAND 61 pci_write_config_word(dev, PCI_COMMAND, cfgword);
77 62
78 /* Enable both ide interfaces. ROM onl 63 /* Enable both ide interfaces. ROM only enables primary one. */
79 pci_write_config_byte(dev, 0x40, 0xb); 64 pci_write_config_byte(dev, 0x40, 0xb);
80 65
81 /* Set latency timer to reasonable val 66 /* Set latency timer to reasonable value. */
82 pci_read_config_byte(dev, PCI_LATENCY_ 67 pci_read_config_byte(dev, PCI_LATENCY_TIMER, <);
83 if (lt < 64) 68 if (lt < 64)
84 pci_write_config_byte(dev, PCI 69 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
85 pci_write_config_byte(dev, PCI_CACHE_L 70 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
86 } 71 }
87 72
88 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PC 73 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
89 qube_raq_via_bmIDE_fixup); 74 qube_raq_via_bmIDE_fixup);
90 75
91 static void qube_raq_galileo_fixup(struct pci_ 76 static void qube_raq_galileo_fixup(struct pci_dev *dev)
92 { 77 {
93 if (dev->devfn != PCI_DEVFN(0, 0)) 78 if (dev->devfn != PCI_DEVFN(0, 0))
94 return; 79 return;
95 80
96 /* Fix PCI latency-timer and cache-lin 81 /* Fix PCI latency-timer and cache-line-size values in Galileo
97 * host bridge. 82 * host bridge.
98 */ 83 */
99 pci_write_config_byte(dev, PCI_LATENCY 84 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
100 pci_write_config_byte(dev, PCI_CACHE_L 85 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
101 86
102 /* 87 /*
103 * The code described by the comment b 88 * The code described by the comment below has been removed
104 * as it causes bus mastering by the E 89 * as it causes bus mastering by the Ethernet controllers
105 * to break under any kind of network 90 * to break under any kind of network load. We always set
106 * the retry timeouts to their maximum 91 * the retry timeouts to their maximum.
107 * 92 *
108 * --x--x--x--x--x--x--x--x--x--x--x-- 93 * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
109 * 94 *
110 * On all machines prior to Q2, we had 95 * On all machines prior to Q2, we had the STOP line disconnected
111 * from Galileo to VIA on PCI. The ne 96 * from Galileo to VIA on PCI. The new Galileo does not function
112 * correctly unless we have it connect 97 * correctly unless we have it connected.
113 * 98 *
114 * Therefore we must set the disconnec 99 * Therefore we must set the disconnect/retry cycle values to
115 * something sensible when using the n 100 * something sensible when using the new Galileo.
116 */ 101 */
117 102
118 printk(KERN_INFO "Galileo: revision %u 103 printk(KERN_INFO "Galileo: revision %u\n", dev->revision);
119 104
120 #if 0 105 #if 0
121 if (dev->revision >= 0x10) { 106 if (dev->revision >= 0x10) {
122 /* New Galileo, assumes PCI st 107 /* New Galileo, assumes PCI stop line to VIA is connected. */
123 GT_WRITE(GT_PCI0_TOR_OFS, 0x40 108 GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);
124 } else if (dev->revision == 0x1 || dev 109 } else if (dev->revision == 0x1 || dev->revision == 0x2)
125 #endif 110 #endif
126 { 111 {
127 signed int timeo; 112 signed int timeo;
128 /* XXX WE MUST DO THIS ELSE GA 113 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
129 timeo = GT_READ(GT_PCI0_TOR_OF 114 timeo = GT_READ(GT_PCI0_TOR_OFS);
130 /* Old Galileo, assumes PCI ST 115 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
131 GT_WRITE(GT_PCI0_TOR_OFS, 116 GT_WRITE(GT_PCI0_TOR_OFS,
132 (0xff << 16) | 117 (0xff << 16) | /* retry count */
133 (0xff << 8) | 118 (0xff << 8) | /* timeout 1 */
134 0xff); 119 0xff); /* timeout 0 */
135 120
136 /* enable PCI retry exceeded i 121 /* enable PCI retry exceeded interrupt */
137 GT_WRITE(GT_INTRMASK_OFS, GT_I 122 GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS));
138 } 123 }
139 } 124 }
140 125
141 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL 126 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
142 qube_raq_galileo_fixup); 127 qube_raq_galileo_fixup);
143 128
144 int cobalt_board_id; 129 int cobalt_board_id;
145 130
146 static void qube_raq_via_board_id_fixup(struct 131 static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
147 { 132 {
148 u8 id; 133 u8 id;
149 int retval; 134 int retval;
150 135
151 retval = pci_read_config_byte(dev, VIA 136 retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id);
152 if (retval) { 137 if (retval) {
153 panic("Cannot read board ID"); 138 panic("Cannot read board ID");
154 return; 139 return;
155 } 140 }
156 141
157 cobalt_board_id = VIA_COBALT_BRD_REG_t 142 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id);
158 143
159 printk(KERN_INFO "Cobalt board ID: %d\ 144 printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id);
160 } 145 }
161 146
162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PC 147 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
163 qube_raq_via_board_id_fixup); 148 qube_raq_via_board_id_fixup);
164 149
165 static char irq_tab_qube1[] = { 150 static char irq_tab_qube1[] = {
166 [COBALT_PCICONF_CPU] = 0, 151 [COBALT_PCICONF_CPU] = 0,
167 [COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ, 152 [COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ,
168 [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ, 153 [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
169 [COBALT_PCICONF_VIA] = 0, 154 [COBALT_PCICONF_VIA] = 0,
170 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, 155 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
171 [COBALT_PCICONF_ETH1] = 0 156 [COBALT_PCICONF_ETH1] = 0
172 }; 157 };
173 158
174 static char irq_tab_cobalt[] = { 159 static char irq_tab_cobalt[] = {
175 [COBALT_PCICONF_CPU] = 0, 160 [COBALT_PCICONF_CPU] = 0,
176 [COBALT_PCICONF_ETH0] = ETH0_IRQ, 161 [COBALT_PCICONF_ETH0] = ETH0_IRQ,
177 [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ, 162 [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
178 [COBALT_PCICONF_VIA] = 0, 163 [COBALT_PCICONF_VIA] = 0,
179 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, 164 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
180 [COBALT_PCICONF_ETH1] = ETH1_IRQ 165 [COBALT_PCICONF_ETH1] = ETH1_IRQ
181 }; 166 };
182 167
183 static char irq_tab_raq2[] = { 168 static char irq_tab_raq2[] = {
184 [COBALT_PCICONF_CPU] = 0, 169 [COBALT_PCICONF_CPU] = 0,
185 [COBALT_PCICONF_ETH0] = ETH0_IRQ, 170 [COBALT_PCICONF_ETH0] = ETH0_IRQ,
186 [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ, 171 [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
187 [COBALT_PCICONF_VIA] = 0, 172 [COBALT_PCICONF_VIA] = 0,
188 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, 173 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
189 [COBALT_PCICONF_ETH1] = ETH1_IRQ 174 [COBALT_PCICONF_ETH1] = ETH1_IRQ
190 }; 175 };
191 176
192 int pcibios_map_irq(const struct pci_dev *dev, 177 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
193 { 178 {
194 if (cobalt_board_id <= COBALT_BRD_ID_Q 179 if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
195 return irq_tab_qube1[slot]; 180 return irq_tab_qube1[slot];
196 181
197 if (cobalt_board_id == COBALT_BRD_ID_R 182 if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
198 return irq_tab_raq2[slot]; 183 return irq_tab_raq2[slot];
199 184
200 return irq_tab_cobalt[slot]; 185 return irq_tab_cobalt[slot];
201 } 186 }
202 187
203 /* Do platform specific device initialization 188 /* Do platform specific device initialization at pci_enable_device() time */
204 int pcibios_plat_dev_init(struct pci_dev *dev) 189 int pcibios_plat_dev_init(struct pci_dev *dev)
205 { 190 {
206 return 0; 191 return 0;
207 } 192 }
208 193
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