1 // SPDX-License-Identifier: GPL-2.0 1
2 #include <linux/init.h>
3 #include <linux/pci.h>
4 #include <asm/mips-boards/piix4.h>
5
6 /* PCI interrupt pins */
7 #define PCIA 1
8 #define PCIB 2
9 #define PCIC 3
10 #define PCID 4
11
12 /* This table is filled in by interrogating th
13 static char pci_irq[5] = {
14 };
15
16 static char irq_tab[][5] = {
17 /* INTA INTB INTC INTD *
18 {0, 0, 0, 0, 0 },
19 {0, 0, 0, 0, 0 },
20 {0, 0, 0, 0, 0 },
21 {0, 0, 0, 0, 0 },
22 {0, 0, 0, 0, 0 },
23 {0, 0, 0, 0, 0 },
24 {0, 0, 0, 0, 0 },
25 {0, 0, 0, 0, 0 },
26 {0, 0, 0, 0, 0 },
27 {0, 0, 0, 0, 0 },
28 {0, 0, 0, 0, PCID }
29 {0, PCIB, 0, 0, 0 },
30 {0, PCIC, 0, 0, 0 },
31 {0, 0, 0, 0, 0 },
32 {0, 0, 0, 0, 0 },
33 {0, 0, 0, 0, 0 },
34 {0, 0, 0, 0, 0 },
35 {0, 0, 0, 0, 0 },
36 {0, PCIA, PCIB, PCIC, PCID }
37 {0, PCIB, PCIC, PCID, PCIA }
38 {0, PCIC, PCID, PCIA, PCIB }
39 {0, PCID, PCIA, PCIB, PCIC }
40 };
41
42 int pcibios_map_irq(const struct pci_dev *dev,
43 {
44 int virq;
45 virq = irq_tab[slot][pin];
46 return pci_irq[virq];
47 }
48
49 /* Do platform specific device initialization
50 int pcibios_plat_dev_init(struct pci_dev *dev)
51 {
52 return 0;
53 }
54
55 static void malta_piix_func3_base_fixup(struct
56 {
57 /* Set a sane PM I/O base address */
58 pci_write_config_word(dev, PIIX4_FUNC3
59
60 /* Enable access to the PM I/O region
61 pci_write_config_byte(dev, PIIX4_FUNC3
62 PIIX4_FUNC3_PMRE
63 }
64
65 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, P
66 malta_piix_func3_base_
67
68 static void malta_piix_func0_fixup(struct pci_
69 {
70 unsigned char reg_val;
71 u32 reg_val32;
72 u16 reg_val16;
73 /* PIIX PIRQC[A:D] irq mappings */
74 static int piixirqmap[PIIX4_FUNC0_PIRQ
75 0, 0, 0, 3,
76 4, 5, 6, 7,
77 0, 9, 10, 11,
78 12, 0, 14, 15
79 };
80 int i;
81
82 /* Interrogate PIIX4 to get PCI IRQ ma
83 for (i = 0; i <= 3; i++) {
84 pci_read_config_byte(pdev, PII
85 if (reg_val & PIIX4_FUNC0_PIRQ
86 pci_irq[PCIA+i] = 0;
87 else
88 pci_irq[PCIA+i] = piix
89 PIIX4_FUNC0_PI
90 }
91
92 /* Done by YAMON 2.00 onwards */
93 if (PCI_SLOT(pdev->devfn) == 10) {
94 /*
95 * Set top of main memory acce
96 * devices to 16 Mb.
97 */
98 pci_read_config_byte(pdev, PII
99 pci_write_config_byte(pdev, PI
100 PIIX4_FUNC0_TO
101 }
102
103 /* Mux SERIRQ to its pin */
104 pci_read_config_dword(pdev, PIIX4_FUNC
105 pci_write_config_dword(pdev, PIIX4_FUN
106 reg_val32 | PII
107
108 /* Enable SERIRQ */
109 pci_read_config_byte(pdev, PIIX4_FUNC0
110 reg_val |= PIIX4_FUNC0_SERIRQC_EN | PI
111 pci_write_config_byte(pdev, PIIX4_FUNC
112
113 /* Enable response to special cycles *
114 pci_read_config_word(pdev, PCI_COMMAND
115 pci_write_config_word(pdev, PCI_COMMAN
116 reg_val16 | PCI_
117 }
118
119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,
120 malta_piix_func0_fixup);
121
122 static void malta_piix_func1_fixup(struct pci_
123 {
124 unsigned char reg_val;
125
126 /* Done by YAMON 2.02 onwards */
127 if (PCI_SLOT(pdev->devfn) == 10) {
128 /*
129 * IDE Decode enable.
130 */
131 pci_read_config_byte(pdev, PII
132 ®_val);
133 pci_write_config_byte(pdev, PI
134 reg_val|PIIX4_FUNC1_ID
135 pci_read_config_byte(pdev, PII
136 ®_val);
137 pci_write_config_byte(pdev, PI
138 reg_val|PIIX4_FUNC1_ID
139 }
140 }
141
142 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,
143 malta_piix_func1_fixup);
144
145 /* Enable PCI 2.1 compatibility in PIIX4 */
146 static void quirk_dlcsetup(struct pci_dev *dev
147 {
148 u8 odlc, ndlc;
149
150 (void) pci_read_config_byte(dev, PIIX4
151 /* Enable passive releases and delayed
152 ndlc = odlc | PIIX4_FUNC0_DLC_USBPR_EN
153 PIIX4_FUNC0_DLC_PASSIVE_
154 PIIX4_FUNC0_DLC_DELAYED_
155 (void) pci_write_config_byte(dev, PIIX
156 }
157
158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, P
159 quirk_dlcsetup);
160
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