1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "Platform options"
3
4 comment "Memory settings"
5
6 config NIOS2_MEM_BASE
7 hex "Memory base address"
8 default "0x00000000"
9 help
10 This is the physical address of the
11 from. This address is used to link t
12 management. You should take the raw
13 or cache bits set.
14 Please not that this address is used
15 do address translation if it's conne
16
17 comment "Device tree"
18
19 config NIOS2_DTB_AT_PHYS_ADDR
20 bool "DTB at physical address"
21 help
22 When enabled you can select a physic
23 Normally this address is passed by a
24 using this you can use a devicetree
25 This way you can store a devicetree
26 Please note that this address is use
27 do address translation if it's conne
28 account that when using an MMU you'd
29 address
30
31 config NIOS2_DTB_PHYS_ADDR
32 hex "DTB Address"
33 depends on NIOS2_DTB_AT_PHYS_ADDR
34 default "0xC0000000"
35 help
36 Physical address of a dtb blob.
37
38 config NIOS2_DTB_SOURCE_BOOL
39 bool "Compile and link device tree int
40 depends on !COMPILE_TEST
41 help
42 This allows you to specify a dts (de
43 which will be compiled and linked in
44
45 config NIOS2_DTB_SOURCE
46 string "Device tree source file"
47 depends on NIOS2_DTB_SOURCE_BOOL
48 default ""
49 help
50 Absolute path to the device tree sou
51 system.
52
53 comment "Nios II instructions"
54
55 config NIOS2_ARCH_REVISION
56 int "Select Nios II architecture revis
57 range 1 2
58 default 1
59 help
60 Select between Nios II R1 and Nios I
61 are binary incompatible. Default is
62
63 config NIOS2_HW_MUL_SUPPORT
64 bool "Enable MUL instruction"
65 help
66 Set to true if you configured the Ni
67 instruction. This will enable the -
68
69 config NIOS2_HW_MULX_SUPPORT
70 bool "Enable MULX instruction"
71 help
72 Set to true if you configured the Ni
73 instruction. Enables the -mhw-mulx
74
75 config NIOS2_HW_DIV_SUPPORT
76 bool "Enable DIV instruction"
77 help
78 Set to true if you configured the Ni
79 instruction. Enables the -mhw-div c
80
81 config NIOS2_BMX_SUPPORT
82 bool "Enable BMX instructions"
83 depends on NIOS2_ARCH_REVISION = 2
84 help
85 Set to true if you configured the Ni
86 the BMX Bit Manipulation Extension i
87 the -mbmx compiler flag.
88
89 config NIOS2_CDX_SUPPORT
90 bool "Enable CDX instructions"
91 depends on NIOS2_ARCH_REVISION = 2
92 help
93 Set to true if you configured the Ni
94 the CDX Bit Manipulation Extension i
95 the -mcdx compiler flag.
96
97 config NIOS2_FPU_SUPPORT
98 bool "Custom floating point instr supp
99 help
100 Enables the -mcustom-fpu-cfg=60-1 co
101
102 config NIOS2_CI_SWAB_SUPPORT
103 bool "Byteswap custom instruction"
104 help
105 Use the byteswap (endian converter)
106 by Altera and which can be enabled i
107 endian conversions in the kernel (e.
108
109 config NIOS2_CI_SWAB_NO
110 int "Byteswap custom instruction numbe
111 default 0
112 help
113 Number of the instruction as configu
114
115 comment "Cache settings"
116
117 config CUSTOM_CACHE_SETTINGS
118 bool "Custom cache settings"
119 help
120 This option allows you to tweak the
121 boot (where the information from dev
122 There should be no reason to change
123 perfectly fine, even if the Nios II
124
125 Say N here unless you know what you
126
127 config NIOS2_DCACHE_SIZE
128 hex "D-Cache size" if CUSTOM_CACHE_SET
129 range 0x200 0x10000
130 default "0x800"
131 help
132 Maximum possible data cache size.
133
134 config NIOS2_DCACHE_LINE_SIZE
135 hex "D-Cache line size" if CUSTOM_CACH
136 range 0x10 0x20
137 default "0x20"
138 help
139 Minimum possible data cache line siz
140
141 config NIOS2_ICACHE_SIZE
142 hex "I-Cache size" if CUSTOM_CACHE_SET
143 range 0x200 0x10000
144 default "0x1000"
145 help
146 Maximum possible instruction cache s
147
148 endmenu
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