1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0 2 # !! 2 config M68K 3 # For a description of the syntax of this conf !! 3 bool 4 # see Documentation/kbuild/kconfig-language.rs !! 4 default y 5 # << 6 << 7 config OPENRISC << 8 def_bool y << 9 select ARCH_32BIT_OFF_T 5 select ARCH_32BIT_OFF_T 10 select ARCH_HAS_DMA_SET_UNCACHED !! 6 select ARCH_HAS_BINFMT_FLAT 11 select ARCH_HAS_DMA_CLEAR_UNCACHED !! 7 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE !! 8 select ARCH_HAS_CURRENT_STACK_POINTER 13 select COMMON_CLK !! 9 select ARCH_HAS_DMA_PREP_COHERENT if HAS_DMA && MMU && !COLDFIRE 14 select OF !! 10 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if HAS_DMA 15 select OF_EARLY_FLATTREE !! 11 select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS 16 select IRQ_DOMAIN !! 12 select ARCH_MIGHT_HAVE_PC_PARPORT if ISA 17 select GPIOLIB !! 13 select ARCH_NO_PREEMPT if !COLDFIRE 18 select HAVE_ARCH_TRACEHOOK !! 14 select ARCH_USE_MEMTEST if MMU_MOTOROLA 19 select SPARSE_IRQ !! 15 select ARCH_WANT_IPC_PARSE_VERSION 20 select GENERIC_IRQ_CHIP !! 16 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 21 select GENERIC_IRQ_PROBE !! 17 select DMA_DIRECT_REMAP if HAS_DMA && MMU && !COLDFIRE 22 select GENERIC_IRQ_SHOW !! 18 select GENERIC_ATOMIC64 23 select GENERIC_PCI_IOMAP << 24 select GENERIC_IOREMAP << 25 select GENERIC_CPU_DEVICES 19 select GENERIC_CPU_DEVICES 26 select HAVE_PCI !! 20 select GENERIC_IOMAP >> 21 select GENERIC_IRQ_SHOW >> 22 select HAS_IOPORT if PCI || ISA || ATARI_ROM_ISA >> 23 select HAVE_ARCH_SECCOMP >> 24 select HAVE_ARCH_SECCOMP_FILTER >> 25 select HAVE_ASM_MODVERSIONS >> 26 select HAVE_DEBUG_BUGVERBOSE >> 27 select HAVE_EFFICIENT_UNALIGNED_ACCESS if !CPU_HAS_NO_UNALIGNED >> 28 select HAVE_MOD_ARCH_SPECIFIC 27 select HAVE_UID16 29 select HAVE_UID16 28 select HAVE_PAGE_SIZE_8KB << 29 select GENERIC_ATOMIC64 << 30 select GENERIC_CLOCKEVENTS_BROADCAST << 31 select GENERIC_SMP_IDLE_THREAD << 32 select MODULES_USE_ELF_RELA << 33 select HAVE_DEBUG_STACKOVERFLOW << 34 select OR1K_PIC << 35 select CPU_NO_EFFICIENT_FFS if !OPENRI << 36 select ARCH_USE_QUEUED_RWLOCKS << 37 select OMPIC if SMP << 38 select PCI_DOMAINS_GENERIC if PCI << 39 select PCI_MSI if PCI << 40 select ARCH_WANT_FRAME_POINTERS << 41 select GENERIC_IRQ_MULTI_HANDLER << 42 select MMU_GATHER_NO_RANGE if MMU 30 select MMU_GATHER_NO_RANGE if MMU 43 select TRACE_IRQFLAGS_SUPPORT !! 31 select MODULES_USE_ELF_REL >> 32 select MODULES_USE_ELF_RELA >> 33 select NO_DMA if !MMU && !COLDFIRE >> 34 select OLD_SIGACTION >> 35 select OLD_SIGSUSPEND3 >> 36 select UACCESS_MEMCPY if !MMU >> 37 select ZONE_DMA 44 38 45 config CPU_BIG_ENDIAN 39 config CPU_BIG_ENDIAN 46 def_bool y 40 def_bool y 47 41 48 config MMU !! 42 config ARCH_HAS_ILOG2_U32 49 def_bool y !! 43 bool >> 44 >> 45 config ARCH_HAS_ILOG2_U64 >> 46 bool 50 47 51 config GENERIC_HWEIGHT 48 config GENERIC_HWEIGHT 52 def_bool y !! 49 bool >> 50 default y 53 51 54 config NO_IOPORT_MAP !! 52 config GENERIC_CALIBRATE_DELAY 55 def_bool y !! 53 bool >> 54 default y 56 55 57 # For now, use generic checksum functions << 58 #These can be reimplemented in assembly later << 59 config GENERIC_CSUM 56 config GENERIC_CSUM 60 def_bool y !! 57 bool 61 << 62 config STACKTRACE_SUPPORT << 63 def_bool y << 64 << 65 config LOCKDEP_SUPPORT << 66 def_bool y << 67 << 68 menu "Processor type and features" << 69 << 70 choice << 71 prompt "Subarchitecture" << 72 default OR1K_1200 << 73 << 74 config OR1K_1200 << 75 bool "OR1200" << 76 help << 77 Generic OpenRISC 1200 architecture << 78 << 79 endchoice << 80 << 81 config DCACHE_WRITETHROUGH << 82 bool "Have write through data caches" << 83 default n << 84 help << 85 Select this if your implementation f << 86 Selecting 'N' here will allow the ke << 87 caches at relevant times. Most OpenR << 88 through data caches. << 89 << 90 If unsure say N here << 91 << 92 config OPENRISC_BUILTIN_DTB << 93 string "Builtin DTB" << 94 default "" << 95 58 96 menu "Class II Instructions" !! 59 config TIME_LOW_RES 97 !! 60 bool 98 config OPENRISC_HAVE_INST_FF1 << 99 bool "Have instruction l.ff1" << 100 default y 61 default y 101 help << 102 Select this if your implementation h << 103 62 104 config OPENRISC_HAVE_INST_FL1 !! 63 config NO_IOPORT_MAP 105 bool "Have instruction l.fl1" !! 64 def_bool y 106 default y << 107 help << 108 Select this if your implementation h << 109 65 110 config OPENRISC_HAVE_INST_MUL !! 66 config HZ 111 bool "Have instruction l.mul for hardw !! 67 int 112 default y !! 68 default 1000 if CLEOPATRA 113 help !! 69 default 100 114 Select this if your implementation h !! 70 >> 71 config PGTABLE_LEVELS >> 72 default 2 if SUN3 || COLDFIRE >> 73 default 3 115 74 116 config OPENRISC_HAVE_INST_DIV !! 75 config MMU 117 bool "Have instruction l.div for hardw !! 76 bool "MMU-based Paged Memory Management Support" 118 default y 77 default y 119 help 78 help 120 Select this if your implementation h !! 79 Select if you want MMU-based virtualised addressing space 121 !! 80 support by paged memory management. If unsure, say 'Y'. 122 config OPENRISC_HAVE_INST_CMOV << 123 bool "Have instruction l.cmov for cond << 124 default n << 125 help << 126 This config enables gcc to generate << 127 the kernel which in general will imp << 128 binary size. << 129 << 130 Select this if your implementation h << 131 l.cmov conistional move instruction. << 132 << 133 Say N if you are unsure. << 134 << 135 config OPENRISC_HAVE_INST_ROR << 136 bool "Have instruction l.ror for rotat << 137 default n << 138 help << 139 This config enables gcc to generate << 140 the kernel which in general will imp << 141 binary size. << 142 << 143 Select this if your implementation h << 144 l.ror rotate right instruction. << 145 << 146 Say N if you are unsure. << 147 << 148 config OPENRISC_HAVE_INST_RORI << 149 bool "Have instruction l.rori for rota << 150 default n << 151 help << 152 This config enables gcc to generate << 153 the kernel which in general will imp << 154 binary size. << 155 << 156 Select this if your implementation h << 157 l.rori rotate right with immediate i << 158 << 159 Say N if you are unsure. << 160 << 161 config OPENRISC_HAVE_INST_SEXT << 162 bool "Have instructions l.ext* for sig << 163 default n << 164 help << 165 This config enables gcc to generate << 166 the kernel which in general will imp << 167 binary size. << 168 << 169 Select this if your implementation h << 170 l.exths, l.extbs, l.exthz and l.extb << 171 81 172 Say N if you are unsure. !! 82 config MMU_MOTOROLA >> 83 bool 173 84 174 endmenu !! 85 config MMU_COLDFIRE 175 !! 86 bool 176 config NR_CPUS << 177 int "Maximum number of CPUs (2-32)" << 178 range 2 32 << 179 depends on SMP << 180 default "2" << 181 87 182 config SMP !! 88 config MMU_SUN3 183 bool "Symmetric Multi-Processing suppo !! 89 bool 184 help !! 90 depends on MMU && !MMU_MOTOROLA && !MMU_COLDFIRE 185 This enables support for systems wit << 186 a system with only one CPU, say N. I << 187 than one CPU, say Y. << 188 91 189 If you don't know what to do here, s !! 92 config ARCH_SUPPORTS_KEXEC >> 93 def_bool M68KCLASSIC && MMU 190 94 191 config FPU !! 95 config BOOTINFO_PROC 192 bool "FPU support" !! 96 bool "Export bootinfo in procfs" 193 default y !! 97 depends on KEXEC && M68KCLASSIC 194 help 98 help 195 Say N here if you want to disable al !! 99 Say Y to export the bootinfo used to boot the kernel in a 196 in the kernel and reduce binary size !! 100 "bootinfo" file in procfs. This is useful with kexec. 197 101 198 If you don't know what to do here, s !! 102 menu "Platform setup" 199 103 200 source "kernel/Kconfig.hz" !! 104 source "arch/m68k/Kconfig.cpu" 201 105 202 config OPENRISC_NO_SPR_SR_DSX !! 106 source "arch/m68k/Kconfig.machine" 203 bool "use SPR_SR_DSX software emulatio << 204 default y << 205 help << 206 SPR_SR_DSX bit is status register bi << 207 the last exception has happened in d << 208 107 209 OpenRISC architecture makes it optio !! 108 source "arch/m68k/Kconfig.bus" 210 in hardware and the OR1200 does not << 211 109 212 Say N here if you know that your Ope !! 110 endmenu 213 SPR_SR_DSX bit implemented. Say Y if << 214 << 215 config OPENRISC_HAVE_SHADOW_GPRS << 216 bool "Support for shadow gpr files" if << 217 default y if SMP << 218 help << 219 Say Y here if your OpenRISC processo << 220 register files. They will in such ca << 221 scratch reg storage on exception ent << 222 << 223 On SMP systems, this feature is mand << 224 On a unicore system it's safe to say << 225 << 226 config CMDLINE << 227 string "Default kernel command string" << 228 default "" << 229 help << 230 On some architectures there is curre << 231 to pass arguments to the kernel. For << 232 supply some command-line options at << 233 here. << 234 111 235 menu "Debugging options" !! 112 menu "Kernel Features" 236 113 237 config JUMP_UPON_UNHANDLED_EXCEPTION !! 114 endmenu 238 bool "Try to die gracefully" << 239 default y << 240 help << 241 Now this puts kernel into infinite l << 242 your kernel crashes this doesn't hav << 243 115 244 Say Y if you are unsure. !! 116 if !MMU >> 117 menu "Power management options" 245 118 246 config OPENRISC_ESR_EXCEPTION_BUG_CHECK !! 119 config PM 247 bool "Check for possible ESR exception !! 120 bool "Power Management support" 248 default n << 249 help 121 help 250 This option enables some checks that !! 122 Support processor power management modes 251 in kernel. << 252 << 253 Say N if you are unsure. << 254 123 255 endmenu 124 endmenu >> 125 endif 256 126 257 endmenu !! 127 source "arch/m68k/Kconfig.devices"
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